JPH05343632A - Cmos element and process - Google Patents

Abstract

PURPOSE: To provide a CMOS element where silicification contact parts are provided for source and drain regions, without dropping the resistance of a silicon gate electrode and a mutual connection part and generating undesired shift of threshold voltage. CONSTITUTION: A CMOS element 10 is constituted of an NMOS transistor 12 and a PMOS transistor 14. The respective transistors have silicification source and drain electrodes 28 and 44 and silicon gate electrodes 24 and 40, containing titanium nitride barrier layers. The transistors are mutually connected by silicon layers covered by the layers of titanium nitride barrier materials. The source and drain regions are silicified by silicified cobalt and other silicified metals, whose reaction with the silicon gate electrode is inhibited, and they are mutually connected by the existence of the titanium nitride barrier layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a CMOS device and a method for manufacturing the CMOS device, and more particularly to a silicided CMOS device and its manufacturing process.

[0002]

BACKGROUND OF THE INVENTION In the manufacture of many CMOS integrated circuits, multiple gate electrodes and materials are often used to interconnect the various devices to be combined to perform the functions of the integrated circuits. Use crystalline or amorphous silicon. Polycrystalline silicon is heavily doped with conductivity-determining impurities to increase the conductivity of this material, thereby increasing the speed of the circuit, increasing the transconductance of individual transistors, or the performance of the circuit. To improve. However, the heavily doped thin silicon layer still has considerable resistance,
In order to achieve the optimum circuit speed, it must be suppressed. The resistance of thin silicon layers can be lowered to acceptable levels by forming a silicide layer on the silicon. The presence of the silicide layer at the contact point with the semiconductor substrate can also improve the contact resistance between the substrate region and the interconnect means. However, providing a silicide layer on a thin layer of silicon causes an unacceptable shift in the critical device parameters. To understand this, it should be noted that the threshold voltage of a silicon gate MOS transistor is determined by the level of impurity doping in the silicon gate electrode. , A work function between the gate electrode and the underlying substrate (work fun)
This is because the action) is determined. P channel M
Generally, a P-type additive is added to the gate electrode of the OS transistor, and an N-type additive is added to the gate electrode of the N-channel transistor. The gate electrodes of N-channel and P-channel transistors are often connected together by patterned portions of the same thin silicon layer from which these gate electrodes are made. This interconnection between the gate electrodes of the different elements is the usual interconnection of the elements for carrying out the intended circuit function. The diffusion of additive impurities is greatly accelerated in the silicided silicon layer. As a result, the added impurities diffuse rapidly through the silicon silicide layer, which causes P
The detrimental result is that the gate electrode of the channel transistor is doped with a rapidly moving N-type dopant, which in the case of an N-channel transistor causes the opposite phenomenon. This charges the threshold voltage of the P-channel transistor, for example, to an unacceptably high value.

Accordingly, there is a need for a method of providing silicided contacts in the source and drain regions without reducing the resistance of the silicon gate electrode and the interconnect and causing undesirable shifts in the threshold voltage.

[0004]

Disclosed is a device and a method of making the device, wherein a conductive barrier layer is formed on the silicon gate electrode prior to forming the metallic silica article on the source and drain regions. It is formed. According to one embodiment of the invention, a CMOS device is provided, the device comprising a first P-channel MOS transistor having a first source and drain region in contact with a metal silicide and a first silicon gate electrode having a titanium nitride layer. Have. The device further comprises a second N-channel MOS transistor, the transistor also comprising a second layer having a titanium nitride layer and source and drain regions in contact with the metal silicide.
It has a silicon gate electrode. Interconnect means including a silicon layer having an upper layer of titanium nitride is provided to couple the first and second gate electrodes.

[0005]

1 is a sectional view of a portion 10 of a CMOS integrated circuit according to the present invention. Part 10 of this integrated circuit is
N-channel MOS transistor 12 and P-channel M
It has an OS transistor 14. A practical integrated circuit will have many such components properly interconnected to achieve the desired circuit function. N-channel transistor 12 is formed in P-type surface region 16 of a single crystal silicon substrate. N-type source and drain regions 18 are formed in the P-type surface region 16, and these regions are separated by a channel region 20. The channel region 20 located above is a gate insulator 22 and a silicon gate electrode 24. The gate electrode 24 is polycrystalline silicon or amorphous silicon, but for the purpose of this description, it will be referred to below as a polycrystalline silicon gate electrode. According to the present invention, the upper gate electrode 24
Is layer 26 of conductive barrier layer 26, such as a titanium nitride layer. Further, in accordance with the present invention, the source and drain regions 18 are contacted by a metal silicide 28 which is spaced from the gate electrode 24 by sidewall spacers 30. Similarly, P channel M
The OS transistor 14 is formed in the N-type surface region 32,
It has P-type source and drain regions 34 separated by a channel region 36. The upper channel region 36 is a gate insulator 38 and a silicon gate electrode 40. According to the invention, a conductive barrier layer 42, such as a titanium nitride layer, overlies the gate electrode 40. Further in accordance with the present invention, the source and drain regions 34 are contacted by a metal silicide 44 which is spaced from the gate electrode 40 by sidewall spacers 46.

FIG. 2 is a plan view schematically showing how two elements such as 12 and 14 are connected together as part of performing the function of the circuit. As shown, N-channel MOS transistor 12 is coupled to P-channel MOS transistor 14 by an interconnect 48 that couples gate electrode 24 of element 12 to gate electrode 40 of element 14. In the case of this embodiment, the element 12 has a P bounded by a dotted line 50.
It is formed in the mold well region 16. Although the invention thus shows a P-well structure, the invention is equally applicable to N-well or twin-well structures. The gate electrode 24 of the element 12 is heavily doped with N-type impurities, and the gate electrode 42 is heavily doped with P-type impurities. According to the present invention, gate electrodes 24 and 40 and interconnect 48 are covered by a layer of conductive barrier material such as titanium nitride. Either side of the gate electrode 24 is an N-type source and drain region 18,
On either side of the gate electrode 40 is a P-type source and drain region 34. The resistance of the gate electrodes and interconnects is lowered by titanium nitride or other conductive barrier materials to values lower than can be achieved by doped polycrystalline silicon alone.

3 to 6 are sectional views showing the manufacturing steps according to an embodiment of the present invention. At the stage of the process shown, an N-channel MO such as transistor 12
A part of the S transistor is formed. P channel MO
Reference is also made to the additional steps required to form the S-transistor, but a detailed description and illustration of these additional steps is not necessary to understanding the process according to the present invention.

As shown in FIG. 3, the process of forming the N-channel MOS transistor portion of the CMOS integrated circuit is initiated by the silicon substrate having the P-type surface region 16. The overlying substrate 16 is a layer of gate insulator 52, which is preferably a layer of thermally grown silicon dioxide having a thickness of 10 to 30 nanometers. The upper gate insulator 32 is a layer of undoped polycrystalline silicon 54 and a layer of conductive barrier material 56. The polycrystalline silicon layer 54 is preferably deposited by chemical vapor deposition to a thickness of 200 to 400 nanometers. Barrier material 56 is preferably titanium nitride, which is provided on the upper surface of polycrystalline silicon layer 54 by reactive sputtering or chemical vapor deposition. This barrier material 56, referred to below as silicon nitride, has a thickness of about 30 to 200 nanometers.

As shown in FIG. 4, in this step, the polycrystalline silicon layer 54 and the titanium nitride layer 56 are patterned to form a polycrystalline silicon gate electrode 24, and an upper portion of the gate electrode 24 is formed. A titanium nitride barrier layer 26 is formed. The patterning of layers 54 and 56 is accomplished by conventional photolithography and etching. At the same time, the gate electrode 24 and the silicon nitride layer 26 formed thereon are formed.
Patterning is performed, and the gate electrode and polycrystalline silicon interconnect lines of other devices used to implement this circuit are also patterned. Therefore, the P-channel transistor and N that form the function of this circuit.
The gate electrode of the channel transistor is formed of undoped polycrystalline silicon on which the titanium nitride barrier layer is formed. In addition, the same layers of polycrystalline silicon and titanium nitride are used to interconnect many of the devices on the circuit.

Source and drain regions 18 are then formed in P-type surface region 16 by selectively introducing N-type additive into the substrate using gate electrode 24 and titanium nitride layer 26 as a mask for the additive. To be done.

These additives can be introduced by using a photoresist to mask the P-channel MOS transistor of the circuit during ion implantation, and implanting ions that determine the N-type conductivity. desirable. Therefore, the N-type additive is introduced only into the source and drain regions of the N-channel MOS transistor. In another stage (not shown), P-type doping impurities are also introduced into the substrate in a selective manner to form the source and drain regions of the P-channel MOS transistor being manufactured. While introducing these P-type impurities into the P-channel source and drain regions, the N-channel transistor is protected from its introduction, for example by overlaying the N-channel transistor with a patterned layer of photoresist. It

The embodiment shown in FIGS. 3 to 6 is an LD.
Figure 4 shows a DMOS structure, where a lightly doped drain region is self-aligned with the gate electrode, and subsequently a more heavily doped drain region is provided away from the gate electrode. Although not shown, these devices can be formed without the optional lightly doped drain structure, so that the source and drain regions 18 are
A large amount of type impurities are added. Often, the LDD structure is used only on N-channel devices, with the associated P-channel device formed by one heavily doped drain region. The selection of such a drain structure can easily be devised within the invention, since the exact structure of the source and drain regions is not limited by the invention itself.

As shown in FIG. 5, in this step, the sidewall spacer 30 is subsequently formed at the end of the gate electrode.
These sidewall spacers are formed from materials such as low temperature oxide (LTO) or other materials such as silicon nitride and the like. The material forming the spacers is deposited on the gate electrode structure and subsequently anisotropically etched, for example by reactive ion etching, to expose the titanium nitride barrier layer. Anisotropic etching or subsequent isotropic etching removes the unprotected portions of the dielectric layer 52 of the sidewall spacer 30. By removing this portion of the dielectric layer, the gate electrode 24
A portion of the source and drain regions spaced apart from is exposed. The remaining portion of the dielectric layer 52, designated by the numeral 22, forms the gate insulation of the device.

When the side wall spacer is formed at a predetermined position,
A layer of cobalt or other silicide forming metal is deposited on the structure to form a layer of cobalt silicide 28 or other metal silicide, where the silicide forming metal is in contact with silicon. Therefore, the silicide is exposed to the exposed portions of the source and drain regions 18 and associated P
Formed on the source and drain regions of the channel transistor. This silicide is not formed on the titanium nitride, nor is it formed on the LTO spacer or other dielectric material such as the field insulator present in the structure. Unreacted cobalt is removed from the surface of titanium nitride and other unreacted areas by etching in the metal etchant, which also does not corrode the titanium nitride or silicide. For example, unreacted cobalt is removed from the structure by etching in an etching solution containing 75 weight percent phosphoric acid, 2 percent nitric acid, 10 percent acetic acid and the balance of these with water. The sidewall spacers 30 prevent the formation of bridges or electrical connections between the gate electrodes and their associated source or drain regions.

This part of the manufacturing process is completed by selectively adding a high concentration of N-type conductivity determining additive impurities to the N-channel device. Arsenic ions or phosphorus ions are implanted into the gate electrode 24 and the silicide region 28,
The P-channel transistor of this circuit is preferably protected by a patterned photoresist layer. The implantation of N-type ions is indicated by arrow 58. N-type ions are introduced into the silicon gate electrode by implanting the ions with sufficient energy to penetrate the titanium nitride top layer. N-type ions are simultaneously cobalt
Implanted in or through the silicide. By the subsequent thermal redistribution of the added impurities,
A high concentration of N-type doped impurities is diffused from the silicide to the upper P-type surface region 16 between the cobalt silicide and the exposed portions of the source and drain regions spaced from the gate electrode 24. To form a low resistance contact. In a similar doping step, impurities that determine P-type conductivity are introduced into the P-channel transistor of the integrated circuit, while the N-channel transistor is located on top, such as a layer of patterned photoresist. The provision of a mask protects against the introduction of this.

This device is characterized by the fact that an insulating upper protective layer,
It is completed in the conventional manner by providing another interconnect layer or the like. The completed device has a highly conductive gate electrode and a highly conductive interconnect material, each of which is composed of a layer of doped polycrystalline silicon and an upper layer of conductive barrier material. .. The source and drain regions of each device are silicided with a metal silicide, which provides a highly conductive device region with low contact resistance. The interconnect is not silicidized, thus avoiding the problem of diffusion of doped impurities being accelerated through the silicified polysilicon.

In the embodiment of the invention described above, the silicon gate electrode is doped by introducing the additive through the top layer of conductive barrier material. This requires that the barrier layer be thin enough that a sufficient amount of added impurities will pass through the barrier layer and that the underlying silicon layer will be sufficiently doped. However, if the top barrier layer is too thin, the resistance of that layer will increase, compromising the goals of reducing or minimizing the resistance of the gate electrodes and interconnecting the lines. According to another embodiment of the invention (not shown), this problem is caused by ion implantation by means of ions which determine the N-type or P-type conductivity before depositing the overlying layer of titanium nitride. This can be solved by selectively adding impurities to the layer of polycrystalline silicon 54. For example, by masking the P-channel transistor with photoresist during ion implantation of the N-channel transistor and masking the N-channel transistor with photoresist during ion implantation of the P-channel transistor, The polycrystalline silicon in the channel transistor region is separately doped. Following the selective doping of the polycrystalline silicon, titanium nitride or other barrier material is added over the polycrystalline silicon layer and the process proceeds as described above.

In yet another embodiment of the present invention, the resistance of the polycrystalline silicon conductor is lowered by introducing titanium silicide below the layer of titanium nitride. This titanium-silicide layer reduces the resistance of the gate electrode and titanium nitride prevents interaction between the titanium-silicide and the layer of cobalt or other silicide-forming metal. The titanium-silicide layer can be formed by depositing a titanium layer having a thickness of about 20 nanometers over the undoped polycrystalline silicon layer. This is followed by a rapid thermal anneal of nitrogen or the nitrogen-containing periphery to convert titanium to titanium silicide in which the titanium contacts polycrystalline silicon and the upper surface of the titanium to titanium nitride. Convert to. The steps shown in FIGS. 4 to 6 above are then carried out.

Those skilled in the art will recognize that variations and changes can be made without departing from the spirit of the invention. For example, a material other than titanium nitride can be used as the conductive barrier layer as the conductive barrier layer. This barrier layer is sufficiently conductive to withstand the desired conductivity and can withstand subsequent processing, is compatible with the silicide-forming metal and is used to remove unreacted silicide-forming metal. It must be selected from materials that are resistant to the etchant used. In addition, other materials such as tungsten, tungsten silicide, tantalum silicide, etc. can be formed on the titanium nitride layer to further reduce the resistance of the polysilicon layer interconnect. Other metals such as platinum or palladium can also be used to form silicides, whereby providing a silicide forming metal is compatible with the selected conductive barrier material.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a CMOS device according to the present invention.

2 is a schematic plan view of interconnected CMOS devices according to the present invention; FIG.

FIG. 3 shows cross-sectional views of process steps according to one embodiment of the present invention.

FIG. 4 illustrates cross-sectional views of process steps according to one embodiment of the present invention.

FIG. 5 illustrates cross-sectional views of process steps according to one embodiment of the present invention.

FIG. 6 shows cross-sectional views of process steps according to one embodiment of the present invention.

[Explanation of symbols]

 10 Part of CMOS integrated circuit 12 N-channel MOS transistor 14 P-channel MOS transistor 16 P-type surface region (well region) 18 N-type source and drain region 20, 36 Channel region 22, 38 Gate insulating part 24, 40 Gate electrode 26 , 42 Conductive barrier layer 28 Metallic silica 30, 46 Sidewall spacer 32 N-type surface region 34 P-type drain and source region 44 Metal silicide 48 Interconnect 52 Dielectric layer 54 Polycrystalline silicon layer 56 Barrier material

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication point 9054-4M H01L 27/08 321 F (72) Inventor Young Lim Ameri Power USA, Austin, Pa. Raid ridge 5626

Claims (3)

[Claims] 1. A first PMOS transistor having a first source / drain region in contact with a metallic silica article and a first silicon gate electrode comprising a layer of conductive barrier material; a second source and drain region in contact with the metallic silica article. And a second NMOS transistor having a second silicon gate electrode including a layer of conductive barrier material; and means for coupling the first and second silicon gate electrodes constituted by a layer of silicon and a conductive barrier material. A CMOS device characterized by being formed. 2. A first PMOS transistor having a first P-type polycrystalline silicon gate electrode having a layer of silicon nitride formed thereon and first source and drain regions formed opposite to the first gate electrode. A first PMOS transistor in which the first source and drain regions are aligned with the first gate electrode and in contact with a metal silicide; a second N on which a layer of silicon nitride is formed; -Type multi-layered silicon gate electrode and second NMO having second source and drain regions formed on the opposite side of the second N-type polycrystalline gate-silicon electrode
An S-transistor, wherein the second source and drain regions are spaced from the N-type polycrystalline silicon gate electrode and a lightly doped N-type region aligned with the second N-type polycrystalline silicon gate electrode. A second NMOS transistor having an open N-type region doped with a large amount of impurities, and the metal silicide is in contact with the N-type region doped with a large amount of impurity; and the first P-type polycrystalline silicon.・ Gate electrode and the second N-type multilayer silicon
A CMOS device comprising: a means composed of polycrystalline silicon provided with silicon nitride for coupling with a gate electrode; 3. Providing a silicon substrate having a first N-type surface region and a second P-type surface region on which a gate insulator is formed; depositing a silicon layer overlying the gate insulator. Forming a layer of a conductive barrier material overlying the silicon layer; patterning the layer of conductive barrier material and the silicon layer, a first gate overlying the first surface region; Forming an electrode, a second gate electrode overlying the second surface region, and means for interconnecting the first and second gate electrodes;
Forming an impurity-doped source and drain region and a gate electrode of a P-channel transistor by selectively adding an impurity that determines P-type conductivity to the first gate electrode and the first surface region. Forming an impurity-doped source and drain region and a gate electrode of an N-channel transistor by selectively adding an impurity that determines N-type conductivity to the portion of the second gate electrode and the second surface region; And a step of forming a cobalt silica material in the doped portions of the source and drain regions of the N-channel and P-channel transistors.