JPH07321327A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To keep resistivity of a resistor high when silicide technique is applied to an SOI structure and further establish a film thickness of the resistor independently of the film thickness of the SOI layer. CONSTITUTION:An element separation region 4 for insulating and separating a silicon layer (SOI) layer 3 and an SOI layer 3 is formed via a buried oxide film 2 on a silicon substrate 1 and MOSFETs are formed in the SOI layer 3. A polysilicon layer 5 being a resistor is formed on the element isolation region 4 and further a polysilicon layer 7 being a mask layer is formed so as to coat a specific region on this polysilicon layer 5. At least a surface layer of the polysilicon layer 5 uncovered with the mask layer is silicified to form a silicide layer, and a region in a lower part of the mask layer out of the polysilicon layer 5 is structured as a resistance layer that is not silicified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device having a resistor and a MOSFET formed thereon.

[0002]

2. Description of the Related Art There is a technique generally called salicide (Self-Aligned-Silicide) for the purpose of reducing the resistance value of a diffusion layer. This technique is a technique of forming a metal silicon compound (silicide) in a self-aligning manner only on the surface of the silicon region exposed before forming the interlayer insulating film to reduce the resistivity of the silicon layer. When the salicide technique is applied, in a so-called bulk type element in which an element is directly formed on a silicon substrate, if a well region in which the surface of a resistor is covered with a field oxide film is used as a resistor, it is not affected by silicide The desired resistance value can be obtained with.

However, in an SOI structure in which a silicon layer is formed on a semiconductor substrate via an insulating film, the surface of the silicon layer used as a resistor is usually exposed before the step of forming an interlayer insulating film. When the technique is applied, a silicide layer is formed on the surface of the resistor, so that there is a problem that the resistance value of the resistor that needs to maintain high resistance is also reduced.

To solve this problem, there is a "semiconductor integrated circuit" disclosed in Japanese Patent Laid-Open No. 241452/1992. Polysilicon used as a gate electrode of MOSFET is shown in FIGS. Is also formed on the upper surface of the resistor and a silicide layer is formed on the surface by using it as a mask to maintain the high resistance of the resistor.

[0005]

In the above, the film thickness of the SOI layer forming the resistor is the same as that of the SOI layer which will be the active layer of the MOSFET, and therefore is the same as that of the SOI layer. The thickness is set so that the channel region of the MOSFET is completely depleted, so 0.1 μm
It becomes the following.

When this resistor is used as a protective element (see FIG. 5 of the above publication) against a surge of a semiconductor integrated circuit, its film thickness is thin as described above, so that the current density that instantaneously passes through the resistor is high. Therefore, the resistor may be damaged. The present invention has been made in view of the above problems, and an object thereof is to solve the above problems by making it possible to set the film thickness of a resistor independently of the film thickness of a semiconductor layer that is an active layer of a MOSFET.

[0007]

In order to achieve the above object, in the invention described in claim 1, a first insulator layer and a MOSFET formed on the first insulator layer,
A second insulator layer formed on the first insulator layer in a region different from that of the MOSFET; a first semiconductor layer formed on the second insulator layer and serving as a resistor; A mask layer formed to cover a predetermined region on the first semiconductor layer, wherein at least a surface layer of the first semiconductor layer not covered with the mask layer is formed as a silicided silicide layer. The first semiconductor layer covered with the mask layer is configured as the semiconductor layer which is not silicidized by the mask layer.

According to a second aspect of the present invention, a first insulator layer and a MOSF formed on the first insulator layer.
ET, a first semiconductor layer serving as a resistor formed on the first insulator layer with a thickness greater than that of a semiconductor layer serving as the active layer of the MOSFET, and the first A mask layer formed so as to cover a predetermined region on the semiconductor layer, wherein at least a surface layer of the first semiconductor layer not covered by the mask layer is formed as a silicided silicide layer, The first semiconductor layer covered with a layer is configured as the non-silicided semiconductor layer by the mask layer.

According to a third aspect of the invention, in the first or second aspect of the invention, the mask layer is a second semiconductor layer, and the silicide layer is formed on a surface layer of the second semiconductor layer. It is characterized by being. According to a fourth aspect of the present invention, in the third aspect, a sidewall insulating film is formed on a side surface of the second semiconductor layer,
The silicide layer is formed on the first semiconductor layer except for the second semiconductor layer and the sidewall insulating film.

According to a fifth aspect of the invention, an insulator layer formed on the semiconductor substrate, a MOSFET formed on the insulator layer, and a MOSFET formed between the semiconductor substrate and the insulator layer. And a semiconductor layer serving as a resistor,
Surfaces of the source and drain regions of the OSFET are formed as a silicide layer in which the semiconductor layer is silicided.
It is characterized in that it is configured as the non-silicided semiconductor layer by the first insulator layer.

According to a sixth aspect of the present invention, the step of forming a first insulator layer on the semiconductor substrate, the first semiconductor layer on the first insulator layer, and the first semiconductor layer Forming a second insulator layer that isolates and isolates the first semiconductor layer, forming a MOSFET in the first semiconductor layer, and forming a second semiconductor layer that serves as a resistor on the second insulator layer. And a step of forming a mask layer so as to cover a predetermined region on the second semiconductor layer, and a step of silicidizing at least the second semiconductor layer using the mask layer as a mask. I am trying.

According to a seventh aspect of the present invention, a step of forming a first insulator layer on the semiconductor substrate, a step of forming a first semiconductor layer on the first insulator layer, and A step of forming a MOSFET in the first semiconductor layer, and a second semiconductor layer serving as a resistor on the first insulator layer with a thickness greater than that of a semiconductor layer serving as the active layer of the MOSFET. A step of forming a mask layer covering a predetermined region on the second semiconductor layer, and a step of silicidizing at least the second semiconductor layer using the mask layer as a mask. Is characterized by.

According to an eighth aspect of the present invention, a step of forming an insulator layer on the first semiconductor substrate having a convex portion, and a step of forming a semiconductor layer to be a resistor on the insulator layer. A step of flattening the insulating layer having the semiconductor layer formed thereon, a step of bonding and joining a second semiconductor substrate to the flattened surface, and a step of polishing from the back surface of the semiconductor substrate. A step of forming an element region that is insulated and separated by the convex portion and the insulator layer;
The method is characterized by including a step of forming T and a step of siliciding the surface of the source and drain regions of the MOSFET after that.

[0014]

In the invention described in claim 1,
A MOSFET and a second insulator layer are formed on the first insulator layer. A first semiconductor layer serving as a resistor is formed on the second insulator layer, and a mask layer is formed so as to cover a predetermined region on the first semiconductor layer. Then, at least the surface layer of the first semiconductor layer not covered by the mask layer is formed as a silicide layer, and the first semiconductor layer covered by the mask layer is silicided by the mask layer. Not configured as a semiconductor layer.

Therefore, since the first semiconductor layer is not silicified by the mask layer, its resistance value can be maintained, and the first semiconductor layer serving as a resistor is a MOS.
Since it is formed separately from the semiconductor layer that will be the active layer of the FET, its thickness can be set independently of the thickness of the semiconductor layer that will be the active layer of the MOSFET, and the resistance of the desired film thickness according to the application target can be set. The value can be set.

Also in the invention described in claim 2, as in the above, since the first semiconductor layer is not silicified by the mask layer, its resistance value can be maintained and the first semiconductor layer becomes a resistor. Since the semiconductor layer is formed with a thickness larger than that of the semiconductor layer serving as the active layer of the MOSFET, even if the resistor is used as a protection element against a surge or the like of the semiconductor integrated circuit, the resistor is momentarily used. The density of the current passing through the resistor can be reduced, and the resistor can fully function.

Further, as in the invention described in claim 3, the second semiconductor layer can be used as the mask layer, in which case a silicide layer is formed on the surface layer of the second semiconductor layer. It Further, when the sidewall insulating film is formed on the side surface of the second semiconductor layer as in the invention according to claim 4, the first semiconductor layer is removed except for the second semiconductor layer and the sidewall insulating film. A silicide layer is formed.

According to a fifth aspect of the invention, the MOSFET is formed on the insulator layer formed on the semiconductor substrate, and the semiconductor layer serving as a resistor is formed between the semiconductor substrate and the insulator layer. To be done. The surface of the source and drain regions of the MOSFET is formed as a silicided silicide layer, and the semiconductor layer serving as a resistor formed between the semiconductor substrate and the insulator layer is silicided by the first insulator layer. It becomes a semiconductor layer that is not transformed.

Therefore, also in the present invention, the resistance value of the resistor can be maintained without being affected by silicidation, and the film thickness of the semiconductor layer can be changed to MOSFET.
It can be set independently of the semiconductor layer that will be the active layer. In the invention according to claim 6, the semiconductor device according to claim 1 can be manufactured, and in the invention according to claim 7, the semiconductor device according to claim 2 can be manufactured, and according to claim 8, In the above invention, the invention described in claim 5 can be manufactured by using a substrate bonding technique.

[0020]

FIG. 1 shows the first embodiment of the present invention. On a silicon substrate 1, a silicon layer (SOI layer) 3 and an element isolation insulating film 4 for insulatingly separating the SOI layer 3 are formed with a buried oxide film 2 interposed therebetween. A poly Si (polysilicon) layer 5 is formed on the element isolation insulating film 4, and a polysilicon layer 7 and a sidewall insulating film 8 are formed on the poly Si (polysilicon) layer 5 with an oxide film 6 interposed therebetween. An interlayer insulating film 9 is formed on the upper surface thereof, and contact holes 10 are provided in the interlayer insulating film 9 to form wirings 11, respectively.

On the other hand, a source and a drain are formed on the SOI layer 3, and a gate electrode 14 is formed via a gate oxide film 13 to form a MOSFET. Here, the polysilicon layer 7 is removed in the region for connecting the polysilicon layer 5 and the wiring 11. Also,
The silicon layer 5 used as a resistor under the polysilicon layer 7 is doped with an impurity having an appropriate concentration to obtain a desired resistivity.

When the salicide technique is applied to this structure, the silicide layer 12 is formed on the surface of the polysilicon layer 7 and the surface of the polysilicon layer 5 where the polysilicon layer 7 is not formed. As a result, the polysilicon layer 5 forming the resistor under the polysilicon layer 7 is not affected by silicidation, and its resistivity can be maintained at a desired value. That is, the polysilicon layer 7 functions as a mask layer for preventing the region forming the resistor in the polysilicon layer 5 from being silicided.

Further, the SOI layer 3 is formed by the silicidation.
A silicide layer is also formed on the surfaces of the source and drain regions of the MOSFET formed in FIG. The manufacturing process of this structure will be described below with reference to FIGS. First, as shown in FIG. 2A, a silicon layer 3 for forming an SOI N-channel MOSFET and an element isolation insulating film 4 are formed on a silicon substrate 1 via a buried oxide film 2 by a known method. An oxide film 31 is formed on the surface of the silicon layer 3.

Next, as shown in FIG. 2B, the polysilicon layer 5 having a desired resistance value used as a resistor is provided only on the element isolation insulating film 4, for example, the entire surface has a desired resistance value. It is formed by patterning after forming a polysilicon layer. In this case, the polysilicon layer 5 is
The film thickness of the SOI layer 3 which becomes the active layer of the MOSFET (for example,
It is formed with a film thickness (for example, 0.3 to 0.5 μm) thicker than 0.1 μm. After that, if necessary, once the oxide film 31
Are removed and then oxidized again to form the gate oxide film 13
And the oxide film 6 is formed.

Next, as shown in FIG. 2C, the MOSFE
A gate electrode 14 and a polysilicon layer 7 are formed by forming and patterning a polysilicon layer which will be the gate electrode of T. Then, if necessary, the LDD structure N
^- after ion implantation of P for layer formation, sidewall insulating films 8
Are further formed, and As ions are implanted to form N-type source / drain regions of the MOSFET. At this time, the resistance value of the polysilicon layer 5 may be adjusted to a desired value by simultaneously implanting As into the polysilicon layer 5. Then, a salicide process is performed to form a silicide layer 12, and then an interlayer insulating film 9 and a wiring 11 are formed to obtain the structure shown in FIG.

In this structure, since the polysilicon layer 5 serving as a resistor is formed on the element isolation insulating film 4, not only the SOI structure but also the element isolation insulating film formed on a normal single crystal silicon substrate. Needless to say, it can be formed. Moreover, although the polysilicon layer 7 is used as the mask layer, an insulator layer may be used as the mask layer.

Further, the case where the polysilicon layer 5 used as the resistor is formed on the element isolation insulating film 4 is shown.
The polysilicon layer 5 may be formed directly on the buried oxide film 2 instead of on the element isolation insulating film 4. For example, the SOI layer is formed on the buried oxide film 2 only in the element formation region, the polysilicon layer 5 used as a resistor is formed in the other region on the buried oxide film 2, and the interlayer insulation is provided between them. It can be formed so as to be separated by a film. Therefore, the first semiconductor, which is a resistor, is formed on the "first insulator layer" with a thickness larger than that of the semiconductor layer that is the active layer of the MOSFET. The term “layer” includes both the case where the polysilicon layer 5 as the first semiconductor layer is formed directly on the buried oxide film 2 or on the buried oxide film 2 via the element isolation insulating film 4.

Next, a second embodiment of the present invention will be described. In this embodiment, as shown in FIG. 3, a semiconductor layer (polysilicon layer) 15 forming a resistor is formed below the buried oxide film 2 formed below the silicon layer 3 forming the SOI type MOSFET. It is arranged. Further, the polysilicon layer 16 and the insulating film 17 are interposed between the silicon substrate 1 and the polysilicon layer 15.

In this structure, since the buried oxide film 2 is arranged on the polysilicon layer 15, no silicide layer is formed on the polysilicon layer 15 even if silicidation is performed and a desired resistance value is maintained. be able to. The manufacturing process of this structure will be described below with reference to FIGS. First, as shown in FIG.
Silicon layer substrate 1 in the region excluding the region where the FET is formed
Is etched to a predetermined depth, for example, about 200 nm to form a convex portion 18 having a step on the silicon substrate 1, and the buried oxide film 2 is formed on the surface thereof by a method such as thermal oxidation or a CVD method.

Next, as shown in FIG. 4B, a polysilicon layer 15 used as a resistor is formed, and then an insulating film 17 is formed on the surface of the polysilicon layer 15 by oxidation or CVD. Note that the polysilicon layer 15 is an SOI that becomes the active layer of the MOSFET, as in the first embodiment.
Thicker than the layer thickness (eg 0.1 μm) (eg 0.3 μm)
~ 0.5 μm). After that, S is applied by a known wafer bonding technique and selective polishing technique.
Form an OI substrate. An example thereof will be described below.

First, as shown in FIG. 4C, the polysilicon 16 is again formed on the entire surface, and then the surface is flattened and polished, and the surface is bonded to another silicon substrate 1B. Here, the bonding with the silicon substrate 1B may be performed through an oxide film. Next, FIG. 4 (d)
As shown in, the silicon substrate 1 is selectively polished from its back surface,
Since the polishing is selectively stopped by the buried oxide film 2, only the convex portion 18 remains as the silicon layer 3. After that, the silicon layer 3 is formed by a normal MOSFET manufacturing process.
A gate oxide film, a gate electrode, and a sidewall insulating film are formed on
After performing the salicide process, the interlayer insulating film 9 and the wiring 11 are formed. At that time, as shown in FIG. 3, the buried oxide film 2 is opened in the contact hole 10 so that the wiring 11 can be connected also to the polysilicon layer 15. Through the above steps, the structure shown in FIG. 3 is obtained.

Although not shown in the drawings, if a hole is provided in a part of the buried oxide film 2 on the polysilicon layer 15 for connection with the wiring layer before performing the salicide process, A silicide layer is also formed on the surface of the polysilicon layer 15 in the opening. Further, if necessary, a high concentration region for forming an ohmic contact may be formed in a region of the polysilicon layer 15 that contacts the wiring 11.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention.

FIG. 2 is a process drawing showing a process for manufacturing the semiconductor device shown in FIG.

FIG. 3 is a sectional view showing a second embodiment of the present invention.

FIG. 4 is a process drawing showing a process of manufacturing the semiconductor device shown in FIG.

[Explanation of symbols]

 1 Silicon Substrate 2 Buried Oxide Film 3 SOI Layer 4 Element Isolation Insulation Film 5 Polysilicon Layer 6 Oxide Film 7 Polysilicon Layer 8 Sidewall Insulation Film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 27/12 B 21/336 H01L 27/04 P 9056-4M 29/78 311 Y

Claims (8)

[Claims] 1. A first insulator layer, a MOSFET formed on the first insulator layer, and a second insulator formed on a region different from the MOSFET on the first insulator layer. A body layer, a first semiconductor layer formed on the second insulator layer and serving as a resistor, and a mask layer formed to cover a predetermined region on the first semiconductor layer, At least a surface layer of the first semiconductor layer that is not covered with a mask layer is formed as a silicide layer that is silicided, and the first semiconductor layer that is covered with the mask layer is formed by the mask layer. A semiconductor device characterized by being configured as a non-silicided semiconductor layer. 2. A first insulator layer, a MOSFET formed on the first insulator layer, and a film thickness of a semiconductor layer which is an active layer of the MOSFET on the first insulator layer. A first semiconductor layer, which has a thicker film thickness and serves as a resistor, and a mask layer formed to cover a predetermined region on the first semiconductor layer, are covered with the mask layer. At least a surface layer of the first semiconductor layer not formed is formed as a silicide layer, and the first semiconductor layer covered with the mask layer is a semiconductor not silicided by the mask layer. A semiconductor device characterized by being configured as a layer. 3. The mask layer is a second semiconductor layer,
The semiconductor device according to claim 1 or 2, wherein the silicide layer is formed on a surface layer of the second semiconductor layer. 4. A sidewall insulating film is formed on a side surface of the second semiconductor layer, and the silicide layer is formed on the first semiconductor layer except the second semiconductor layer and the sidewall insulating film. The semiconductor device according to claim 3, wherein: 5. An insulator layer formed on a semiconductor substrate, a MOSFET formed on the insulator layer, and a semiconductor layer formed between the semiconductor substrate and the insulator layer and serving as a resistor. The source and drain regions of the MOSFET are formed as a silicided silicide layer, and the semiconductor layer is formed as the semiconductor layer that is not silicided by the insulator layer. Semiconductor device. 6. A step of forming a first insulator layer on a semiconductor substrate, and a second insulation for insulatingly separating the first semiconductor layer and the first semiconductor layer on the first insulator layer. A step of forming a body layer, a step of forming a MOSFET in the first semiconductor layer, a step of forming a second semiconductor layer serving as a resistor on the second insulator layer, and a step of forming the second semiconductor layer A method of manufacturing a semiconductor device, comprising: a step of forming a mask layer covering a predetermined region on a semiconductor layer; and a step of silicidizing at least the second semiconductor layer using the mask layer as a mask. 7. A step of forming a first insulator layer on a semiconductor substrate, a step of forming a first semiconductor layer on the first insulator layer, and a MOSFET on the first semiconductor layer. A second step of forming a resistor on the first insulator layer with a film thickness larger than that of a semiconductor layer to be an active layer of the MOSFET.
Forming a semiconductor layer, forming a mask layer covering a predetermined region on the second semiconductor layer, and silicifying at least the second semiconductor layer using the mask layer as a mask. A method of manufacturing a semiconductor device, comprising: 8. A step of forming an insulator layer on a first semiconductor substrate having a convex portion, a step of forming a semiconductor layer to be a resistor on the insulator layer, and the step of forming the semiconductor layer A step of flattening the insulator layer; a step of bonding and joining a second semiconductor substrate to the flattened surface; a step of polishing from the back surface of the semiconductor substrate to form the convex portion and the insulator layer; And a step of forming a MOSFET in the element area, a step of forming a MOSFET in the element area, and a step of siliciding the surface of the source and drain regions of the MOSFET after that. Device manufacturing method.