JP2006216969A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a performance comparable to that of an MOSFET. <P>SOLUTION: An amorphous silicon film is deposited on a substrate having an insulating surface, a metal element for accelerating crystallization by forming a mask insulating film is introduced selectively onto the amorphous silicon film, at least a part of the amorphous silicon film is rendered to crystalline silicon film by first heat treatment, the mask insulating film is removed and an insular crystalline silicon film is formed by patterning, metal element in the insular crystalline silicon film is removed through gettering by performing second heat treatment in an atmosphere containing a halogen element, a thermal oxidation film being employed as a gate insulating film is formed on the surface of the insular crystalline silicon film, a gate electrode is formed on the thermal oxidation film, a source region and a drain region are formed on the insular crystalline silicon film by implanting impurity ions for imparting one conductivity, a metal film is formed on the upper surface of the source region and drain region, and then the source region and drain region are silicificated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

The invention disclosed in this specification relates to a semiconductor device having a semiconductor thin film formed over a base having an insulating surface as an active layer. In particular, the present invention relates to a thin film transistor in which an active layer is formed of a crystalline silicon film.

In recent years, attention has been paid to a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several hundred to several thousand Å) formed on a substrate having an insulating surface. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.

For example, in a liquid crystal display device, a pixel matrix circuit that individually controls pixel areas arranged in a matrix, a drive circuit that controls the pixel matrix circuit, and a logic circuit (processor circuit or memory circuit) that processes an external data signal Attempts have been made to apply TFTs to all electrical circuits.

An important part that should be called the heart of such a TFT is a channel forming region and a junction part that joins the channel forming region and the source / drain region. That is, it can be said that the active layer most affects the performance of the TFT.

As a semiconductor thin film constituting the active layer of a TFT, a silicon (silicon) film formed by using a plasma CVD method or a low pressure thermal CVD method is generally used.

At present, TFTs using amorphous silicon films (amorphous silicon films) have been put into practical use, but electrical circuits that require higher speed operation performance such as drive circuits and logic circuits have crystallinity. A TFT using a silicon film (polysilicon film) is required.

As a method for forming a crystalline silicon film on a substrate, techniques described in Japanese Patent Application Laid-Open Nos. 6-232059 and 6-244103 by the present applicant are known. The technique described in this publication uses a metal element (especially nickel) that promotes the crystallization of silicon.
A crystalline silicon film having excellent crystallinity can be formed by heat treatment at 0 ° C. for about 4 hours.

Further, the technique described in Japanese Patent Laid-Open No. 7-321339 applies the above technique to perform crystal growth substantially parallel to the substrate, and the inventors set the formed crystallization region in particular as the lateral growth region (or Lateral growth area).

The crystalline silicon film formed by such a technique has a feature that it has excellent crystallinity because it has a crystal structure in which columnar or needle-like crystals are gathered in a state where their traveling directions are substantially aligned. For this reason, it has been found that when a crystalline silicon film formed by using the technique described in the above publication is used as an active layer of a TFT, it is possible to produce a TFT having high operating performance.

However, even if a drive circuit is configured using such TFTs, the required performance is still not fully satisfied. In particular, it is currently impossible to configure a high-speed logic circuit that requires extremely high-performance electrical characteristics that simultaneously achieve high-speed operation and high breakdown voltage characteristics with conventional TFTs.

As described above, in order to improve the performance of an electro-optical device or the like, a TFT having a performance comparable to a MOSFET formed using a single crystal silicon wafer must be realized.

Accordingly, an object of the invention disclosed in this specification is to provide an extremely high performance thin film semiconductor device and a method for manufacturing the same, which can be a breakthrough for realizing higher performance of an electro-optical device.

The reason why a high-performance TFT as described above could not be obtained by the conventional method is that the crystal grain boundaries of needle-like or columnar crystals (the crystal grain boundaries in this specification are needle-like or columnar unless otherwise noted) It is considered that carriers (electrons or holes) are trapped at the boundary between the crystals), and the improvement of field effect mobility, which is one of the parameters indicating the TFT characteristics, is hindered.

For example, many unpaired bonds (dangling bonds) and defects (trapping) levels of silicon atoms exist at the grain boundaries. Further, it has been found that if a metal element that promotes crystallization is used during crystallization, the metal element segregates at the crystal grain boundary.

Therefore, carriers moving inside individual needle-like or columnar crystals are easily trapped in unpaired bonds, defect levels, etc. when they approach or come into contact with the crystal grain boundaries. It is thought that it was acting as a “malignant grain boundary” to inhibit.

In order to realize the semiconductor device of the present invention, a technique for changing the structure of such a “malignant grain boundary” and transforming it into a “benign crystal grain boundary” for the carrier is indispensable. That is, it can be said that it is important to form a crystal grain boundary that has a low probability of capturing carriers and has a low possibility of hindering the movement of carriers.

Therefore, the configuration of the invention disclosed in this specification is as follows.
In manufacturing a semiconductor device having an active layer made of a semiconductor thin film,
Forming an amorphous silicon film on a substrate having an insulating surface;
Selectively forming a mask insulating film on the amorphous silicon film;
Selectively holding a metal element that promotes crystallization of the amorphous silicon film;
Transforming at least a part of the amorphous silicon film into a crystalline silicon film by a first heat treatment;
Removing the mask insulating film;
Forming an island-like semiconductor layer composed only of the crystalline silicon film by patterning as a later active layer;
Performing a second heat treatment in an atmosphere containing a halogen element to remove the metal element in the island-shaped semiconductor layer and forming a gate insulating film made of a thermal oxide film;
Having at least
The active layer is formed by collecting a plurality of needle-like or columnar crystals substantially parallel to the substrate.

In addition, the configuration of other inventions is as follows:
In manufacturing a semiconductor device having an active layer made of a semiconductor thin film,
Forming an amorphous silicon film on a substrate having an insulating surface;
Selectively forming a mask insulating film on the amorphous silicon film;
Selectively holding a metal element that promotes crystallization of the amorphous silicon film;
Transforming at least a part of the amorphous silicon film into a crystalline silicon film by a first heat treatment;
Removing the mask insulating film;
Forming an island-like semiconductor layer composed only of the crystalline silicon film by patterning as a later active layer;
A step of performing gettering removal of the metal element in the island-shaped semiconductor layer by performing a second heat treatment in an atmosphere containing a halogen element;
Removing the thermal oxide film formed by the second heat treatment;
Forming a thermal oxide film functioning as a gate insulating film on the surface of the island-like semiconductor layer by performing a third heat treatment;
Having at least
The active layer is formed by collecting a plurality of needle-like or columnar crystals substantially parallel to the substrate.

When a crystalline silicon film is formed by a manufacturing method according to the above configuration, a thin film having an appearance as shown in FIG. 9 is obtained. FIG. 9 is an enlarged photomicrograph when the present invention is carried out using the technique described in Japanese Patent Laid-Open No. 7-321339 as a means for crystallizing an amorphous silicon film, and a laterally grown region having a length of several hundred μm. 901 is formed.

The laterally grown region 901 grows substantially perpendicularly to the region (indicated by 902) in which needle-like or columnar crystals are added with a metal element that promotes crystallization and substantially parallel to each other. The crystal orientation is aligned. In addition, what is indicated by reference numeral 903 is a macroscopic grain boundary formed by collision of needle-like or columnar crystals extending from the opposite addition region 902 (distinguishable from a grain boundary between needle-like or columnar crystals). ).

Further, focusing on the inside of the lateral growth region shown in FIG. 9, a TEM photograph in which the inside of the crystal grain is enlarged to 250,000 times is FIG. 10 (A). FIG. 1A schematically shows the structure of FIG.
4 (B).

That is, the crystalline silicon film of the present invention macroscopically appears to be composed of a large lateral growth region 901 as shown in FIG. 9, but when the lateral growth region 901 is observed microscopically, FIG. As shown in FIG. 5A, the crystal structure is formed by a plurality of acicular or columnar crystals 1001.

In FIG. 10B, reference numeral 1002 denotes a crystal grain boundary indicating a boundary between needle-like or columnar crystals, and the needle-like or columnar crystal 1001 from the direction in which the crystal grain boundary 1002 extends.
It can be confirmed that the crystals grew in directions substantially parallel to each other.

In the semiconductor device of the present invention, a metal element that promotes crystallization by heat treatment in an atmosphere containing a halogen element (in this specification, nickel is a main example) is gettered and removed.
SIMS analysis shows that nickel remaining at a concentration of 1 × 10 ¹⁸ atoms / cm ³ or more is reduced to 1 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁷ atoms / cm ³ or less). Secondary ion mass spectrometry).

Of course, it is considered that other metal elements (Cu, Al, etc.) mixed due to contamination or the like are also gettered and removed.

At this time, the silicon atom bonded to nickel is broken and forms many dangling bonds. However, it is bonded to oxygen during the heat treatment in the halogen atmosphere to form an oxide (silicon oxide). ). As a result, it is considered that silicon oxide is formed in a region that was a “malignant grain boundary”, and the silicon oxide substantially functions as a crystal grain boundary.

It is presumed that the crystal grain boundary 1002 formed in this way is in an excellent state in which the interface between silicon oxide and crystalline silicon contains almost no lattice defects. This is due to the synergistic effect of the process in which silicon oxide is formed by thermal oxidation and the process in which recombination between silicon atoms or silicon atoms and oxygen atoms is promoted by the catalytic action of nickel. This is because silicon atoms are consumed.

That is, the crystal grain boundary denoted by reference numeral 1002 in FIG. 10 has almost no defects that capture carriers and functions only as an energy barrier for carriers moving inside the needle-like or columnar crystals. It is thought to behave as a “grain boundary”.

Further, since the thermal oxidation reaction preferentially proceeds in such a crystal grain boundary, the thermal oxide film is formed thicker than other regions. For this reason, when the thermal oxide film is used as the gate insulating film, it is estimated that the gate voltage applied in the vicinity of the crystal grain boundary can be an apparent energy barrier.

However, in consideration of the TFT characteristics described later, the energy barrier of the crystal grain boundary 1002 is not so high as to completely prevent carrier movement, and it is assumed that carriers moving beyond the crystal grain boundary exist with a considerable probability. .

In addition, when this heat treatment is performed at a relatively high temperature exceeding 700 ° C. (typically 800 to 1100 ° C.), crystal defects such as dislocations and stacking faults existing inside the needle-like or columnar crystals are almost disappeared. Resulting in. Furthermore, the remaining dangling bonds of silicon atoms are terminated by hydrogen or halogen elements contained in the film.

Therefore, the present inventors define a region inside a plurality of needle-like or columnar crystals as “a region that can be regarded as a substantially single crystal for carriers” in the state shown in FIG. 10A obtained as described above. is doing.

The phrase “substantially regarded as a single crystal for carriers” means that there are no barriers that prevent the carriers from moving when carriers move, and there are no crystal defects or grain boundaries, and potential for energy barriers. In other words, there is no barrier.

The present invention forms an active layer of a semiconductor device typified by a TFT using the crystalline silicon film having the above-described configuration, and realizes a high-performance semiconductor device sufficient to form a drive circuit and a logic circuit. Is.

The configuration of the present invention as described above will be described in detail in the embodiments described below.

According to the invention disclosed in this specification, a TFT having high performance comparable to a MOSFET manufactured over single crystal silicon can be realized. Further, the ring oscillator constituted by the TFT of the present invention can operate 20 times faster than the ring oscillator constituted by the conventional TFT.

Moreover, despite having such high characteristics, it has been confirmed that even in the fine region where the channel length is 1 μm or less, it has extremely high breakdown voltage characteristics, and the short channel effect is effectively suppressed. it can.

By applying the integrated circuit configured using the TFT as described above to the electro-optical device, it is possible to further improve the performance of the electro-optical device. In addition, applied products that apply electro-optical devices can also have high performance and high added value.

In this embodiment, a crystalline silicon film formed according to the manufacturing method of the present invention is formed using a thin film transistor (
An example used as an active layer of TFT) will be described. FIG. 1 shows an embodiment of a TFT manufacturing process.

Incidentally, the means for crystallizing the amorphous silicon film used in this embodiment is a technique described in Japanese Patent Laid-Open No. 7-321339. Therefore, in this embodiment, only the outline is described, so the details should be referred to the above publication.

First, a base 101 having an insulating surface is prepared. In this embodiment, a silicon oxide film 102 is formed to a thickness of 2000 mm as a base film on a quartz substrate. As a method for forming the silicon oxide film 102, a low pressure thermal CVD method, a plasma CVD method, a sputtering method, or the like may be used. Further, when the upper limit temperature of the TFT manufacturing process is 700 ° C. or lower, a glass substrate can be used as the substrate 101.

In addition, when crystallizing an amorphous silicon film later, it has been found by the present inventors that the crystallinity of a crystalline silicon film obtained by a denser base film is better. In the film, 5 × 10 ¹⁷ 〜 2
It is preferable that oxygen of × 10 ¹⁹ atoms / cm ³ is contained. Oxygen contained in the film plays an important role in the subsequent gettering treatment of the metal element that promotes the crystal.

Next, an amorphous silicon film 103 is formed to a thickness of 750 mm by low pressure thermal CVD. As a film forming gas, disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), or the like may be used. Note that the amorphous silicon film formed by the low pressure thermal CVD method has a small natural nucleus generation rate in the subsequent crystallization. This reduces the rate at which the individual crystals interfere with each other (collision stops and growth stops)
This is desirable for increasing the lateral growth width.

Of course, as a method for forming the amorphous silicon film 103, a plasma CVD method, a sputtering method, or the like can be used.

Next, a silicon oxide film 104 having a thickness of 500 to 1200 mm is formed by a plasma CVD method or a sputtering method, and only a region where a metal element for promoting crystallization is introduced is selectively removed by etching. That is, the silicon oxide film 104 functions as a mask insulating film for selectively introducing nickel into the amorphous silicon film 103.

The region 105 exposed by the silicon oxide film 104 is formed in a slit shape having a longitudinal direction in a direction perpendicular to the paper surface. (Fig. 1 (A))

Next, UV light is irradiated in an oxygen atmosphere to form an extremely thin oxide film (not shown) on the surface of the amorphous silicon film 103 exposed by the region 105. This oxide film is for improving the wettability of the solution in the solution coating step when a metal element that promotes crystallization is introduced later.

Note that the metal elements that promote crystallization include Fe, Co, Ni, Ru, Rh, Pd, and O.
One or more kinds of elements selected from s, Ir, Pt, Cu, and Au are used. In the present embodiment, description will be made taking Ni (nickel) as an example.

Next, a nickel nitrate solution (or nickel acetate solution) containing nickel at a predetermined concentration (10 ppm in terms of weight in this embodiment) is dropped, and a thin water film 106 containing nickel is formed by spin coating. . The concentration of nickel added to the amorphous silicon film can be easily controlled by adjusting the concentration of the nickel salt solution in the solution coating process. (Fig. 1 (B
))

Next, after dehydrogenating at 450 ° C. for about 1 hour in an inert atmosphere, 500 to 700
The amorphous silicon film 103 is crystallized by applying a heat treatment (first heat treatment) for 4 to 8 hours at a temperature of ° C., typically 550 to 600 ° C. Thus, the crystalline silicon film 107 is obtained. (Fig. 1 (
C))

At this time, crystal growth proceeds in a direction in which needle-like or columnar crystals are substantially parallel to the substrate. In the case of the present example, the region indicated by 105 has a slit shape having a longitudinal direction from the front side to the back side of the drawing, so that the crystal growth proceeds substantially in one direction as indicated by an arrow 108. To do. At this time, crystal growth can be performed over several hundred μm or more.

Reference numeral 109 denotes a nickel-added region, which contains nickel at a higher concentration than the lateral growth region 107. The added region 109 is not very good in crystallinity because crystal nuclei are densely grown to grow crystals. Therefore, the active layer to be formed later is constituted by a region excluding the addition region 109.

During crystallization, nickel contained in the water film 106 diffuses into the amorphous silicon film 103 through an oxide film (not shown) and functions as a catalyst for promoting crystallization. Specifically, nickel and silicon react to form silicide, which becomes crystal nuclei and crystallization proceeds.

At this time, crystal growth proceeds from a region where crystal nuclei are generated, with needle-like or columnar crystals extending in a direction substantially parallel to the substrate. At this time, if the temperature of the heat treatment exceeds 600 ° C., spontaneous nucleation occurs regardless of the catalytic action of nickel. Then, the crystal growth of needle-like or columnar crystals having nickel silicide as a crystal nucleus is hindered, and the growth width of the crystal growth is shortened, which is not preferable.
Therefore, it is desirable that the conditions be such that the generation of crystal nuclei occurs only with the introduced nickel, with less generation of natural nuclei.

Next, when the heat treatment for crystallization is completed, the silicon oxide film 104 which is a mask insulating film for selectively adding nickel is removed. This step is easily performed with buffered hydrofluoric acid or the like.

Note that laser annealing using an excimer laser may be performed on the crystalline silicon film 105 before and / or after the subsequent heat treatment in an atmosphere containing a halogen element. However, the crystallinity of the crystalline silicon film can be improved by laser irradiation, but care must be taken because irregularities are easily formed on the surface of the silicon film.

Next, the obtained crystalline silicon film 107 is patterned to form an island-shaped semiconductor layer 110. The island-shaped semiconductor layer 110 functions later as an active layer of the TFT. In the present invention, the arrangement of the island-like semiconductor layers is important. This will be described later.

In this embodiment, after the island-shaped semiconductor layer 116 is formed, heat treatment is performed in an atmosphere containing the next halogen element. Conversely, before the island-shaped semiconductor layer is formed, the heat treatment is performed in an atmosphere containing the halogen element. Heat treatment may be performed.

However, since the surface area is increased after the crystalline silicon film 107 is processed into an island shape, it is preferable for efficient gettering of nickel.

In addition, the island-shaped semiconductor layer 110 is formed by a dry etching method. At this time, plasma damage remaining on the edge of the island-shaped semiconductor layer may cause a leakage current of the TFT. In the case of this embodiment, the edge of the island-like semiconductor layer 110 is thermally oxidized, so that it also serves to remove plasma damage.

Next, heat treatment (second heat treatment) is performed on the island-shaped semiconductor layer 110 obtained through the above steps in an atmosphere containing a halogen element. The temperature range of the heat treatment is a temperature exceeding 700 ° C., preferably 800 to 1000 ° C. (typically 950 ° C.), and the treatment time is 1 to 24 hours, typically 6 to 12 hours.

In this embodiment, heat treatment is performed at 950 ° C. for 30 minutes in an atmosphere containing hydrogen chloride (HCl) at a concentration of 0.5 to 10% by volume with respect to an oxygen (O ₂ ) atmosphere. Note that it is not preferable that the HCl concentration be equal to or higher than the above concentration because unevenness of the same degree as the film thickness occurs on the surface of the crystalline silicon film.

As a result of this heat treatment, a silicon film of about 250 mm is oxidized on the surface of the island-shaped semiconductor layer 110 to form a thermal oxide film 111 of 500 mm, and the film thickness of the island-shaped semiconductor layer 110 is about 500 mm.

It is important that the heat treatment for gettering is performed at a temperature of 700 ° C. or higher in order to obtain the effect. This is because if the temperature is lower than that, the thermal oxide film formed on the film surface becomes a blocking layer and a sufficient gettering effect cannot be obtained.

In addition, various conditions can be set for the gettering process by appropriately setting the processing temperature, the processing atmosphere, and the processing time. For example, when it is desired to lengthen the processing time and set a longer effective gettering time, this can be achieved by lowering the processing temperature or reducing the content of the halogen element.

In this embodiment, nickel contained in the island-shaped semiconductor layer 110 (strictly segregated at the grain boundaries of needle-like or columnar crystals) is gettered and removed by a halogen element, and thermal oxidation is performed. It serves both as the purpose of forming a film and using it as a gate insulating film.

Of course, it is possible to separately perform the heat treatment for gettering and the heat treatment (third heat treatment) for forming the thermal oxide film (gate insulating film) by dividing both purposes separately.

Further, a gate insulating film made of a silicon oxide film is formed on the island-like semiconductor layer by any one of a plasma CVD method, a low pressure thermal CVD method, and a sputtering method, and then heat treatment in an atmosphere containing the halogen element. May be performed.

In this embodiment, an example in which HCl gas is used as a compound containing a halogen element is shown.
As other gases, HF, NF ₃ , HBr, Cl ₂ , ClF ₃ , BCl ₃ , F ₂ , B
One or a plurality of compounds selected from compounds containing halogen such as r ₂ can be used. In general, a hydride of halogen or an organic substance (carbon hydride) can also be used.

In this step, it is considered that nickel segregated at the crystal grain boundaries of the needle-like or columnar crystals is gettered by the action of the halogen element and becomes volatile nickel chloride which is released into the atmosphere and removed.

The above gettering process reduces the island shape to a level that does not contain nickel or affects device characteristics (1 × 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³ or less) It is confirmed by SIMS analysis that the semiconductor layer 110 is obtained. Moreover, the impurity concentration in this specification is defined by the minimum value of the measured values obtained by SIMS analysis.
(Figure 1 (D))

According to the knowledge of the present inventors, nickel used for promoting crystallization tends to segregate a lot at the crystal grain boundaries of the needle-like or columnar crystals, and the inside of the needle-like or columnar crystals is substantially hardly present. Not considered to be included.

However, since the current SIMS analysis picks up information on both the inside of the crystal and the grain boundary, strictly speaking, the nickel concentration in this specification is an average of the nickel concentration contained in the inside of the crystal and the grain boundary. Mean average concentration.

When the gettering process is performed, the halogen element used for the gettering process remains in the crystalline silicon film at a concentration of 1 × 10 ¹⁵ to 1 × 10 ²⁰ atoms / cm ³ . At that time, it tends to be distributed at a high concentration between the crystalline silicon film and the thermal oxide film.

The nickel removed in the gettering step is segregated by being pushed out to the crystal grain boundaries of the needle-like or columnar crystals during crystallization. That is, it is thought that it existed as nickel silicide in the crystal grain boundary.

Nickel that has existed as nickel silicide is separated as nickel chloride, and a large number of dangling bonds of silicon that is disconnected from nickel are present in the crystal grain boundaries.

But the process in an oxidizing atmosphere, is believed to form a relatively dangling bonds formed to be done at high temperatures oxides coupled with readily oxygen (silicon oxide represented by SiO _X) . That is, the present inventors believe that the crystalline silicon film becomes a crystal structure in which silicon oxide functions as a crystal grain boundary by the series of heating steps.

The remaining dangling bonds are terminated by hydrogen or halogen elements contained in the island-like semiconductor layer 110 or compensated by recombination of silicon, and crystal defects such as dislocations and stacking faults are caused by silicon atoms. It is considered that the crystallinity inside the needle-like or columnar crystal is remarkably improved because it is almost disappeared by recombination and rearrangement.

Therefore, the island-shaped semiconductor layer 110 is sufficiently removed by heat treatment in a halogen atmosphere to the extent that nickel does not hinder device characteristics, and the needle-like or columnar crystals constituting the island-like semiconductor layer 110 have extremely high crystallinity. It is improved and is composed of a crystal structure having a region which can be regarded as a single crystal for carriers.

After completing the formation of the gate insulating film (thermal oxide film) 111 as described above, an aluminum film (not shown) for forming a gate electrode is then formed by sputtering to a thickness of 2500 mm. . This aluminum film contains 0.2% by weight of scandium to prevent hillocks and whiskers.

In this embodiment, a material mainly composed of aluminum is used as a material for forming the gate electrode (including the gate line), but tungsten, tantalum, molybdenum, or the like can also be used. Alternatively, a crystalline silicon film imparted with conductivity may be used as a gate electrode.

When the aluminum film is formed, an extremely thin anodic oxide film (not shown) is formed on the surface. This anodic oxide film is obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia as an electrolytic solution. That is, in this electrolytic solution, the aluminum film is an anode,
Anodization is performed using platinum as a cathode.

The anodized film formed in this step has a dense film quality and functions to improve adhesion with a resist mask to be formed later. The film thickness of this anodic oxide film is about 100 mm. The film thickness can be controlled by the applied voltage.

Next, as shown in FIG. 1D, the aluminum film is patterned to form an island-shaped aluminum film pattern 112 which becomes a prototype of the gate electrode. The resist mask (not shown) used at this time is left as it is. (Fig. 2 (A))

Then, anodization is performed again using the aluminum film pattern 112 as an anode. Here, a 3% oxalic acid aqueous solution is used as the electrolytic solution. In this anodic oxidation process, since there is a resist mask (not shown), the anodic oxidation proceeds only on the side surface of the aluminum pattern 112. Accordingly, an anodic oxide film is formed as indicated by 113 in FIG.

Further, the anodic oxide film 113 formed in this step has a porous shape, and the growth distance can be increased to several μm. The thickness of the porous anodic oxide film 113 is 0.7 μm.
And The thickness of the anodic oxide film 113 can be controlled by the anodic oxidation time.

When the porous anodic oxide film 113 shown in FIG. 2B is formed, the resist mask (not shown) is removed. A dense anodic oxide film 114 is formed by performing anodic oxidation again. This anodic oxidation step is performed under the same conditions as those for forming the above-described dense anodic oxide film.

However, the film thickness to be formed is 900 mm. In this step, the porous anodic oxide film 1
In order for the electrolytic solution to enter 13, an anodic oxide film 114 is formed as shown in FIG. Further, when the thickness of the anodic oxide film 114 is increased to 1500 mm or more, an offset gate region can be formed in a subsequent impurity ion implantation step.

Further, the gate electrode 115 is defined through the above steps. The dense anodic oxide film 114 functions to protect the surface of the gate electrode 115 and to suppress generation of hillocks and whiskers in a later process.

Next, when the dense anodic oxide film 114 is formed, impurity ions are implanted to form source / drain regions in this state. If an N-channel TFT is manufactured, P (phosphorus) ions are implanted. If a P-channel TFT is manufactured, B (boron) ions are implanted.

In this step, the source region 116 and the drain region 11 doped with impurities at a high concentration are used.
7 is formed.

Next, using a mixed acid in which acetic acid, phosphoric acid and nitric acid are mixed, the porous anodic oxide film 113 is selectively removed, and then ion implantation of P ions is performed again. This ion implantation is performed with a lower dose than in the previous formation of the source / drain regions. (Fig. 2 (C))

Then, low-concentration impurity regions 118 and 119 having a lower impurity concentration than the source region 116 and the drain region 117 are formed. A region indicated by 120 immediately below the gate electrode 115 becomes a channel formation region in a self-aligning manner.

Note that the low concentration impurity region 119 disposed between the channel formation region 120 and the drain region 117 is particularly called an LDD (lightly doped drain region) region, and is formed between the channel formation region 120 and the drain region 117. It has the effect of relaxing the high electric field.

Further, the channel formation region 120 (strictly speaking, inside the needle-like or columnar crystal) is constituted by an intrinsic or substantially intrinsic region. An intrinsic or substantially intrinsic region is a region where the activation energy is approximately 1/2 (the Fermi level is located at the center of the forbidden band) and the impurity concentration is lower than the spin density. Or an undoped region where impurities such as P and B are not intentionally added.

Further, after the impurity ion implantation step, laser light, infrared light, or ultraviolet light irradiation is performed to anneal the ion-implanted region. By this treatment, activation of the added ions and recovery of damage caused to the active layer at the time of ion implantation are performed.

Further, here, it is effective to perform the plasma hydrogenation treatment in the temperature range of 300 to 350 ° C. for 0.5 to 1 hour. In this step, dangling bonds generated by hydrogen desorption from the active layer are again hydrogen-terminated. When this step is performed, hydrogen is added to the active layer at a concentration of 1 × 10 ²¹ atoms / cm ³ or less, preferably 1 × 10 ¹⁵ to 1 × 10 ²¹ atoms / cm ³ .

When the state shown in FIG. 2C is thus obtained, an interlayer insulating film 121 is formed next. The interlayer insulating film 121 includes a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film of these films. (Fig. 2 (D))

The use of a silicon nitride film is preferable because hydrogen added in the previous step can be prevented from being released again outside the device.

In addition, when polyimide which is an organic resin film is used, since the relative dielectric constant is small, the parasitic capacitance between the upper and lower wirings can be reduced. In addition, since the film can be formed by a spin coating method, the film thickness can be easily increased and the throughput can be improved.

Next, an interlayer insulating film 121 contact hole is formed, and a source electrode 122 and a drain electrode 123 are formed. Further, by performing heat treatment in a hydrogen atmosphere at 350 ° C., the entire element is hydrogenated, and the TFT shown in FIG. 2D is completed.

Although the TFT shown in FIG. 2D has the simplest structure for explanation, it is easy to make a desired TFT structure as appropriate by adding some changes and additions to the manufacturing process procedure of this embodiment. is there. Accordingly, the pixel TFT constituting the pixel matrix circuit of the active matrix display device
Alternatively, a circuit TFT (an inverter circuit, a shift register circuit, a processor circuit, a memory circuit, or the like) that forms a logic circuit can be manufactured.

Here, the reason why the arrangement of the island-like semiconductor layer 110 is important as described above will be described. The description will be given with reference to FIG.

When this example is carried out, needle-like or columnar crystals grow in substantially parallel to each other, so that the crystal grain boundaries are aligned in one direction. In addition, by selectively adding a metal element that promotes crystallization, it is possible to freely control the direction in which needle-like or columnar crystals grow. This has a very important meaning.

FIG. 3 shows an embodiment in which an island-like semiconductor layer is formed on a substrate having an insulating surface. FIG.
Shown are island-shaped semiconductor layers arranged in a matrix on the substrate 301 in manufacturing an active matrix liquid crystal display device.

In addition, the area | region shown with the broken line 302 is a place where the area | region for selectively introduce | transducing nickel existed. Reference numeral 303 denotes a place where a macroscopic grain boundary formed by the laterally grown regions colliding with each other exists. Since these cannot be confirmed after the island-shaped semiconductor layer is formed, they are indicated by dotted lines.

Further, when crystallization is performed by the means shown in this embodiment, needle-like or columnar crystals grow in a direction substantially perpendicular to the nickel-added region 302 (direction indicated by an arrow in the figure).

Therefore, by disposing the island-shaped semiconductor 304 as shown in FIG. 3, the channel direction and the crystal grain boundary of the needle-like or columnar crystal can be aligned in the same direction. Moreover, the nickel addition region 30
By designing 2 so as to reach the end of the substrate 301, the above-described configuration can be realized on the entire surface of the substrate.

With such a configuration, the channel direction and the direction in which the needle-like or columnar crystals are arranged coincide with each other. In other words, the channel direction and the moving direction of the carriers moving inside the needle-like or columnar crystal are exactly the same.

That is, when functioning as an active layer of a TFT, this means that there are very few energy barriers that hinder the movement of carriers in the channel formation region, and further improvement in the operation speed can be expected.

Therefore, the TFT shown in this embodiment can realize a very high-speed operation by adopting a configuration in which the direction in which the needle-like or columnar crystal extends and the channel direction coincide with each other.

Here, FIG. 4 shows the electrical characteristics of the semiconductor device shown in FIG. 2D manufactured by the present inventors in accordance with this embodiment. 4A shows the electrical characteristics (Id-Vg characteristics) of the N-channel TFT, FIG.
(B) shows the electrical characteristics of the P-channel TFT. Note that the graph showing the Id-Vg characteristics displays the measurement results for 10 points together.

VG on the horizontal axis is the gate voltage value, and ID on the vertical axis is the current value flowing between the source and drain.
Also, Id-Vg characteristics (Id-Vg curves) indicated by 401 and 403 indicate characteristics when the drain voltage VD = 1V, and Id-Vg characteristics indicated by 402 and 404 indicate characteristics when the drain voltage VD = 5V. The characteristics are shown. Reference numerals 405 and 406 denote leakage currents when the drain voltage VD = 1V.

Note that the drain current (Ioff) in the off region (-1V or less in FIG. 4A and -1V or more in FIG. 4B) and the leakage current (IG) in the on and / or off regions are almost 1 ×. Since it is below 10 ^-13 A (lower limit of measurement), it is confused with noise in Figs. 4 (A) and 4 (B).

Here, Table 1 and Table 2 show typical characteristic parameters of the TFT according to the present invention obtained from the electric characteristics shown in FIGS. 4 (A) and 4 (B). Table 1 shows the results of electrical characteristics (arbitrary 20 points measurement) of the N-channel TFT, and Table 2 shows the results of electrical characteristics (arbitrary 20 points measurement) of the P-channel TFT.

Of particular note in Tables 1 and 2 are the sub-threshold characteristics (S value, S-value).
Is small enough to fit between 60-100 mV / dec and mobility (μFE, mobility) is 150-300 cm ² / V
It is extremely large like s. In the present specification, mobility means field effect mobility.

These measured data are values that cannot be achieved with a conventional TFT, and are exactly the values of T according to the present invention.
The FT proves to be a very high performance TFT comparable to a MOSFET fabricated on a single crystal.

At the same time, the TFT according to the present invention is confirmed to be very resistant to deterioration by an accelerated deterioration test by repeated measurement. Empirically, TFTs that operate at high speed have the disadvantage of being easily deteriorated, but it has been found that the TFTs according to the present invention have no deterioration and have extremely high breakdown voltage characteristics.

Tables 1 and 2 also list average values and standard deviations (σ values) for reference. The standard deviation is used as a measure of dispersion (variation) from the average value. In general, if the measurement results (population) follow a normal distribution (Gaussian distribution), the entire value is within ± 1σ around the average value.
It is known that 95.4% falls within .3%, ± 2σ, and 99.7% falls within ± 3σ.

For example, if 100 N-channel TFTs manufactured according to the present invention are measured, the S value of about 95 TFTs is in the range of 60 to 100 mV / dec (70 to 100 mV / dec for P-channel TFTs). Means it fits in.

In order to more accurately evaluate the dispersion of the TFT characteristics of this example, the present inventors have made 540 TFs.
T was measured, and the average value and aiming deviation were determined from the results. As a result, the average value of S values is 80
0.5 mV / dec (n-ch) and 80.6 mV / dec (p-ch), with standard deviations of 5.8 (n-ch) and 11.5 (p-ch). The average mobility (max) is 194.0cm ² / Vs (n-ch), 131.8cm ² / Vs (p-ch), and the standard deviation is 38.5 (n-ch), 10.2 (p-ch) )Met.

That is, in the N-channel TFT using the present invention, the following TFT characteristics can be obtained.
(1) The S value σ value is within 10 mV / dec, preferably within 5 mV / dec.
(2) The S value is within 80 ± 30 mV / dec, preferably within 80 ± 15 mV / dec.
(3) The σ value of μFE is within 40 cm ² / Vs, preferably within 35 cm ² / Vs.

Further, in the P-channel TFT using the present invention, the following TFT characteristics can be obtained.
(1) The σ value of the S value is within 15 mV / dec, preferably within 10 mV / dec.
(2) S value is within 80 ± 45 mV / dec, preferably within 80 ± 30 mV / dec.
(3) The σ value of μFE is within 15 cm ² / Vs, preferably within 10 cm ² / Vs.

As described above, the TFT according to the present invention realizes extremely excellent electrical characteristics, such as a complicated SRAM circuit or D which has been used only in a MOSFET manufactured up to now on a single crystal.
A logic circuit that requires high-speed operation, such as a RAM circuit, can be configured.

In this example, only a manufacturing process example of a TFT having a single gate structure is described.
The present invention can also be applied to a TFT having a double gate structure and a TFT having a multigate structure having a gate electrode higher than that.

It is also possible to produce an inverted staggered TFT using a crystalline silicon film as the gate electrode. That is, the present invention can be realized by increasing the crystallinity of the active layer.
Any structure can be implemented.

[Knowledge about Crystal Structure Obtained by the Present Invention]
It has already been described that the crystalline silicon film obtained by the present invention is a crystal structure made up of acicular or columnar crystal aggregates as shown in FIG. Here, a comparison is made between a crystal structure according to the present invention and a crystal structure formed by another method.

The photograph shown in FIG. 11 shows the TE of the sample after the crystallization of the amorphous silicon film was completed by the procedure of Example 1.
It is M photograph. That is, the crystal structure of a crystalline silicon film not subjected to heat treatment containing a halogen element is shown.

As can be confirmed in FIG. 11, a large number of dislocation defects (inside a circle indicated by 1101) exist in the needle-like or columnar crystal immediately after crystallization. However, the TE shown in FIG.
In the M photograph, such dislocation defects are not confirmed, and it can be seen that the crystal structure is clean.

This is evidence that heat treatment in an atmosphere containing a halogen element greatly contributes to improvement of crystallinity in the present invention.

The crystal structure shown in FIG. 12 is an example in the case where the crystallization condition of the amorphous silicon film is different from that of the present invention. Specifically, an amorphous silicon film is crystallized by performing a heat treatment at 600 ° C. for 48 hours in a nitrogen atmosphere, and a thermal oxidation treatment is performed at a temperature of about 900 to 1100 ° C.

The crystalline silicon film formed as described above has a large individual crystal grain as shown in FIG. 12A, and is divided by irregularly distributed grain boundaries. FIG. 12B schematically shows FIG. 12A.

In FIG. 12B, the crystal grains 1201 are surrounded by irregular grain boundaries 1202. Therefore, when the crystal structure shown in FIG. 12A is actually used as the active layer of the TFT, the energy barrier generated by the irregular grain boundary 1202 hinders carrier movement.

On the other hand, a crystal structure as shown in FIG. 10A has a crystal grain boundary 10 as shown in FIG.
02 is arranged with a certain degree of regularity. Therefore, it is considered that there is no energy barrier that hinders carrier movement inside the needle-like or columnar crystal.

In addition, as a result of observing the array state of needle-like or columnar crystals with a wide field of view of about 1 to 50,000 times, the present inventors have confirmed that the needle-like or columnar crystals may progress zigzag. Yes. This is a phenomenon caused by crystal growth in a direction that is stable in terms of energy, and it is presumed that a kind of grain boundary is formed at a location where the crystal direction is changed.

However, the present inventors speculate that this grain boundary that may occur inside a needle-like or columnar crystal is like an energetically inactive twin grain boundary. In other words, it is a grain boundary that has different crystal directions but is continuously bonded with good consistency, and does not become an energy barrier that prevents carrier movement (substantially not considered a grain boundary). Yes.

As described above, the polycrystalline silicon (polysilicon) film crystallized by the normal process is shown in FIG.
Since it has a crystal structure as shown in FIG. 2A and irregular grain boundaries are distributed so as to block the movement of carriers, it is difficult to achieve high mobility.

However, the crystalline silicon film according to the present invention has a crystal structure as shown in FIG. 10A, the crystal grain boundaries are aligned in one direction, and the inside of the needle-like or columnar crystal is substantially energy. It is thought that there is no grain boundary as a barrier. That is, the carrier can move inside the crystal without being obstructed at all, so that extremely high mobility can be achieved.

In particular, the remarkable point of the acicular or columnar crystals obtained by the present invention is that the distance of several tens to several hundreds of μm is continuously grown while avoiding distortion caused by unevenness and stress (changing the crystal direction). It is a point that will be considered.

If the inventors' assumption is correct, the crystalline silicon film according to the present invention grows without forming a grain boundary that can be a carrier trap inside the crystal, and is a completely new crystal structure composed of a special crystal aggregate. It can be said that it is a body.

This embodiment is an example in which a CMOS circuit is formed using the TFT shown in the first embodiment. CMO
The S circuit is configured by complementarily combining an N-channel TFT and a P-channel TFT having the structure shown in the first embodiment.

One embodiment of a manufacturing process of the CMOS circuit in this embodiment will be described with reference to FIGS.
Note that the application range of the crystalline silicon film formed according to the present invention is wide, and the method for forming a CMOS circuit is not limited to this embodiment.

First, according to the manufacturing procedure shown in Embodiment 1, a silicon oxide film 502 is formed on a quartz substrate 501, and a crystalline silicon film (not shown) is obtained thereon. Then, the island-shaped semiconductor layer 503 of the N-channel TFT and the island-shaped semiconductor layer 504 of the P-channel TFT are formed by patterning it.

After the island-shaped semiconductor layers 503 and 504 are formed, heat treatment is performed in an atmosphere containing a halogen element. In this embodiment, the processing conditions are the same as those in the first embodiment. Thus, thermal oxide films 505 and 506 functioning as gate insulating films are formed with a thickness of 500 mm.

Here, for simplicity of explanation, a pair of N-channel TFT and P-channel TF is used.
An example of forming T is shown. Actually, N-channel type T in hundreds or more on the same glass substrate
FT and P-channel TFT are formed.

Next, an aluminum film (not shown) constituting a prototype of the gate electrode is formed later and patterned to form aluminum film patterns 507 and 508 (the resist mask used for patterning remains after pattern formation). deep).

As in Example 1, this aluminum film contains scandium in an amount of 0.2 wt% in order to suppress generation of hillocks and whiskers. The aluminum film is formed by sputtering or electron beam evaporation.

Hillocks and whiskers are stab-like or needle-like protrusions resulting from abnormal growth of aluminum. The presence of hillocks and whiskers causes a short circuit and crosstalk between adjacent wirings and between wirings separated between upper limits.

As materials other than the aluminum film, anodizable metals such as tantalum and molybdenum can be used. It is also possible to use a silicon film provided with conductivity instead of the aluminum film.

In this way, the state of FIG. After the aluminum film patterns 507 and 508 are formed, the aluminum film patterns 507 and 50 are then subjected to the same conditions as in the first embodiment.
Porous anodic oxide films 509, 510 are formed on the side surfaces of 8. In this embodiment, the thickness of the porous anodic oxide films 509 and 510 is 0.7 μm.

Further, dense and strong anodic oxide films 511 and 512 are formed under the same conditions as in the first embodiment. However, in this embodiment, the ultimate voltage is adjusted so that the film thickness becomes 700 mm. In addition, gate electrodes 513 and 514 are defined by this process. Thus, a state as shown in FIG. 5B is obtained.

Next, the entire surface is doped with P (phosphorus) ions as an impurity imparting N-type conductivity. This doping is performed at a high dose of 0.2 to 5 × 10 ¹⁵ atoms / cm ² , preferably 1 to 2 × 10 ¹⁵ atoms / cm ² . As a doping method, a plasma doping method or an ion doping method is used.

As a result of the process shown in FIG. 5C, regions 515 to 518 in which P ions are implanted at a high concentration.
Is formed. These regions later function as source / drain regions. (Fig. 5 (C)
)

Next, the porous anodic oxide films 509 and 510 are removed using a mixed acid solution in which acetic acid, nitric acid, and phosphoric acid are mixed. At this time, the active layer region located immediately below the anodic oxide films 509 and 510 is
Since it is not ion-implanted, it is substantially intrinsic.

Next, as shown in FIG. 5D, P ions are implanted again. This implantation of P ions has a dose amount as low as 0.1 to 5 × 10 ¹⁴ atoms / cm ² , preferably 0.2 to 1 × 10 ¹⁴ atoms / cm ² .

That is, the implantation amount of P ions performed in the step shown in FIG. 5D is lower than the dose amount performed in the step shown in FIG. Then, as a result of this step, low concentration impurity regions 519 to 522 having a lower impurity concentration than regions 515 to 518 are formed.

When the step shown in FIG. 5D is completed, the active layer of the N-channel TFT is completed. That is, a source region 515, a drain region 516, low-concentration impurity regions (or LDD regions) 519 and 520, and a channel formation region 523 of the N-channel TFT are defined.

Although not particularly illustrated, a region where ion implantation is blocked by the anodic oxide film 511 exists between the channel formation region 523 and the low-concentration impurity regions 519 and 520. This region is called an offset region, and the distance is determined by the thickness of the anodic oxide film 511.

The offset region is substantially intrinsic without being ion-implanted, but does not form a channel because a gate voltage is not applied, and functions as a resistance component that relaxes electric field strength and suppresses deterioration.
However, when the distance (offset width) is short, it does not function as an effective offset region. In this embodiment, since the width is 700 mm, it does not function as an offset area.

Next, as shown in FIG. 6A, a resist mask 524 covering the left N-channel TFT is left.
Form. Then, B (boron) ions are implanted as an impurity imparting P-type in the state shown in FIG.

Here, the dose amount of B ions is 0.2 to 10 × 10 ¹⁵ atoms / cm ² , preferably 1 to 2 × 10 ^15.
About atoms / cm ² . This dose amount is set to be approximately the same as or more than the dose amount in the P ion implantation step shown in FIG.

Through this process, the conductivity types of the impurity (P ion) regions 517, 518, 521, and 521 are all inverted from the N type to the P type, and the source region 525 and the drain region 52 of the P channel TFT are obtained.
6 is formed. A channel formation region 527 is formed immediately below the gate electrode 514.

Next, after the step shown in FIG. 6A, the resist mask 524 is removed, and the entire surface of the substrate is irradiated with intense light such as laser light, infrared light, or ultraviolet light. The impurity ions added by this step are activated and the damage of the region into which the impurity ions are implanted is recovered. (Fig. 6 (
B))

Next, when the state shown in FIG. 6B is obtained, an interlayer insulating film 528 is formed to a thickness of 4000 mm.
The interlayer insulating film 528 may be any of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, and an organic resin film, and may have a multilayer structure. These insulating films can be formed by plasma CVD, thermal CV
A D method or a spin coating method may be used.

Next, contact holes are formed, and a source electrode 529 of an N-channel TFT and a source electrode 530 of a P-channel TFT are formed. The drain electrode 531 is configured to be shared by the N-channel TFT and the P-channel TFT, thereby realizing a CMOS circuit. (Fig. 6 (C))

Through the above process, a CMOS circuit having the structure shown in FIG. 6C can be manufactured. A CMOS circuit is an inverter circuit having the simplest configuration, and a closed circuit formed by connecting an odd number of CMOS inverter circuits in series is called a ring oscillator and is used for evaluating the operation speed of a semiconductor device.

Here, the top view photograph shown in FIG. 7A is a ring oscillator circuit configured by combining CMOS circuits manufactured according to this embodiment. The present inventors actually made a prototype of an active matrix type liquid crystal display device using the present invention, and confirmed the operation performance of the drive circuit with a ring oscillator.

The gate electrode width of the CMOS circuit constituting the ring oscillator shown in FIG.
As thin as 0.6 μm, the channel formation region is usually miniaturized to such an extent that a short channel effect occurs.

FIG. 7B shows a photograph of the shift register circuit as a reference. The shift register circuit shown in FIG. 7B is one of important circuits constituting the prototype peripheral drive circuit, and is a logic circuit for designating the address of the pixel region. In particular, the horizontal scanning (source side) shift register circuit is required to be driven at a very high frequency of about several MHz to several tens of MHz during actual operation.

The oscillation frequency of the ring oscillator circuit was measured with a ring oscillator to which 9, 19, and 51 sets (stages) of CMOS circuits were connected. As a result, it was found that an oscillation frequency of 300 MHz or higher, more than 500 MHz was obtained with a 9-stage ring oscillator with a power supply voltage of 3 to 5 V, and the operating speed was extremely high.

These values mean that the operating speed is nearly 20 times that of a ring oscillator manufactured in the conventional manufacturing process. Moreover, even if the power supply voltage is varied in the range of 1 to 5 V, an oscillation frequency of several tens to several hundreds of MHz is always realized.

The ring oscillator circuit is a test pattern for evaluating the operation speed. When a logic circuit such as a shift register circuit or a processor circuit is actually configured, it is inevitable that the operation speed decreases. This is because various additional capacitors are added to the logic circuit itself.

However, a CMOS circuit using the present invention can be operated at high speed without any problem even in a situation where such added value is added, and has a performance meeting the requirements of all logic circuits.

Furthermore, despite the extremely fine channel length of 0.6 μm, the present invention also has a high breakdown voltage characteristic that can withstand extremely high speed operation as shown in this embodiment. This means that the TFT is hardly affected by the short channel effect and has extremely high reliability.

[Inference derived from the configuration of the present invention]
As shown in Example 1 and Example 2, TFTs manufactured according to the present invention achieve extremely high performance (high-speed operation characteristics, high breakdown voltage characteristics). In particular, conventional TFTs that have an S value of 60 to 100 mV / dec and a field effect mobility (μFE) in the range of 150 to 300 cm ² / Vs (which is considered to be higher in actual field effect mobility, as will be described later). Then it was impossible to achieve.

In addition, it can be said that this characteristic of being resistant to deterioration while having such a high-speed operation characteristic is a peculiar phenomenon from experience. Therefore, the present inventors considered why the TFT according to the present invention is so excellent in deterioration resistance, and inferred one theory from the reason, will be described below.

In order to increase the breakdown voltage (source-drain breakdown voltage) of a TFT, an offset region or an LDD region is generally provided between a channel formation region and a source / drain region. However, the inventors' experience has shown that even with such a structure, significant degradation occurs when the mobility exceeds 150 cm ² / Vs.

Therefore, the inventors attach importance to the influence of the crystal grain boundary of the needle-like or columnar crystal as the reason why the TFT of the present invention has a high breakdown voltage. This crystal grain boundary is composed of an oxide (silicon oxide) in which a metal element that promotes crystallization is removed by heat treatment containing a halogen element, and at the same time, dangling bonds of silicon atoms are combined with oxygen. Yes.

That is, the present inventors effectively applied a high electric field in which a grain boundary (oxide region) locally existing in the channel formation region is applied between the source region and the drain region, particularly between the channel formation region and the drain region. I guessed it was relaxed.

Specifically, the electric field formed by the depletion layer charge that spreads from the drain region, particularly in the oxide region, is suppressed, and the drain voltage is increased (the drain side depletion layer charge is increased). It was thought that it functions so as not to change the diffusion potential on the source side.

In summary, when the crystalline silicon film according to the present invention is used for the active layer, the channel formation region can be regarded as satisfying the following configuration.
(1) There is a substantially intrinsic region (inside the needle-like or columnar crystal) where the carrier moves (for the carrier).
(2) Suppressing carrier movement or channel direction (direction connecting source and drain)
There is an impurity region (oxide region) that relaxes the electric field applied to the substrate.

Therefore, by satisfying the above two configurations, in other words, having a channel formation region that is substantially intrinsic to the carrier and a locally formed impurity region, it has excellent characteristics as shown in the present invention. It is considered that a TFT can be manufactured.

The above configuration is derived from the experimental data of the present inventors, although with some assumptions. Therefore, the present inventors expected that the same effect could be obtained by artificially creating this configuration.

As a result, the present inventors have proposed a configuration effective for suppressing the short channel effect. Here, the outline is described below. In addition, the considerations described below are limited to the scope of estimation at present.

In general, as the device element (MOSFET, TFT, etc.) becomes finer and the channel length becomes shorter, the short channel effect becomes a problem. The short channel effect is a decrease in threshold voltage,
It is a general term for the breakdown of breakdown voltage and the deterioration of subthreshold characteristics associated with the punch-through phenomenon.

A particularly problematic punch-through phenomenon is a phenomenon in which the diffusion potential on the source side decreases due to the influence of the electric field on the drain side, and a current flows between the source and drain even when no channel is formed. That is, the drain depletion layer extends to the source region, so that the drain electric field affects the source side.

Therefore, the present inventors pay attention to the effect of the grain boundary (oxide region) of the present invention, and the channel length is
In a short channel TFT of about 0.01 to 2 μm, it is estimated that an effect of suppressing the spread of the depletion layer on the drain side can be obtained by providing the impurity region artificially and locally in the channel formation region.

Such a configuration can be achieved by making the active layer as shown in FIG. In FIG. 8A, reference numeral 801 denotes a source region, 802 denotes a drain region, and 803 denotes a channel formation region. An impurity region 804 is artificially formed in the channel formation region 803.
In the channel formation region 803, a region 805 other than the impurity region 804 is a substantially intrinsic region and serves as a region where carriers move.

Here, it is important that the structure shown in FIG. 8A is a structure imitating the crystal structure of the present invention shown in FIG. That is, the crystal grain boundary indicated by 1001 in FIG. 10 corresponds to the impurity region 804 in FIG. 8A, and the needle-like or columnar crystal in FIG.
This corresponds to 05.

Accordingly, the impurity region 804 disposed in the channel formation region 803 locally forms a region with a large built-in potential (also referred to as an energy barrier) in the channel formation region, and the energy barrier effectively spreads the drain side depletion layer. It can be speculated that it will be suppressed.

FIG. 8B is a cross-sectional view taken along line AA ′ of FIG. Reference numeral 806 denotes a substrate having an insulating surface. 8C is a cross-sectional view taken along the line BB ′ of FIG.

In FIG. 8C, wpi, n represents the width of the impurity region 804, and wpa, m represents the width of the region in which carriers move. Here, n and m in the channel formation region 803 mean that wpi, n is the width of the nth impurity region, and wpa, m is a region where the mth carrier moves.

The widths of wpi, n and wpa, m must satisfy a certain range of conditions. This will be described below.

In FIG. 8A, the width of the channel formation region 803, that is, the channel width is W. Here, of the channel width W, the width occupied by the impurity region 804 is defined as Wpi. And
If the width of an arbitrary impurity region is Wpi, ₁ , Wpi, ₂ , Wpi, ₃ ... Wpi _{, n} , Wpi is expressed by the following equation.

However, in order to achieve this configuration, at least one impurity region needs to be formed in a region other than the end portion of the channel formation region, so n must be an integer of 1 or more.

Of the channel width W, the width occupied by the carrier movement region 805 is defined as Wpa. If the moving region 805 of an arbitrary carrier is Wpa, ₁ , Wpa, ₂ , Wpa, ₃ ... Wpa _{, m} , Wpa is expressed by the following equation.

However, since at least one impurity region is formed in a region other than the end portion of the channel formation region as described above, the channel formation region must be divided into at least two and m must be an integer of 2 or more.

That is, the relationship that the total channel width W is W = Wpi + Wpa and n + m is 3 or more is established. The relationship between W and Wpi, W and Wpa, and Wpi and Wpa preferably satisfy the following conditions at the same time.
Wpi / W = 0.1-0.9
Wpa / W = 0.1-0.9
Wpi / Wpa = 1/9 to 9

The meaning of these mathematical expressions is that Wpa / W or Wpi / W must not be 0 or 1. For example, in the case of Wpa / W = 0 (synonymous with Wpi / W = 1), the channel formation region is completely blocked by the impurity region, so that carrier movement is inhibited. Conversely, Wpa
In the case of / W = 1 (synonymous with Wpi / W = 0), the impurity region does not exist at all in the channel formation region, so that the spread of the drain side depletion layer cannot be suppressed.

In addition, the knowledge related to Equations 1 and 2 plays an important role in explaining the TFT characteristics found in Example 1 and Example 2. This is shown below.

The inventors noticed that the oscillation frequency of the ring oscillator shown in Example 2 is too high for the mobility value shown in Example 1. That is, it was thought that the numerical value may differ between the actual mobility and the mobility obtained by measurement.

The present inventors consider that the measured mobility value is smaller than the actual mobility (the mobility inherent in the TFT of the present invention). The reason is that the measured channel width W is substituted into the following equation for calculating the mobility in the measurement by the present inventors.

μFE = 1 / Cox (ΔId / ΔVg) · 1 / Vd · L / W
Here, Cox is the gate oxide film capacitance, ΔId and ΔVg are the amounts of change in the drain current Id and the gate voltage Vg, Vd is the drain voltage, and L and W are the channel length and channel width, respectively.

As is apparent from this equation, the field effect mobility (μFE) is inversely proportional to the channel width W. In the measurement, calculation is performed by substituting the channel width actually measured by a measuring machine as a value for W.

However, as described using Equations 1 and 2, an oxide layer is actually formed between the needle-like or columnar crystals, and the effective channel width Wpa is obtained by subtracting the oxide layer. Must be defined. That is, the assigned channel width W is equal to the effective channel width W.
It is a value larger than pa.

For the above reason, since the mobility calculated by substituting a channel width larger than the actual one is obtained, it is considered that the apparent mobility is calculated to be small. Therefore,
In accordance with the present invention, it is presumed that a TFT achieving a mobility exceeding 400 cm ² / Vs is actually realized. And it can be said that the oscillation frequency exceeding 500 MHz as shown in the embodiment 2 can be realized because such mobility is achieved.

Further, it is expected that providing the impurity regions in an arrangement as shown in FIG. 8A has a very significant meaning for improving the mobility. The reason will be described below.

The mobility (μFE) is determined by scattering of carriers in a semiconductor film (here, a silicon film is taken as an example), and scattering in the silicon film is roughly divided into lattice scattering and impurity scattering. Lattice scattering has a low impurity concentration in the silicon film and is dominant at relatively high temperatures, and impurity scattering has a high impurity concentration,
It is dominant at relatively low temperatures. The overall mobility μ formed by these influences is expressed by the following equation.

The equation shown in Equation 5 is obtained when the overall mobility μ is affected by the reciprocal of mobility μ _l when _l is affected by lattice scattering ( _l means lattice) and by impurity scattering. Mobility μ
_It means inversely proportional to the sum of the reciprocals of _i ( _i means impurity).

Here, if the drift electric field is not so strong in the lattice scattering, the acoustic phonon plays an important role, and the mobility μ _l at that time is proportional to the −3/2 power of the temperature as shown in the following equation. Therefore, it is determined by the effective mass (m *) and temperature (T) of the carrier.

Moreover, the mobility mu _i due to impurity scattering is proportional to 3/2 power of the temperature as indicated by the following expression and inversely proportional to the concentration N _i of ionized impurities. That can be varied by adjusting the concentration N _i of ionized impurities.

According to these formulas, mobility cannot be obtained due to the influence of impurity scattering in a state where impurities are uniformly added to the entire channel formation region. However, in the case of the structure shown in FIG. 8, since the impurity region is locally formed, no impurity is added to the region where the carrier moves, which is substantially intrinsic to the carrier.

In other words, it means that the closer to 0 without limit concentration N _i of impurities ionized in the number 7 in theory, the mobility mu _i will be approaching infinity as possible. That is, in Equation 5, it means that impurities are reduced to such an extent that the term of 1 / μ _i can be ignored, so it is estimated that the entire mobility μ approaches the mobility μ _l without limit.

In FIG. 8A, it is important that the impurity region 804 is arranged so as to be substantially parallel to the channel direction. Such an arrangement corresponds to the case where the direction in which the crystal grain boundary of the needle-like or columnar crystal shown in FIG. 10 extends matches the channel direction.

In such an arrangement, the impurity region 804 is expected to behave as a “benign crystal grain boundary”. Therefore, it is presumed that the moving direction is defined for the carrier by playing a role like a rail without capturing the carrier. The This is a very important configuration for reducing the influence of scattering caused by collision between carriers.

In addition, with the above configuration, it is expected that a decrease in threshold voltage, which is one of the short channel effects, can be suppressed. This is an expectation based on the inference that the narrow channel effect that occurs when the channel width becomes extremely narrow can be artificially caused between the impurity regions.

Further, as described above, it is considered possible to suppress the punch-through phenomenon by suppressing the spread of the drain side depletion layer. However, by suppressing the punch-through phenomenon, the breakdown voltage is improved and the subthreshold characteristic (S value). Can also be improved.

The improvement in the subthreshold characteristic can be explained as follows from the inference that the volume occupied by the drain side depletion layer can be reduced by using this configuration.

If the spread of the depletion layer is effectively suppressed in the configuration shown in FIG. 8A, it should be possible to significantly reduce the volume occupied by the drain side depletion layer. Therefore, it is considered that the depletion layer capacitance can be reduced because the total charge of the depletion layer can be reduced. Here, the equation for deriving the S value is expressed by the following equation.

This equation represents the reciprocal of the slope of the rising portion of the Id-Vg characteristic (near the gate voltage of 0 V) in the graph shown in FIG. Further, the expression expressed by Equation 3 can be approximately expressed as the following expression.

In Equation 4, k is the Boltzmann constant, T is the absolute temperature, q is the charge amount, Cd is the depletion layer capacitance,
Cit is the interface state equivalent capacitance, and Cox is the gate oxide film capacitance. Therefore, in this configuration, the depletion layer capacitance Cd is sufficiently smaller than the conventional one, so that the S value can be set to a small value of 85 mV / decade or less, that is, an excellent subthreshold characteristic can be obtained.

In addition, by bringing the depletion layer capacitance Cd and the interface state equivalent capacitance Cit as close as possible to 0, it is possible to realize an ideal state where Cd = Cit = 0, that is, a semiconductor device having an S value of 60 mV / decade. There is.

By the way, in the present invention, the crystal grain boundaries of needle-like or columnar crystals are composed of oxides, but in this configuration inferred therefrom, nitrogen or nitrogen other than oxygen is used as an impurity region corresponding to the crystal grain boundaries of the present invention. Carbon may be used. This is because the purpose of this configuration is to artificially arrange an energy barrier with respect to the channel formation region.

Therefore, from the viewpoint of forming an energy barrier, it can be said that an impurity region having a conductivity type opposite to that of the inversion layer is also effective. That is, it can be said that an impurity region may be formed using B ions for an N-channel semiconductor device and P ions for a P-channel H semiconductor device.

When the impurity region is composed of P or B ions, the threshold value can be directly controlled by the concentration of the impurity ions to be added.

As described above, this configuration is a technique derived by the inventors' estimation based on the configuration and experimental facts of the invention disclosed in this specification. By implementing this configuration, it is estimated that the short channel effect, which is a problem in a semiconductor device in a deep submicron region with an extremely short channel length, can be effectively suppressed.

In this example, an example in which the crystalline silicon film shown in Example 1 is formed on a silicon wafer is shown. In this case, an insulating layer needs to be provided on the surface of the silicon wafer, but usually a thermal oxide film is often used.

The temperature range of the heat treatment is generally 700 to 1300 ° C., and the treatment time varies depending on the desired oxide film thickness.

Further, thermal oxidation of a silicon wafer is usually performed in an atmosphere such as O ₂ , O ₂ —H ₂ O, H ₂ O, O ₂ —H ₂ combustion. In addition, oxidation in an atmosphere to which a halogen element such as HCl or Cl ₂ is added has been widely put into practical use.

Silicon wafers are one of the bases indispensable for semiconductor devices such as ICs, and techniques for forming various semiconductor elements on the wafers have been created.

According to the present embodiment, a crystalline silicon film having crystallinity comparable to that of a single crystal can be combined with a technique using a conventional silicon wafer to further expand the application range of the crystalline silicon film.

It is also possible to form an integrated circuit in which TFTs are formed on an IC on a silicon wafer and semiconductor devices are arranged three-dimensionally.

In this embodiment, a TFT manufactured by applying the present invention is a DRAM (Dynamic Rondom Access).
An example applied to (Memory) will be described. FIG. 13 is used for the description.

A DRAM is a type of memory that stores stored information as electric charges in a capacitor. The input / output of electric charge as information to the capacitor is controlled by a TFT connected in series to the capacitor. FIG. 13 shows a circuit of TFT and capacitor constituting one memory cell of DRAM.
Shown in (A).

When a gate signal is supplied by the word line 1301, the TFT indicated by 1303 is turned on. In this state, the capacitor 1304 is charged with charge from the bit line 1302 side to read information, or the charge is taken out from the charged capacitor to read information.

A cross-sectional structure of the DRAM is shown in FIG. Reference numeral 1305 denotes a substrate made of a quartz substrate or a silicon substrate.

A silicon oxide film 1306 is formed on the base 1305 as a base film, and a TFT to which the present invention is applied is formed thereon. If the base 1305 is a silicon substrate, a thermal oxide film can be used as the base film 1306. Reference numeral 1307 denotes an active layer formed according to the first embodiment.

The active layer 1307 is covered with a gate insulating film 1308, and a gate electrode 1309 is formed thereon. Then, after an interlayer insulating film 1310 is stacked thereon, a source electrode 1311 is formed. Simultaneously with the formation of the source electrode 1311, the electrodes indicated by the bit lines 1302 and 1312 are formed. Reference numeral 1313 denotes a protective film made of an insulating film.

The electrode 1312 maintains a fixed potential, and a capacitor 1304 is formed between the electrode 1312 and the drain region of the active layer existing below the electrode 1312. That is, a function as a memory element is obtained by writing or reading out the electric charge accumulated in the capacitor with a TFT.

The feature of the DRAM is that it is suitable for constructing a large scale memory with high integration density because the number of elements constituting one memory is very small with only TFTs and capacitors. Also, the price is kept low, so it is currently used in large quantities.

In addition, since the storage capacitor can be set small as a feature when a DRAM cell is formed using TFTs, it is possible to operate at a low voltage.

In this embodiment, a TFT manufactured by applying the present invention is an SRAM (Static Rondom Access M).
An example applied to emory) will be described. FIG. 14 is used for the description.

The SRAM is a memory using a bistable circuit such as a flip-flop as a storage element, and stores a binary information value (0 or 1) corresponding to the bi-stable state of ON-OFF or OFF-ON of the bistable circuit. To do. This is advantageous in that the memory is retained as long as power is supplied.

The memory circuit is composed of an N-MOS or C-MOS. The SRAM circuit shown in FIG. 14A is a circuit using a high resistance as a passive load element.

Reference numeral 1401 denotes a word line, and reference numeral 1402 denotes a bit line. Reference numeral 1403 denotes a load element having a high resistance, and an SRAM is constituted by two sets of driver transistors as indicated by 1404 and two sets of access transistors as indicated by 1405.

A cross-sectional structure of the TFT is shown in FIG. Base 1 made of quartz substrate or silicon substrate
A silicon oxide film 1407 is formed as a base film on 406, and a TFT to which the present invention is applied thereon.
Can be produced. Reference numeral 1408 denotes an active layer formed according to the first embodiment.

The active layer 1408 is covered with a gate insulating film 1409, on which a gate electrode 1410 is formed. Then, after an interlayer insulating film 1411 is stacked thereon, a source electrode 1412 is formed. Simultaneously with the formation of the source electrode 1412, a bit line 1402 and a drain electrode 1413 are formed.

An interlayer insulating film 1414 is again laminated thereon, and then a polysilicon film 1415 is formed as a high resistance load. It is also possible to adopt an SRAM structure in which a function similar to that of a high resistance load is replaced with a TFT. Reference numeral 1416 denotes a protective film made of an insulating film.

The characteristics of the SRAM configured as described above are that it can operate at high speed, is highly reliable, and can be easily incorporated into a system.

In this embodiment, an example is shown in which an active matrix electro-optical device in which a pixel matrix circuit and a logic circuit are integrated on the same substrate using the semiconductor device of Embodiment 1 and the CMOS circuit of Embodiment 2 is shown. Examples of the electro-optical device include a liquid crystal display device, an EL display device, and an EC display device.

Note that the logic circuit refers to an integrated circuit for driving the electro-optical device, such as a peripheral drive circuit or a control circuit. In the active matrix type electro-optical device, the logic circuit is generally an external IC due to the limitation of the operation performance and the degree of integration. However, by using the TFT of the present invention, everything is integrated on the same substrate. Can be realized.

The control circuit includes a processor circuit, a memory circuit, a clock generation circuit, and an A / D.
(D / A) All electric circuits necessary for driving an electro-optical device such as a converter circuit are included. Of course, the memory circuit includes the SRAM circuit and the DRAM circuit shown in the fifth and sixth embodiments.

When the invention disclosed in this specification is applied to such a configuration, a MOSF formed on a single crystal is used.
A logic circuit can be configured with TFTs having performance comparable to that of ET.

In this embodiment, an example of manufacturing a TFT having a structure different from that in Embodiment 1 is shown. FIG. 15 is used for the description.

First, the state shown in FIG. 2A is obtained through the same steps as in the first embodiment. When the state shown in FIG. 2A is obtained, the resist mask (not shown) used for patterning the aluminum film is removed, and then anodized in tartaric acid to obtain a dense anodic oxide film having a thickness of 1000 mm. . This state is shown in FIG.

In FIG. 15A, 101 is a quartz substrate, 102 is a base film, 110 is an island-shaped semiconductor layer,
Reference numeral 111 denotes a thermal oxide film that functions as a gate insulating film later. Reference numeral 1501 denotes a gate electrode made of a material mainly composed of aluminum, and reference numeral 1502 denotes a dense anodic oxide film obtained by anodizing the gate electrode 1501.

Next, impurity ions imparting one conductivity to the island-like semiconductor layer 110 are implanted in this state. Then, impurity regions 1503 and 1504 are formed by this ion implantation process.

The impurity ions may be formed using P (phosphorus) or As (arsenic) for N-channel TFTs and B (boron) for P-channel TFTs. At this time, the dose is 0
A low value of 0.1 to 5 × 10 ¹⁴ atoms / cm ² , preferably 0.2 to 1 × 10 ¹⁴ atoms / cm ² is set.

When the impurity ion implantation is completed, a silicon nitride film 1505 is formed to a thickness of 0.5 to 1 μm. The film forming method may be any of a low pressure thermal CVD method, a plasma CVD method, and a sputtering method. In addition to the silicon nitride film, a silicon oxide film may be used.

Thus, the state of FIG. 15B is obtained. When the state of FIG. 15B is obtained, the silicon nitride film 1505 is then etched by the etch-back method, leaving only the side wall of the gate electrode 1501. The silicon nitride film thus left functions as a sidewall 1506.

At this time, the thermal oxide film 111 is removed except for the region where the gate electrode is used as a mask.
It remains in the state as shown in C).

Impurity ions are implanted again in the state shown in FIG. At this time, the dose is 0.2
It is set to ˜10 × 10 ¹⁵ atoms / cm ² , preferably 1 to 2 × 10 ¹⁵ atoms / cm ^2, which is higher than the dose amount of the previous ion implantation.

At the time of this ion implantation, the regions 1507 and 1508 immediately below the sidewall 1506 are not ion-implanted, so the impurity ion concentration does not change. However, the exposed area 1
In 509 and 1510, higher-concentration impurity ions are implanted.

As described above, after the second ion implantation, the source region 1509, the drain region 1510, and the low concentration impurity region (LDD region) 15 having an impurity concentration lower than that of the source / drain region.
07 and 1508 are formed. Note that an undoped region immediately below the gate electrode 1501 is a channel formation region 1511.

When the state of FIG. 15C is obtained through the above steps, a titanium film (not shown) having a thickness of 300 mm is formed, and the titanium film and the silicon (crystalline silicon) film are reacted. After the titanium film is removed, heat treatment such as lamp annealing is performed to form titanium silicides 1512 and 1513 on the surfaces of the source region 1509 and the drain region 1510. (Fig. 15 (
D))

In the above process, a tantalum film, a tungsten film, a molybdenum film, or the like can be used instead of the titanium film. Further, in FIG. 15D, a part of the source / drain region is described as being silicided. However, depending on the conditions of the heat treatment, the entire source / drain region may be formed depending on the thin film thickness of the source / drain region. Silicidation may occur.

Next, a silicon oxide film is formed as an interlayer insulating film 1514 to a thickness of 5000 mm, and the source electrode 15
15. A drain electrode 1516 is formed. Thus, a TFT having the structure shown in FIG. 15D is completed.

In the TFT having the structure shown in this embodiment, the source / drain electrodes are titanium silicide 1512,
Since it is connected to the source / drain region via 1513, a good ohmic contact can be realized.

In this embodiment, an example of manufacturing a TFT having a structure different from that of Embodiment 1 or Embodiment 7 is shown. FIG. 16 is used for the description.

First, the state shown in FIG. 2A is obtained through the same steps as in the first embodiment. However, in this embodiment, a crystalline silicon film provided with conductivity is used as the material of the gate electrode. This state is shown in FIG.

In FIG. 16A, 101 is a quartz substrate, 102 is a base film, 110 is an island-shaped semiconductor layer,
Reference numeral 111 denotes a thermal oxide film that functions as a gate insulating film later. Reference numeral 1601 denotes a gate electrode made of a crystalline silicon film (polysilicon film).

Next, impurity ions imparting one conductivity to the island-like semiconductor layer 110 are implanted in this state. Impurity regions 1602 and 1603 are formed by this ion implantation process. (Fig. 16B)

The impurity ions may be formed using P (phosphorus) or As (arsenic) for N-channel TFTs and B (boron) for P-channel TFTs. At this time, the dose is 0
A low value of 0.1 to 5 × 10 ¹⁴ atoms / cm ² , preferably 0.2 to 1 × 10 ¹⁴ atoms / cm ² is set.

When the impurity ion implantation is completed, the sidewalls 1604 are formed using the etch-back method as in the seventh embodiment.

After the sidewall 1604 is formed, impurity ions are implanted again. At this time, the dose is set to 0.2 to 10 × 10 ¹⁵ atoms / cm ² , preferably 1 to 2 × 10 ¹⁵ atoms / cm ^2, which is higher than the dose of the previous ion implantation. (Fig. 16 (C))

During this ion implantation, the regions 1605 and 1606 immediately below the sidewall 1604 are not ion-implanted, so that the impurity ion concentration does not change. However, the exposed area 1
In 607 and 1608, impurity ions of higher concentration are implanted.

As described above, after the second ion implantation, the source region 1607, the drain region 1608, and the low concentration impurity region (LDD region) 16 having an impurity concentration lower than that of the source / drain region.
05, 1606 are formed. Note that an undoped region immediately below the gate electrode 1601 is a channel formation region 1609.

When the state shown in FIG. 16C is obtained through the above steps, a tungsten film (not shown) having a thickness of 500 mm is formed, and the tungsten film and the silicon film are reacted. Then, after removing the tungsten film, the gate electrode 1601,
Tungsten silicide 1610 on the surface of the source region 1607 and the drain region 1608
~ 1612 are formed. (FIG. 16D)

Needless to say, a titanium film, a molybdenum film, or a tantalum film can be used in addition to the tungsten film. Further, in this embodiment, the heat treatment time is set to be long and adjusted so that the entire source / drain region is silicided.

Next, a silicon nitride film is formed as an interlayer insulating film 1613 to a thickness of 4000 mm, and the source electrode 16
14 and the drain electrode 1615 are formed. Thus, a TFT having the structure shown in FIG.

The TFT having the structure shown in this embodiment can realize a good ohmic contact because the gate electrode and the source / drain electrode are connected to the extraction electrode through the tungsten silicide 1610 to 1612.

In this embodiment, an example of an electro-optical device (display device) incorporating a semiconductor device using the present invention is shown. The electro-optical device may be used in a direct view type or a projection type as necessary. Further, since an electro-optical device is also considered to function using a semiconductor, the electro-optical device in this specification is included in the category of a semiconductor device.

Further, application products of semiconductor devices using the present invention include TV cameras, head mounted displays, car navigation, projections (front and rear types), video cameras, personal computers, and the like. A simple example of these application uses will be described with reference to FIG.

FIG. 17A illustrates a TV camera, which includes a main body 3001, a camera portion 3002, and a display device 300.
3 and operation switch 3004. The display device 3003 is used as a viewfinder.

FIG. 17B illustrates a head mounted display, which includes a main body 3101 and a display device 3102.
, And a band unit 3103. Two display devices 3102 having a relatively small size are used.

FIG. 17C illustrates car navigation, which includes a main body 3201, a display device 3202, operation switches 3203, and an antenna 3204. Although the display device 3202 is used as a monitor, it can be said that the allowable range of resolution is relatively wide because the main purpose is to display a map.

FIG. 17D illustrates a portable information terminal device (a mobile phone in this embodiment), which includes a main body 3301, an audio output unit 3302, an audio input unit 3303, a display device 3304, operation buttons 3305, and an antenna 3306. It is expected that the display device 3303 will be requested to display a moving image as a TV phone in the future.

FIG. 17E illustrates a video camera, which includes a main body 3401, a display device 3402, and an eyepiece unit 340.
3, an operation switch 3404 and a tape holder 3405. Since the captured image displayed on the display device 3402 can be viewed in real time through the eyepiece 3403,
The user can take a picture while viewing the image.

FIG. 17D illustrates a front projection, which includes a main body 3501, a light source 3502, a reflective display device 3503, an optical system (including a beam splitter, a polarizer, and the like) 3504 and a screen 3505. Since the screen 3505 is a large screen used for presentations such as conferences and conference presentations, the display device 3503 is required to have a high resolution.

In addition to the electro-optical device shown in this embodiment, the present invention can be applied to portable information terminal devices such as rear projection, mobile computers, and handy terminals. As described above, the application range of the present invention is extremely wide and can be applied to display media in various fields.

The TFT of the present invention is not limited to an electro-optical device, but can be incorporated into an integrated circuit in the form of SRAM or DRAM, for example, and used as a drive circuit for an application product as shown in this embodiment.

10A and 10B illustrate a manufacturing process of a semiconductor device. 10A and 10B illustrate a manufacturing process of a semiconductor device. The figure which shows the arrangement configuration of an island-shaped semiconductor layer. FIG. 6 shows characteristics of a semiconductor device. The figure which shows a semiconductor device field manufacturing process. The figure which shows the manufacturing process of a semiconductor device The microscope picture which shows the structure of an electric circuit. The figure which shows the structure of an active layer. A photograph showing the surface of a crystalline silicon film. A photograph showing the crystal structure. A photograph showing the crystal structure. A photograph showing the crystal structure. Diagram showing the configuration of DRAM The figure which shows the structure of SRAM 10A and 10B illustrate a manufacturing process of a semiconductor device. 10A and 10B illustrate a manufacturing process of a semiconductor device. FIG. 10 illustrates an application example of a semiconductor device.

Explanation of symbols

101 Quartz substrate 102 Base film 103 Amorphous silicon film 104 Silicon oxide film (mask insulating film)
105 A region 106 where an amorphous silicon film is exposed 106 A nickel-containing water film 107 A crystalline silicon film 108 An arrow 109 indicating a crystallization direction Nickel-added region 110 An island-like semiconductor layer 111 A thermal oxide film 112 An aluminum film pattern 113 Porous Anodic oxide film 114 dense anodic oxide film 115 gate electrode 116, 117 impurity region 118, 119 low concentration impurity region 120 channel formation region 121 interlayer insulating film 122 source electrode 123 drain electrode 301 quartz substrate 302 nickel added region 303 macroscopic Grain boundary 304 Island-like semiconductor layer 801 Source region 802 Drain region 803 Channel formation region 804 Impurity region 805 Carrier moving region 1001 Needle-like or columnar crystal grain boundary

Claims (20)

Forming an amorphous silicon film on a substrate having an insulating surface;
Selectively forming a mask insulating film on the amorphous silicon film;
A metal element that promotes crystallization is selectively introduced into the amorphous silicon film using a mask insulating film as a mask,
At least part of the amorphous silicon film is converted into a crystalline silicon film by the first heat treatment,
Removing the mask insulating film;
An island-like crystalline silicon film is formed by patterning,
By performing a second heat treatment in an atmosphere containing a halogen element, the metal element in the island-shaped crystalline silicon film is gettered and removed, and a thermal oxide film used as a gate insulating film is formed in the island-shaped film. Formed on the surface of the crystalline silicon film,
Forming a gate electrode on the thermal oxide film;
Impurity ions imparting one conductivity are implanted into the island-shaped crystalline silicon film to form a source region and a drain region in the island-shaped crystalline silicon film,
A method for manufacturing a semiconductor device, comprising: forming a metal film over the source region and the drain region, and siliciding the source region and the drain region. Forming an amorphous silicon film on a substrate having an insulating surface;
Selectively forming a mask insulating film on the amorphous silicon film;
A metal element that promotes crystallization is selectively introduced into the amorphous silicon film using a mask insulating film as a mask,
At least part of the amorphous silicon film is converted into a crystalline silicon film by the first heat treatment,
Removing the mask insulating film;
An island-like crystalline silicon film is formed by patterning,
By performing a second heat treatment in an atmosphere containing a halogen element, the metal element in the island-shaped crystalline silicon film is gettered and removed, and a thermal oxide film used as a gate insulating film is formed in the island-shaped film. Formed on the surface of the crystalline silicon film,
Forming a gate electrode on the thermal oxide film;
Impurity ions imparting one conductivity are implanted into the island-shaped crystalline silicon film,
Forming a silicon nitride film or a silicon oxide film so as to cover the gate electrode and the island-shaped crystalline silicon film, and etching the silicon nitride film or the silicon oxide film to form a sidewall on the side surface of the gate electrode; Impurity ions that impart the one conductivity are implanted into the island-shaped crystalline silicon film, and a source region, a drain region, and an LDD region are formed in the island-shaped crystalline silicon film,
A method for manufacturing a semiconductor device, comprising: forming a metal film over the source region and the drain region; and siliciding the source region and the drain region In any one of Claim 1 or Claim 2,
A method of manufacturing a semiconductor device, wherein the amorphous silicon film is formed by a low pressure thermal CVD method. In any one of Claim 1 thru | or Claim 3,
Any one of a tungsten film, a titanium film, a molybdenum film, and a tantalum film is used as the metal film. In any one of Claims 1 thru | or 4,
One or more kinds of elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used as the metal element for promoting the crystallization. Device fabrication method. In any one of Claims 1 thru | or 5,
The atmosphere containing the halogen element is an oxygen atmosphere to which one or plural kinds of gases selected from HCl, HF, HBr, Cl ₂ , ClF ₃ , BCl ₃ , NF ₃ , F ₂ and Br ₂ are added. A method for manufacturing a semiconductor device. In any one of Claims 1 thru | or 6,
The first heat treatment is performed in a temperature range of 450 to 700 ° C.,
The method for manufacturing a semiconductor device, wherein the second heat treatment is performed in a temperature range exceeding 700 ° C.
A crystalline silicon film formed on a substrate having an insulating surface;
A thermal oxide film used as a gate insulating film formed on the surface of the crystalline silicon film;
An insulating gate type semiconductor device having a gate electrode on the gate insulating film,
The crystalline silicon film has a source region and a drain region which are partly or entirely silicided. A crystalline silicon film formed on a substrate having an insulating surface;
A thermal oxide film used as a gate insulating film formed on the surface of the crystalline silicon film;
A gate electrode on the gate insulating film;
An insulating gate type semiconductor device having a sidewall made of silicon nitride or silicon oxide formed on a side surface of the gate electrode,
The crystalline silicon film has an LDD region, and a source region and a drain region partially or entirely silicided. In any one of Claim 8 or Claim 9,
The S value representing the electrical characteristics of the semiconductor device is 60 to 100 mV / dec for the N channel type, or 70 to 100 mV / dec for the P channel type. In any one of Claims 8 to 10,
The standard deviation of the S value representing the electrical characteristics of the semiconductor device is within 10 mV / dec for the N channel type or within 15 mV / dec for the P channel type. In any one of Claims 8 thru | or 11,
The crystalline silicon film is a silicon film that is heat-treated in an atmosphere containing a halogen element,
A concentration of the halogen element in the crystalline silicon film is 1 × 10 ¹⁵ to 1 × 10 ²⁰ atoms / cm ³ . In any one of Claims 8 to 12,
A part of or all of the silicided source region and drain region is any one of tungsten silicide, titanium silicide, tantalum silicide, and molybdenum silicide. In any one of Claims 8 to 13,
2. The semiconductor device according to claim 1, wherein the crystalline silicon film is formed by collecting a plurality of needle-like or columnar crystals substantially parallel to the substrate. In any one of Claims 8 to 14,
The length of the channel formation region in the crystalline silicon film is 0.01 to 2 μm. In any one of Claims 8 thru | or 15,
The crystalline silicon film is a silicon film crystallized by introducing a metal element for promoting crystallization into amorphous silicon,
The semiconductor device is characterized in that the concentration of the metal element for promoting crystallization in the crystalline silicon film is 1 × 10 ¹⁸ atoms / cm ³ or less. In claim 16,
The metal element that promotes crystallization is one or more kinds of elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au. .   A DRAM formed using the semiconductor device according to claim 1.   An SRAM formed using the semiconductor device according to claim 1.   An active matrix electro-optical device in which a pixel matrix circuit and a logic circuit formed using the semiconductor device according to claim 1 are integrated on the substrate.