JPH09289167A - Semiconductor thin film, manufacture thereof, semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a mono-domain region equivalent in crystallinity to a single crystal to be formed on a substrate with an insulating surface, by a method wherein a semiconductor thin film possessed of a mono-domain region formed of aggregated columnar or needle crystals nearly in parallel with the substrate is formed on the substrate with an insulating film. SOLUTION: A silicon oxide film 202 is formed on a substrate 201 with an insulating surface, and then a non-crystal silicon film 203 is formed thereon. Then, the substrate 201 is irradiated with UV rays, whereby a silicon oxide film 204 is formed, the oxide film 204 is removed by etching from a region where nickel is introduced, nickel elements are held coming into contact with a region 205 on the non-crystal silicon film 203 through the intermediary of an oxide film, hydrogen is expelled, and then a thermal treatment is carried out to crystallize the non-crystal silicon film 203. At this point, columnar or needle crystals are grown nearly in parallel with a substrate. Then, an obtained crystalline silicon film 207 is thermally treated at a high temperature, whereby crystal grain boundaries are bonded together high in conformity, and a lateral growth region itself is made to serve as a mono-domain region.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor thin film having a region that can be regarded as a substantially single crystal (hereinafter referred to as a monodomain region) formed on a substrate having an insulating surface, and a semiconductor device including the semiconductor thin film as an active layer. In particular, the present invention relates to a thin film transistor having an active layer made of a crystalline silicon film.

[0002]

2. Description of the Related Art In recent years, a technique for forming a thin film transistor (TFT) by using a thin silicon semiconductor film (having a thickness of several hundreds to several thousands Å) formed on a substrate having an insulating surface has received attention. Thin film transistors have been widely applied to electronic devices such as ICs and liquid crystal display devices.

The important part which should be called the heart of the thin film transistor is a channel forming region and a junction part for joining the channel forming region and the source / drain regions. That is, it can be said that the active layer most affects the performance of the thin film transistor.

As a semiconductor thin film forming an active layer of a thin film transistor, an amorphous silicon film (amorphous silicon film) formed by a plasma CVD method or a low pressure thermal CVD method is generally used.

At present, a thin film transistor using an amorphous silicon film has been put into practical use, but a silicon thin film having crystallinity (referred to as a crystalline silicon film) is used when higher speed operation is required. A thin film transistor utilized is needed.

As a method for forming a crystalline silicon film on a substrate, the applicant of the present invention has disclosed Japanese Patent Laid-Open Nos. 6-232059 and 6-
The technique described in Japanese Patent No. 244103 is known. The technique described in this publication forms a crystalline silicon film having excellent crystallinity by heat treatment at 550 ° C. for about 4 hours by utilizing a metal element that promotes crystallization of silicon. .

Further, the technique described in Japanese Patent Application Laid-Open No. 7-321339 applies the above technique to perform crystal growth substantially parallel to the substrate, and the inventors of the present invention particularly laterally grow the formed crystallization region. It is called the area (or lateral growth area).

The lateral growth region formed by such a technique is
It is a region in which columnar or needle-shaped crystals are gathered in a state in which the traveling directions are aligned, and has a characteristic of excellent crystallinity. Therefore, it is known that a thin film transistor having an active layer formed by utilizing this region has high performance.

However, even with the above technique, there is a feeling that the thin film transistor for forming various arithmetic circuits, memory circuits, etc. is insufficient in its function. This is because the crystallinity is still insufficient and the required properties cannot be obtained.

For example, a peripheral circuit of an active matrix type liquid crystal display device or a passive type liquid crystal display device, a driving circuit for driving a pixel TFT arranged in a pixel region, a circuit for handling and controlling a video signal, A memory circuit or the like for storing various kinds of information is required.

Among these circuits, a circuit for handling and controlling a video signal and a memory circuit for storing various information are
It is required to have performance comparable to that of an integrated circuit using a known single crystal wafer. Therefore, in order to integrate these circuits using a thin film semiconductor formed on a substrate, it is necessary to form a crystalline silicon film having crystallinity comparable to a single crystal on the substrate.

Further, according to the means described in the above-mentioned publication, the metal element used in the crystallization remains in the crystalline silicon film, and the reproducibility and the reproducibility of the semiconductor device when the semiconductor device is actually formed are It has been suggested by the present inventors that it becomes an anxiety factor that affects stability.

[0013]

SUMMARY OF THE INVENTION An object of the invention disclosed in the present specification is to form a monodomain region having crystallinity comparable to a single crystal on a substrate having an insulating surface. Then, it is an object to obtain a semiconductor device in which an active layer is formed by the monodomain region.

[0014]

The structure of the invention disclosed in the present specification is a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is in a columnar or needle-like shape substantially parallel to the substrate. It is characterized by having a monodomain region formed by a plurality of crystals being aggregated.

According to another aspect of the invention, there is provided a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is formed by assembling a plurality of columnar or needle crystals substantially parallel to the substrate. The monodomain region has substantially no crystal grain boundaries, and the semiconductor thin film forming the monodomain region contains hydrogen and halogen elements at a concentration of 5 atomic% or less. The halogen element is an element selected from chlorine, bromine and fluorine.

A semiconductor device having a structure of another invention uses only the monodomain region as an active layer. The inside of this monodomain region is characterized by the absence of grain boundaries.

According to another aspect of the invention, a step of forming an amorphous silicon film by a low pressure thermal CVD method on a substrate having an insulating surface, and a silicon oxide film selectively on the amorphous silicon film. And a step of holding a metal element that promotes crystallization in the amorphous silicon film, and at least a part of the amorphous silicon film becomes a crystalline silicon film by the first heat treatment. A step of transforming, a step of removing the silicon oxide film, and a second heat treatment in an atmosphere containing a halogen element are performed to remove the halogen element on the amorphous silicon film and / or the crystalline silicon film. At least a step of forming a contained thermal oxide film and a step of removing the thermal oxide film are included, and the crystalline silicon film is transformed into a monodomain region by the second heat treatment. . Further, it is characterized in that the active layer is constituted by a mono domain region formed through these steps.

The present inventors defined the lateral growth region obtained by the present invention as a region which can be regarded as a substantially single crystal, and defined that region as a monodomain region. The feature of the monodomain region is that there is substantially no grain boundary in the region,
That is, there are almost no crystal defects caused by dislocations, stacking faults, and the like. Further, it goes without saying that it does not contain a metal element that affects the device.

Note that "there is substantially no crystal grain boundary" means that even if the crystal grain boundary exists, it is electrically inactive. Such electrically inactive grain boundaries include {111} twin grain boundaries, {111} stacking faults,
{221} twin grain boundaries and {221} Twist twin grain boundaries have been reported (R.Simokawa and Y.Hayashi: Jpn.J.App.
l.Phys. 27 (1987) pp.751 to 758).

The present inventors presume that the crystal grain boundaries contained in the monodomain region are highly likely to be these electrically inactive crystal grain boundaries. That is, it is considered to be an inactive region that does not electrically hinder the movement of carriers even if it appears as grain boundaries.

By the way, the monodomain region, which is the most important concept in the present invention, is formed in the following process.

First, as shown in FIG. 1A, crystal growth proceeds around a region 101 into which a metal element is selectively introduced. At this time, the columnar or acicular crystals that grow crystals grow in a direction substantially parallel to the substrate.

The metal elements that promote crystallization are Fe, Co, Ni, Ru, Rh, Pd, Os, Ir and P.
One or a plurality of types selected from t, Cu, and Au are used, but here Ni (nickel) is taken as an example.

In this way, a lateral growth region 102 is formed. For example, when formed by heat treatment at 600 ° C. for about 6 hours, the lateral growth width (distance X in the figure) is 100.
It becomes about 200 μm.

The lateral growth region 102 thus formed is shown in FIG.
It is divided into eight parts A to H as shown in FIG. This time,
Each of A to H looks like one crystal grain. This is because a defect such as slip occurs in a region where A to H collide with each other and becomes a crystal grain boundary.

FIG. 1B shows a simplified diagram in which a part of the regions A to H is enlarged. As shown in FIG. 1 (B), when viewed microscopically, the lateral growth region is formed by a plurality of columnar or needle-like crystals aggregated, and because these are densely packed, macroscopically FIG. ), It looks like a single crystal grain.

Each of these columnar or needle-like crystals is a region which does not include a grain boundary inside and can be regarded as a substantially single crystal.
That is, it is a mono-domain area.

Further, since each crystal grows while excluding the impurity element such as nickel from the inside, a metal silicide is formed on the crystal surface, and 10 in FIG. 1B is used.
The metal element is segregated in the crystal grain boundaries as shown by 3.

Therefore, in the state shown in FIG. 1B, a plurality of monodomain regions are simply aggregated and the crystallinity is relatively good, but the lateral growth region itself is not a monodomain region.

In order to realize the present invention, it is indispensable to heat the lateral growth region in an atmosphere containing a halogen element. This heat treatment is performed in a temperature range of 700 to 1100 ° C, typically 800 to 1000 ° C.

By this heat treatment, the metal element contained in the lateral growth region is gettered and removed by the action of the halogen element. At this time, the silicon atoms that have been bonded to the metal element are broken, and many dangling bonds are formed, but they recombine with adjacent silicon atoms during the heat treatment.

The broken line 104 indicates a bonding interface in which the crystal grain boundary 103 is once dissociated by the heat treatment and then recombined.

That is, in the individual regions A to H, the columnar or needle-like crystals are recombined with each other with good matching, and FIG.
As shown in (3), there is substantially no grain boundary.

Since this heat treatment is performed at a relatively high temperature of 950 ° C., crystal defects such as dislocations and stacking faults are almost eliminated. Furthermore, the dangling bonds that cannot be supplemented are terminated by the hydrogen and halogen elements contained in the film.

Therefore, the individual regions represented by A to H do not contain crystal grain boundaries or impurity elements such as nickel inside,
At the same time, there are almost no crystal defects. That is, it becomes a monodomain region in which the crystallinity is remarkably improved.

Further, the monodomain region of the present invention is characterized in that the film contains hydrogen and halogen elements at a concentration of 5 atomic% or less. This is because there is an unpaired bond terminated by hydrogen or a halogen element as described above.

One of the structures of the present invention is to form an active layer of a semiconductor device represented by a thin film transistor by utilizing only the above-mentioned monodomain region.

FIG. 7 shows active layers arranged in a matrix on a substrate 701 having an insulating surface for manufacturing an active matrix type liquid crystal display device.

The region indicated by the broken line 702 is the place where the region for selectively introducing nickel exists. Reference numeral 703 is a place where a crystal grain boundary formed by the lateral growth regions hitting each other exists. Since it cannot be confirmed after the active layer is formed, it is shown by a dotted line.

As shown in FIG. 7, the active layer 704 of the thin film transistor is formed in a matrix so as not to include a nickel introduction region and a crystal grain boundary.

FIG. 7 is a view seen locally, but the base 70
The same is true for all active layers formed on 1. That is, the active layers of millions of thin film transistors are formed by using only the monodomain regions that do not include grain boundaries.

The structure of the present invention as described above will be described in detail with reference to the following embodiments.

[0043]

【Example】

[Embodiment 1] In this embodiment, a crystalline silicon film is taken as an example of a semiconductor thin film formed on a substrate having an insulating surface, and a means for further enhancing the crystallinity of a lateral growth region composed of the crystalline silicon film is provided. The means for applying the mono domain region will be described. FIG. 2 is used to explain this process.

The crystallization means used in the present embodiment selectively introduces nickel, which is a metal element that promotes crystallization, into the amorphous silicon film to grow crystals in a direction substantially parallel to the substrate. To obtain a crystalline silicon film. This technique is described in JP-A-7-321339, as mentioned above.

First, a substrate 201 having an insulating surface is prepared. In this embodiment, a silicon oxide film 202 is formed as a base film on a quartz substrate to a thickness of 3000 Å. This silicon oxide film 202 is formed by a sputtering method using an artificial quartz target (as a reference material, a component table of the artificial quartz target is shown in FIG. 15).

When the amorphous silicon film is crystallized later,
The present inventors have found that the denser the base film, the better the crystallinity of the obtained crystalline silicon film. Therefore, in this embodiment, the silicon oxide film 202 is formed by the sputtering method using the artificial quartz target.

The surface of the silicon oxide film 202 is extremely flat and smooth. For example, the height of the unevenness is 30 Å or less, the width of the unevenness is 100 Å or more, and the AF
Even when observed with M, the level becomes difficult to recognize as unevenness.

Next, the amorphous silicon film 203 is coated with 100 to 750 Å.
Plasma CVD to a thickness (preferably 150 to 450 Å)
Method, sputtering method or low pressure thermal CVD method. When the low pressure thermal CVD method is used, disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ) or the like may be used as the film forming gas.

A semiconductor device having a low off-current is manufactured when the crystalline silicon film obtained by subsequent crystallization is used as the active layer of the semiconductor device by setting the film thickness of the amorphous silicon film 203 to the above-mentioned film thickness. can do.

The amorphous silicon film formed by the low pressure thermal CVD method has a small natural nucleus generation rate during the subsequent crystallization. This is desirable in order to increase the lateral growth width, since the rate at which individual crystals interfere with each other (collision stops growth) is reduced.

After forming the amorphous silicon film 203, UV light is irradiated in an oxygen atmosphere to form an extremely thin oxide film (not shown) on the surface of the amorphous silicon film 203. This oxide film is for improving the wettability of the solution in the solution applying step when nickel is introduced later. (Fig. 2 (A))

Then, a silicon oxide film 204 having a thickness of 500 to 1200 Å is formed by a sputtering method using a quartz target, and only the region into which nickel is introduced is selectively removed by etching. That is, the silicon oxide film 204 functions as a mask for selectively introducing nickel into the amorphous silicon film 203.

The region 205 exposed by the silicon oxide film 204 is formed in a slit shape having a longitudinal direction perpendicular to the paper surface. (FIG. 2 (B))

Next, a nickel acetate solution containing nickel at a predetermined concentration is dropped to form a water film 206.
(Fig. 2 (C))

Considering residual impurities in the subsequent heating step, it is preferable to use a nickel nitrate salt solution as the nickel salt solution. This is because the nickel acetate salt solution can be used, but the nickel acetate salt solution contains carbon, which may cause carbonization in the subsequent heating step and remain in the film.

In the state of FIG. 2C, spin coating is performed using a spinner, and a nickel element is held in contact with the region 205 on the amorphous silicon film 203 via an oxide film (not shown). To do.

Then, at 450 ° C. in an inert atmosphere,
After dehydrogenating for about 1 hour, 500 ~ 700 ℃,
Typically, heat treatment is performed at a temperature of 550 to 600 ° C. for 4 to 8 hours to crystallize the amorphous silicon film 203 (first).
Heat treatment). Thus, the crystalline silicon film 207 is obtained. (Fig. 2 (D))

In the region indicated by 205, nickel is diffused into the amorphous silicon film 203 through the oxide film (not shown) from the state of being held in contact with the amorphous silicon film 203 through the oxide film (not shown). It functions as a catalyst for promoting crystallization. Specifically, nickel and silicon react with each other to form a silicide, which serves as a nucleus to promote crystallization.

At this time, in the crystal growth, columnar or acicular crystals proceed in a direction substantially parallel to the substrate. In the case of the present embodiment, the region indicated by 205 has a slit shape having a longitudinal direction from the front direction to the back direction in the drawing, so that the crystal growth proceeds substantially along one direction as indicated by an arrow 208. To do. At this time, the crystal growth can be performed over several hundred μm.

At this time, if natural nucleation occurs due to the heat treatment, columnar or needle-like crystals that have grown crystals interfere with each other and hinder their growth. That is, the growth width of the lateral growth region becomes short, which is not preferable. Therefore,
It is desirable to set the conditions such that the spontaneous nucleation is small and only the introduced nickel becomes the nuclei.

The nickel concentration introduced at this time can be easily controlled by adjusting the concentration of the nickel salt solution in the solution coating step.

The lateral growth region as described above is not affected by other crystals so much because the crystal growth directions are aligned.
Therefore, this lateral growth region appears macroscopically as large crystal grains (grains) of several hundred μm or more.

However, microscopically, the columnar or needle-like crystals are only densely packed, and although the individual crystals are monodomains, the region having relatively excellent crystallinity is generally present. It's just forming. That is, it cannot be regarded as a monodomain region.

Next, after the heat treatment for crystallization is completed, the silicon oxide film 204 which serves as a mask for selectively introducing nickel is removed. This step is easily performed with buffered hydrofluoric acid or the like.

Next, the crystalline silicon film 207 obtained in the above step is subjected to a heat treatment at a higher temperature (second heat treatment). The temperature range of heat treatment is 700 to 1100
℃, typically 800 ~ 1000 ℃, processing time is 1
-24 hours, typically 6-12 hours. The processing atmosphere is an atmosphere containing a halogen element.

In this embodiment, the amount is 3% with respect to the oxygen atmosphere.
The heat treatment is performed at 950 ° C. for 6 hours in the atmosphere containing HCl at the concentration (volume concentration). Introducing nitrogen into the atmosphere to slow down the oxide film formation rate is effective for obtaining a sufficient gettering effect.

In this embodiment, the halogen element is C
Although an example in which HCl gas is selected and HCl gas is used as the introduction method has been shown, HF, NF ₃ , H
One or more selected from Br, Cl ₂ , F ₂ and Br ₂ can be used. In general, a hydride or an organic substance (hydrocarbon) of a halogen can also be used.

In this step, nickel in the crystalline silicon film is gettered by the action of chlorine, and the thermal oxide film 2
It is removed by being taken in by 09 or released into the atmosphere. Therefore, nickel inside the crystalline silicon film 207 is removed, and the crystalline silicon film 210 from which nickel is removed is obtained. (FIG. 2 (E))

The nickel removed in the gettering step is crystal grain boundary (103 in FIG. 1B) during crystallization.
(Shown by) is segregated by being extruded into. That is, it is considered that nickel silicide was present at the crystal grain boundaries.

Nickel existing as silicide is released as nickel chloride, and a large number of dangling bonds of silicon, which has been disconnected from nickel, exist at the crystal grain boundaries.

However, since the above process is performed at a relatively high temperature of 950 ° C., the dangling bonds formed are recombined between silicon. Further, the dangling bonds that cannot be supplemented are terminated by hydrogen and halogen elements contained in the crystalline silicon film 310.

Therefore, the crystal grain boundaries are bonded with good conformity by the bonding of the silicons, and the crystal grain boundaries do not substantially exist. That is, it becomes possible to make the lateral growth region itself a mono-domain region.

Furthermore, since crystal defects such as dislocations and stacking faults that are internal to the needle-shaped or columnar crystal are almost eliminated, the crystallinity of the originally columnar or needle-shaped crystal is remarkably improved. Becomes

After the above steps are completed, the crystalline silicon film 310
It is clear from the analysis by SIMS (secondary ion analysis) that the nickel concentration in the steel has decreased from a few thousandth before the treatment to a fewth or less.

After the gettering of nickel is completed, the thermal oxide film 209 which has become the gettering site is removed.
This prevents nickel from diffusing into the crystalline silicon film 210 again. (Fig. 2 (F))

Through the above process, a crystalline silicon film 211 having a reduced nickel concentration as shown in FIG. 2F can be obtained. This crystalline silicon film 211 has a region as shown by 208 where the crystal is grown in a direction substantially parallel to the substrate.

In this region, the heat treatment in the halogen atmosphere is such that nickel does not hinder the manufacture of semiconductor devices (1
× 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³
Hereinafter, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less) is sufficiently removed, and the crystallinity is remarkably improved, and the monodomain region has a crystallinity comparable to that of a single crystal.

The surface roughness of the monodomain region is ± 30Å or less (preferably ± 20Å or less).
It is considered that this is because the surface of the silicon film is suppressed by the silicon oxide film 204 during the crystal growth of the crystalline silicon film.
This means that an active layer having an extremely flat surface can be obtained by utilizing the monodomain region.

[Embodiment 2] This embodiment shows an example in which an active layer of a thin film transistor is formed by using the monodomain region obtained in the process shown in Embodiment 1. Although the top gate type is taken as an example in the present embodiment, it can be easily applied to the bottom gate type by using a gate electrode having high heat resistance.

First, as shown in FIG. 3A, a semiconductor thin film including a monodomain region is formed according to the process shown in the first embodiment, and an active layer 303 including only the monodomain region is formed by patterning. .. Incidentally, 301 is a quartz substrate as described in the first embodiment, and 302 is a silicon oxide film.

Next, a silicon oxide film 304 functioning as a gate insulating film is formed to a thickness of 1500Å by the plasma CVD method. It may be a silicon oxynitride film or a silicon nitride film.

Next, an aluminum film 305 for forming a gate electrode is formed to a thickness of 5000Å by a sputtering method. 0.2% scandium is contained in this aluminum film.
% By weight. In addition to aluminum, other metals such as tantalum and molybdenum may be used. Thus, the state shown in FIG. 3A is obtained.

After the aluminum film 305 is formed, a 100 Å-thick anodic oxide film (not shown) is formed on the surface thereof. This anodic oxide film is formed by using an ethylene glycol solution containing 3% tartaric acid neutralized with aqueous ammonia as an electrolytic solution. That is, in this electrolytic solution, anodization is performed using the aluminum film 305 as an anode and platinum as a cathode.

The anodic oxide film formed in this step has a dense film quality and functions to improve the adhesion to the resist mask formed later.

Next, the aluminum film 305 is patterned to form an island-shaped aluminum film pattern 306 which will be the base of the gate electrode. The resist mask (not shown) used at this time is left as it is. (Fig. 3
(B))

After obtaining the state shown in FIG. 3B, anodic oxidation is performed again using the aluminum film pattern 306 as an anode. Here, a 3% oxalic acid aqueous solution is used as the electrolytic solution. In this anodizing step, anodization proceeds only on the side surface of the aluminum pattern 306 due to the presence of a resist mask (not shown). Therefore,
An anodic oxide film is formed as indicated by 307 in FIG.

Further, the anodic oxide film 30 formed in this step
No. 7 has a porous shape, and its growth distance can be increased up to several μm.

The thickness of the porous anodic oxide film 307 is set to 7,000 Å. The film thickness of the anodic oxide film 307 can be controlled by the anodic oxidation time.

Porous anodic oxide film 3 shown in FIG.
After forming 07, the resist mask not shown is removed. Then, by performing anodic oxidation again, a dense anodic oxide film 308 is formed. This anodic oxidation process is performed under the same conditions as those for forming the dense anodic oxide film described above.

However, the film thickness to be formed is 800 Å.
In this step, since the electrolytic solution enters the inside of the porous anodic oxide film 307, the anodic oxide film 308 is formed as shown in FIG.

If the thickness of this anodic oxide film is increased to 1500 Å or more, the offset gate region can be formed in the subsequent impurity ion implantation step.

This dense anodic oxide film 308 functions to suppress the generation of hillocks on the surface of the gate electrode 309 in a later step.

After forming the dense anodic oxide film 308,
In this state, impurity ions are implanted to form the source / drain regions. Here, P ions are implanted in order to manufacture an N-channel thin film transistor.

In this step, the source region 310 and the drain region 311 to which impurities are added at a high concentration are formed. (FIG. 3 (C))

Next, using a mixed acid obtained by mixing acetic acid, phosphoric acid and nitric acid, the porous anodic oxide film 307 is selectively removed, and then P ions are implanted again. This ion implantation is performed with a lower dose amount than when forming the source / drain regions.

As a result, low-concentration impurity regions 312 and 313 each having a lower impurity concentration than the source region 310 and the drain region 311 are formed. Then, the region 314 is formed as a channel forming region in a self-aligning manner. (Fig. 3
(D))

After the above impurity ion implantation step, laser light, infrared light, or ultraviolet light is irradiated to anneal the region into which the ions have been implanted.

In this way, the source region 310, the low concentration impurity region 312, the channel forming region 314, the low concentration impurity region 313, and the drain region 311 are formed. Here, the low-concentration impurity region 313 is a region usually called LDD (lightly doped drain region).

Here, the plasma hydrogenation treatment is performed in the range of 300-35.
It is effective to perform the treatment in the temperature range of 0 ° C. for 0.5 to 1 hour.
By this step, 5 atomic% or less (1 ×
10 ²¹ atoms / cm ³ or less), preferably 1 × 10 ¹⁵ to 1 ×
Hydrogen of 10 ²¹ atoms / cm ³ or less is added.

Since this hydrogen is active, it can be removed by neutralizing the dangling bonds of silicon in the active layer 303 or the level at the interface of the active layer / gate insulating film.

After the state shown in FIG. 3D is obtained in this way, an interlayer insulating film 315 is next formed. Interlayer insulating film 315
Is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a resin film, or a stacked film of these films. It is preferable to use a silicon nitride film because hydrogen added in the previous step can be prevented from being released again to the outside of the device.

Then, contact holes are formed to form a source electrode 316 and a drain electrode 317. Pixel TFT in active matrix type liquid crystal display device
However, in the case of the circuit TFT used in the peripheral drive circuit, the extraction electrode from the gate electrode 309 also needs to be formed at the same time.

Further, heat treatment is performed in a hydrogen atmosphere at 350 ° C. to hydrogenate the entire element, thereby completing the thin film transistor shown in FIG.

Since the thin film transistor formed in this manner has the active layer composed of the monodomain region, it exhibits a good field effect mobility that can cope with high-speed operation. In addition, since there is no segregation of crystal grain boundaries and nickel compounds in the channel region and the drain junction, a thin film transistor with excellent reliability can be manufactured.

[Embodiment 3] In this embodiment, the effect of the thermal oxidation step in the atmosphere containing a halogen element, which was performed when forming the monodomain region as described in Embodiment 1, will be described.

FIG. 4 shows the relationship between the vapor pressure and the temperature of NiCl ₂ (nickel chloride) which is a compound of chlorine and nickel.

Since nickel chloride is a sublimation substance as shown in FIG. 4, when nickel in the crystalline silicon film is gettered by chlorine, it immediately becomes volatile. As a result, the produced nickel chloride compound diffuses into the air or is taken into the thermal oxide film and escapes to the outside of the crystalline silicon film. In this way, nickel can be removed from the crystalline silicon film.

In this example, the electrical characteristics of the thin film transistor using the present invention and the electrical characteristics of the thin film transistor not using the present invention are compared. The electrical characteristics referred to here are Id-Vg curves (Id-V) in which the horizontal axis represents the gate voltage (Vg) and the vertical axis represents the drain voltage (Id).
g characteristic).

In FIG. 5, reference numeral 501 shows the electric characteristics of the thin film transistor utilizing the present invention, and 502 shows the electric characteristics of the thin film transistor not utilizing the present invention.
Specifically, reference numeral 502 is an electrical characteristic of a thin film transistor manufactured by a process in which heat treatment in an atmosphere containing a halogen element and subsequent nitrogen annealing are removed from the process of Example 1.

Comparing the characteristics of both transistors, it can be confirmed that the thin film transistor according to the present invention flows an on-current that is larger by about 2 to 4 orders of magnitude even at the same gate voltage. Note that the on-state current refers to a drain current flowing when the thin film transistor is in an on state (gate voltage range of 0 to 5 V in FIG. 5).

It can also be confirmed that the thin film transistor according to the present invention has a better subthreshold characteristic. The subthreshold characteristic is a parameter indicating the steepness of the switching operation of the thin film transistor, and it can be said that the steeper the rise of the Id-Vg curve when the thin film transistor switches from the off state to the on state, the better the subthreshold characteristic.

While the subthreshold characteristic without using the present invention is around 350 mV / decade, the subthreshold characteristic with using the present invention is 100 mV / decade.
It is around decades. It can be said that the smaller this value is, the better the switching performance is. The field effect mobility, which is a measure of the operating speed of a transistor, is 80 to 100 cm ² / Vs when the present invention is not used, and 180 to 200 cm ² / Vs when the present invention is used. It can be said that the larger this value, the faster the operating speed of the transistor.

As described above, the effect of the present invention is clear, and it is experimentally clear that the use of the present invention significantly improves the electric characteristics of the thin film transistor.

[Embodiment 4] In this embodiment, the gettering effect of a metal element by chlorine will be described based on experimental data. The sample for which the experimental data was obtained was formed according to Example 1, and had the structure in the state of FIG.

FIG. 6 shows the results of measuring the chlorine concentration distribution in the cross-sectional direction of the crystalline silicon film obtained by using nickel. This measured value is obtained by SIMS (secondary ion mass spectrometry).

The measurement data in the vicinity of the surface is not significant because it is affected by surface irregularities and adsorbed substances. Further, for the same reason, some error is included in the data near the interface.

As is clear from FIG. 6, chlorine is concentrated near the interface between the crystalline silicon film and the thermal oxide film. It is presumed that this is because chlorine adsorbed on the surface of the crystalline silicon film at the time of starting the heat treatment was taken into the thermal oxide film while gettering nickel.

Moreover, since it is considered that many dangling bonds, so-called dangling bonds, existed on the surface of the crystalline silicon film before the thermal oxidation formation, it was confirmed that these dangling bonds were terminated with chlorine. It seems to suggest.

Therefore, when a semiconductor device is constructed, it is considered that chlorine exists on the surface of the active layer (more accurately, near the interface between the active layer and the gate insulating film) with a high concentration distribution.

[Embodiment 5] This embodiment is an example of forming a CMOS structure with the TFT shown in Embodiment 2. FIG.
~ Fig. 10 shows a manufacturing process of this example. Note that the crystalline silicon film formed according to the present invention has a wide range of applications, and the CMO
The method of forming the S structure is not limited to this embodiment.

First, according to the structure shown in Example 1, a silicon oxynitride film 802 is formed on a quartz substrate 801, and a crystalline silicon film having a monodomain region is obtained thereon. Then, by patterning it, the active layers 803 and P of the N-channel TFT composed of only the mono domain region are formed.
An active layer 804 of the channel type TFT is obtained.

After forming the active layers 803 and 804, the silicon oxide film 805 functioning as a gate insulating film is plasma C
The film is formed by the VD method. The thickness is 500 to 2000Å, typically 1000 to 1500Å. Further, as the gate insulating film, another insulating film such as a silicon oxynitride film or a silicon nitride film may be used.

Thus, the state shown in FIG. 8A is obtained. Here, an example in which a pair of N-channel thin film transistors and P-channel thin film transistors is formed is shown for simplicity of description. Generally, an N-channel type thin film transistor and a P-channel type thin film transistor are formed in units of several hundreds or more on the same glass substrate.

When the state shown in FIG.
As shown in (B), an aluminum film 806 which will later form a gate electrode is formed.

This aluminum film contains scandium in an amount of 0.2 wt% in order to suppress the generation of hillocks and whiskers. The aluminum film is formed by a sputtering method or an electron beam evaporation method.

Hillocks and whiskers are spine-like or needle-like protrusions caused by abnormal growth of aluminum. The presence of hillocks or whiskers causes short circuits or crosstalk between adjacent wirings or between wirings separated by an upper limit.

As the material other than the aluminum film, anodizable metal such as tantalum can be used.

After forming the aluminum film 806, anodization is performed in the electrolytic solution using the aluminum film 806 as an anode to form a thin and dense anodic oxide film 807.

Here, an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia is used as an electrolytic solution. By using this anodizing method, an anodized film having a dense film quality can be obtained. The film thickness can be controlled by the applied voltage.

Here, the thickness of the anodic oxide film 807 is set to 100.
Å The anodic oxide film 807 has a role of improving the adhesion with a resist mask formed later. In this way, the state shown in FIG. 8B is obtained.

Next, resist masks 808 and 809 are formed. Then, using the resist masks 808 and 809, the aluminum film 806 and the anodic oxide film 80 on the surface thereof are formed.
7 is patterned. In this way, the state shown in FIG. 8C is obtained.

Next, using 3% oxalic acid aqueous solution as an electrolytic solution, anodic oxidation is performed with the patterns 810 and 811 made of the aluminum film remaining in this solution as anodes.

In this anodic oxidation process, the anodic oxidation selectively progresses on the side surfaces of the aluminum films 810 and 811 where they remain. This is the aluminum film 810 and 8
11. A dense anodic oxide film and a resist mask 808 on the upper surface of 11.
And 809 remain.

In this anodic oxidation, the anodic oxide films 812 and 81 having a porous (porous) film quality.
3 is formed. Also, this porous anodic oxide film 81
2,813 can be grown up to about several μm.

In the present embodiment, this anodic oxidation progress distance,
That is, the film thickness is 7,000 Å. The length of the low-concentration impurity region will be determined later by the progress distance of this anodic oxidation. Empirically, the growth distance of this porous anodic oxide film is 6000Å
It is desirable to set it to ~ 8000Å. Thus, FIG.
The state shown in (D) is obtained.

In this state, the gate electrodes 81 and 82 are defined. After obtaining the state shown in FIG. 8D, the resist masks 808 and 809 are removed.

Next, anodic oxidation is performed again using an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia as an electrolytic solution. In this step, the electrolytic solution penetrates into the porous anodic oxide films 812 and 813. As a result, dense anodic oxide films 814 and 815 in FIG. 8E are formed.

The thickness of the dense anodic oxide films 814 and 815 is set to 500 to 4000 Å. The film thickness is controlled by the voltage application time. The remaining portion of the dense anodic oxide film 807 formed previously is integrated with the anodic oxide films 814 and 815.

Next, in the state shown in FIG. 8E, the entire surface is doped with P (phosphorus) ions as an impurity imparting N type.

This doping is 0.2-5 × 10 ¹⁵ / c
The dose is as high as m ² , preferably 1 to 2 × 10 ¹⁵ / cm ² . A plasma doping method or an ion doping method is used as the doping method.

As a result of the step shown in FIG. 8 (E), regions 816, 817, 818 in which P ions are implanted at a high concentration,
819 is formed.

Next, the porous anodic oxide films 812 and 813 are removed using aluminum mixed acid. At this time, the anodic oxide film 8
The active layer regions located immediately below the layers 12 and 813 are substantially intrinsic because they are not ion-implanted.

Next, the resist mask 8 is formed so as to cover the element forming the P channel type thin film transistor on the right side.
Form 20. Thus, the state shown in FIG. 9A is obtained.

When the state shown in FIG.
As shown in (B), P ions are implanted again. This P
The dose of ion implantation is 0.1 to 5 × 10 ¹⁴ / cm 3.
² , preferably a low value of 0.3 to 1 × 10 ¹⁴ / cm ² .

That is, P performed in the step shown in FIG.
The dose of the ion implantation is set lower than the dose performed in the step shown in FIG.

As a result of this step, the regions 822 and 824 become lightly doped low concentration impurity regions. Also, 8
The regions 21 and 825 are high-concentration impurity regions in which P ions are implanted at a higher concentration.

In this step, the region 821 becomes the source region of the N-channel type thin film transistor. Then, 822 and 824 become low concentration impurity regions, and 825 becomes a drain region. Further, a region indicated by 823 is a substantially intrinsic channel forming region. The region indicated by 824 is a region generally called an LDD (lightly doped drain) region.

Although not shown in particular, the anodic oxide film 814 is not shown.
The region where the ion implantation is blocked by the channel formation region 823
And the low-concentration impurity regions 822 and 824.
This region is called an offset gate region and has a distance corresponding to the film thickness of the anodic oxide film 814.

Although the offset gate region is not ion-implanted and is substantially intrinsic, it does not form a channel because the gate voltage is not applied and functions as a resistance component that relaxes the electric field strength and suppresses deterioration.

However, the distance (offset gate width)
Is short, it does not function as an effective offset gate region. Also, there is no clear boundary as to how far away it will work effectively.

Next, the resist mask 820 is removed,
As shown in FIG. 9C, a resist mask 826 which covers the left N-channel thin film transistor is formed.

Next, in the state shown in FIG. 9C, B (boron) ions are implanted as impurities imparting P-type. Here, the dose amount of B ions is 0.2 to 10 × 10.
¹⁵ / cm ² , preferably about 1 to 2 × 10 ¹⁵ / cm ² . This dose amount can be approximately the same as the dose amount in the step shown in FIG.

827 and 831 formed by this process
The region indicated by contains an impurity imparting N-type and P-type, but substantially has only a function as a pad (hereinafter, referred to as a contact pad) for making contact with the extraction electrode. That is, unlike the N-channel thin film transistor on the left side, the regions 827 and 831 are clearly distinguished from the source / drain regions.

The present inventors defined the source region as a region indicated by 828 and the drain region as a region indicated by 830 for the P-channel type thin film transistor.

These regions 828 and 830 are formed by implanting only B ions into the substantially intrinsic region. Therefore, since other ions do not coexist, the impurity concentration can be easily controlled, and a PI junction with good compatibility can be realized. Further, the disorder of crystallinity due to ion implantation can be relatively small.

Although the offset gate region can be formed using the anodic oxide film 815, empirically, the P-channel type thin film transistor hardly deteriorates. Therefore, it is not necessary to provide the offset gate region.

Thus, the source region 828 and the drain region 830 of the P-channel type thin film transistor are formed. Further, the region 829 becomes a channel forming region without any impurities being implanted. Then, as described above, 827, 8
31 is a source region 828 and a drain region 830, respectively.
It becomes a contact pad for taking out a current from.

Next, after the step shown in FIG. 9C is completed, the resist mask 826 is removed to obtain the state shown in FIG. 9D. In this state, laser light irradiation is performed to activate the implanted impurities and anneal the regions where the impurity ions are implanted.

At this time, a region shown by a pair of source / drain regions 821 and 825 of the N-channel type thin film transistor and a region shown by a pair of source / drain regions 828 and 830 of the P-channel type thin film transistor. Irradiation with laser light can be performed in a state in which the difference in crystallinity between and is not so large.

The difference in crystallinity is not so large because the source / drain regions 828 and 830 of the P-channel type thin film transistor are not greatly damaged during the ion implantation in the step shown in FIG. 9C. Is.

Therefore, when laser light irradiation is performed in the state shown in FIG. 9D to anneal the source / drain regions of the two thin film transistors, the difference in annealing effect can be corrected. That is, it is possible to correct the difference in the characteristics of the obtained N-type and P-channel type thin film transistors.

After obtaining the state shown in FIG.
As shown in (A), an interlayer insulating film 832 is formed to a thickness of 4000Å. The interlayer insulating film 832 may be any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, and may have a multi-layer structure. These silicide films are formed by plasma CVD.
Method or thermal CVD method may be used.

Next, contact holes are formed to form a source electrode 833 and a drain electrode 834 of an N-channel type thin film transistor (NTFT). At the same time, the source electrode 8 of the P-channel type thin film transistor (PTFT)
35 and the drain electrode 836 are formed.

By patterning so that the drain electrode 834 of the N-channel thin film transistor and the drain electrode 836 of the P-channel thin film transistor are connected to each other, and the gate electrodes of two TFTs are connected to each other, a CMOS structure is realized. To be done.

For example, the CMOS type thin film circuit as shown in this embodiment can be used for an active matrix type liquid crystal display device or an active matrix type EL display device.

Note that FIG. 8 (E), FIG. 9 (B), and FIG.
In the step of implanting impurity ions shown in (C), it is important that the active layer is covered with the silicon oxide film 805 forming the gate insulating film.

By implanting impurity ions in such a state, it is possible to suppress the surface of the active layer from being roughened or contaminated. This greatly contributes to improving the yield and the reliability of the obtained device.

[Embodiment 6] This embodiment shows an example in which the crystalline silicon film shown in Embodiment 1 is formed on a silicon wafer. In this case, it is necessary to provide an insulating layer on the surface of the silicon wafer, but usually a thermal oxide film is often used.

The temperature range of the heat treatment is generally 700 to 1300 ° C., and the treatment time varies depending on the desired oxide film thickness.

Further, thermal oxidation of a silicon wafer is usually O
₂ , O ₂ -H ₂ O, H ₂ O, O ₂ -H ₂ combustion or the like. Further, oxidation in an atmosphere to which a halogen element such as HCl or Cl ₂ is added is also widely used.

The silicon wafer is one of the essential substrates for semiconductor devices such as ICs, and techniques for forming various semiconductor elements on the wafer have been created.

According to this embodiment, a crystalline silicon film having crystallinity comparable to that of a single crystal can be combined with the conventional technique using a silicon wafer to further expand the range of application of the crystalline silicon film. .

[Embodiment 7] This embodiment shows an example of Embodiment 5 in which a TFT using a crystalline silicon film according to the present invention is formed on an IC formed on a silicon wafer. The outline of the manufacturing process will be described with reference to FIG.

FIG. 11A shows a MOS-FET formed on a silicon wafer by a normal process. Reference numeral 11 indicates a silicon substrate, and reference numerals 12 and 13 indicate insulating films for separating the elements from each other. Generally, a thermal oxide film is used.

Further, 14 is a source region and 15 is a drain region, which are formed through a diffusion process after implanting impurity ions imparting one conductivity type into the silicon substrate 11.
If the silicon substrate 11 is P-type, an impurity (phosphorus) imparting N-type is implanted, and if the silicon substrate 11 is N-type, an impurity (boron) imparting P-type is implanted.

The region indicated by 16 is a channel forming region. A part of the thermal oxide film formed in the diffusion process after ion implantation is left on the silicon surface in this region by controlling the film thickness, and functions as a gate insulating film. Reference numeral 17 is a gate electrode made of a polycrystalline silicon film having one conductivity type.

The gate electrode 17 is an insulating film 1 such as a silicon oxide film.
It is covered with 8 and is not electrically short-circuited with the source electrode 19 and the drain electrode 20. (FIG. 11A)

When the state of FIG. 11A is obtained, the interlayer insulating film 21 is formed. A silicon oxide film, a silicon nitride film, or the like is used as this interlayer insulating film. After the interlayer insulating film 21 is formed, a contact hole is formed and a lead wire 22 from the drain electrode is formed. (Fig. 11 (B))

After obtaining the state shown in FIG. 11B, the exposed surface is flattened by polishing by CMP (chemical mechanical polishing) technique or the like. By this step, the interlayer insulating film 21 is flattened, and the protruding portion of the take-out wiring 22 is eliminated.

In FIG. 11C, 23 is a flattened interlayer insulating film, and 24 is its flat surface. In addition, reference numeral 25 is a lead-out wiring having no convex portion, and a lead-out wiring 26 is formed in connection with the lead-out wiring.

The source electrode 19, the drain electrode 20, and the lead-out wiring 26 must all be made of a material having heat resistance that can withstand up to about 1100 ° C.
This is in consideration of the formation temperature of the active layer formed later.

Next, the interlayer insulating film 27 is formed. The present invention can be applied on the interlayer insulating film 27. That is, a thin film transistor having an active layer formed by using a monodomain region is formed on the interlayer insulating film 27.

First, the active layer 28 formed of a monodomain region is formed according to the first embodiment. And the gate insulating film 2
9 is formed, and then the gate electrode 30 is formed. And
An impurity imparting one conductivity type is injected into the active layer.

After the impurity implantation is completed, the sidewalls 31 for forming the low-concentration impurity region are formed later.
The sidewall 31 is formed by the following steps.

First, an insulating film (not shown) made of a silicon oxide film or the like is formed so as to cover the gate electrode 30 and have a thickness equal to or larger than that of the gate electrode 30. Next, anisotropic etching is performed by dry etching to remove the formed insulating film, so that the insulating film remains only on the side surface of the gate electrode 30.

Impurity implantation is performed again in this state. Then, the region into which the impurity is implanted a second time becomes the source region and the drain region, and the region shielded by the sidewall becomes the impurity region having a lower concentration than the source region and the drain region. After implanting the impurities, the impurities are activated by heat treatment, laser light irradiation, or the like.

After the active layer is formed as described above, a silicon oxide film or a silicon nitride film is formed as the interlayer insulating film 32, contact holes are formed, and the source electrode 33 and the drain electrode 34 are formed.

As described above, by applying the present invention on an IC as shown in this embodiment, an integrated circuit having a three-dimensional structure as shown in FIG. 11D can be constructed. According to the present invention, since the TFT formed above the IC has a performance comparable to that of the TFT formed on the single crystal, it is possible to realize a higher density integrated circuit than before without impairing the original performance of the IC. You can [Embodiment 8] In this embodiment, an example in which a TFT manufactured by applying the present invention is applied to a DRAM (Dynamic Rondom Access Memory) will be described. FIG. 12 will be used for the description.

The DRAM is a type of memory in which information to be stored is stored in a capacitor as an electric charge. The transfer of charge as information to and from the capacitor is controlled by a TFT connected in series to the capacitor. FIG. 12 shows a circuit of a TFT and a capacitor which constitutes one memory cell of DRAM.
It shows in (A).

When a gate signal is applied by the word line 121, the TFT indicated by 123 becomes conductive.
In this state, the capacitor 124 is charged with electric charge from the bit line 122 side to read information, or the electric charge is taken out from the charged capacitor to read information.

A sectional structure of the DRAM is shown in FIG. Denoted by 125 is a substrate made of a quartz substrate or a silicon substrate. If it is a silicon substrate, the so-called S
An OI structure can be constructed.

A silicon oxide film 126 is formed as a base film on the base 125, and a T film to which the present invention is applied is formed on the silicon oxide film 126.
An FT is created. If the base 125 is a silicon substrate, a thermal oxide film can be used as the base film 126. Further, 127 is an active layer formed of the mono domain region formed according to the first embodiment.

The active layer 127 is covered with the gate insulating film 128, and the gate electrode 129 is formed thereon. Then, after the interlayer insulating film 130 is laminated thereon, the source electrode 131 is formed. Simultaneously with the formation of the source electrode 131, the electrodes indicated by the bit lines 122 and 132 are formed. Further, 133 is a protective film made of an insulating film.

This electrode 132 maintains a fixed potential, and forms a capacitor 124 between itself and the drain region of the active layer located below it. That is, the electric charge accumulated in this capacitor is written into or read from the TFT to have a function as a memory element.

The feature of DRAM is that the number of elements constituting one memory is very small with only TFTs and capacitors.
It is suitable for constructing large-scale memory with high integration density.
In addition, the price is kept low, so it is currently used in the largest amount.

For example, when an SOI structure to which the present invention is applied is formed on a silicon substrate, the junction area is small, so T
The leak current of the FT can be suppressed to a small value. This greatly contributes to the data retention time.

Further, as a feature of the DRAM cell formed on the SOI substrate, since the storage capacitance can be set small, it is possible to operate at a low voltage.

[Embodiment 9] In this embodiment, a TFT manufactured by applying the present invention is used as an SRAM (Static Rondom Access).
Memory) will be described. FIG. 13 will be used for the description.

The SRAM is a memory that uses a bistable circuit such as a flip-flop as a storage element.
The binary information value (0 or 1) is stored corresponding to the two stable states of N-OFF or OFF-ON. This is advantageous in that memory is retained as long as power is supplied.

The memory circuit is composed of N-MOS and C-MOS. The SRAM circuit illustrated in FIG. 13A is a circuit in which a high resistance is used for a passive load element.

Reference numeral 221 indicates a word line, and 2
22 is a bit line. Reference numeral 223 is a load element composed of a high resistance, and an SRAM is composed of two sets of driver transistors as shown by 224 and two sets of access transistors as shown by 225.

A sectional structure of the TFT is shown in FIG.
A silicon oxide film 227 is formed as a base film on a base 226 made of a quartz substrate or a silicon substrate, and a TFT to which the present invention is applied can be formed on the silicon oxide film 227. Reference numeral 228 is an active layer formed of a monodomain region formed according to the first embodiment.

The active layer 228 is covered with the gate insulating film 229, and the gate electrode 230 is formed thereon. Then, after the interlayer insulating film 231 is laminated thereon, the source electrode 232 is formed. At the same time as the formation of the source electrode 232, the bit line 22 and the drain electrode 233 are formed.

An interlayer insulating film 234 is laminated again thereon, and then a polysilicon film 235 is formed as a high resistance load. Reference numeral 236 is a protective film made of an insulating film.

The characteristics of the SRAM configured as described above are that it can operate at high speed, has high reliability, and can be easily incorporated into a system.

[Embodiment 10] The research on the SOI structure as mentioned in Embodiments 7 and 8 has been remarkable in recent years as a breakthrough of low power consumption. In this embodiment, the problem left on the SOI substrate is compared with the present invention.

The above problems are summarized in FIG. As shown in FIG. 14, there are things related to crystallinity such as interface states and fixed charges in the silicon film, and external things such as metal contamination and boron concentration.

In the present invention, the crystalline silicon film is heat-treated in an atmosphere containing a halogen element, so that the silicon film is single-crystallized and the metal element is gettered at the same time.

First, metal contamination is easily removed by the gettering effect. This is due to the action of the halogen element, and as a result, it has a secondary action of increasing the number of dangling bonds of silicon atoms that have broken bonds with nickel.

Next, there is single crystallization due to the annealing effect of the heat treatment. As this effect, factors that adversely affect the crystallinity such as pipe density, interface state, fixed charge, and threading transition can be removed or sufficiently reduced.

The precipitate in FIG. 14 can be removed by a gettering effect of a halogen element if it is a silicide-based substance. Further, in the case of an oxide-based substance, it can be expected that oxygen is desorbed and diffused again by heat treatment and the oxide disappears.

[Embodiment 11] In this embodiment, an active matrix region and a peripheral drive circuit for driving this active matrix region are integrated on the same substrate by using the semiconductor device of Embodiment 2 and the CMOS structure of Embodiment 5. An example is shown below.

One of the substrates constituting the integrated active matrix type liquid crystal display device has the following constitution. That is, in the active matrix area, at least one thin film transistor for switching is arranged in each of the pixels arranged in a matrix, and peripheral circuits for driving the active matrix area are arranged around the active matrix area. There is. All of these circuits are integrated on a single quartz substrate (or silicon substrate).

When the invention disclosed in this specification is used in such a configuration, the active matrix region and the peripheral circuit can be configured by thin film transistors having performance comparable to that of a MOS-FET formed on a single crystal. .

That is, the thin film transistor shown in FIG. 3 constitutes a pixel TFT in the active matrix region, and the CMOS circuit shown in FIGS. 8 to 10 constitutes a peripheral circuit.

Since it is necessary for the thin film transistor arranged in the active matrix region to maintain the charge held in the pixel electrode for a predetermined time, it is desirable to make the off current value as small as possible.

Since the active layer of the thin film transistor according to the present invention is formed in the monodomain region, there is substantially no crystal grain boundary that can serve as a path (current path) through which the off current preferentially flows. Therefore, a thin film transistor with a small off-state current can be provided.

On the other hand, as the peripheral drive circuit, a CMOS circuit is often used. And in order to improve its characteristics, C
It is necessary to make the characteristics of the N-channel type thin film transistor and the P-channel type thin film transistor forming the MOS circuit uniform as much as possible.

For this purpose, the CMOS structure as shown in the fifth embodiment (see FIGS. 8 to 10) is optimum.

In this way, it is possible to obtain an integrated active matrix type liquid crystal display device having a structure having preferable characteristics for each circuit.

[Embodiment 12] In this embodiment, an example in which the step of forming the gate insulating film is different from that in Embodiment 2 will be described.

First, a semiconductor thin film including a monodomain region is formed through the same steps as in Example 1, and then the active layer of the semiconductor device is formed by selectively utilizing only the monodomain region.

Next, 200 to 1500Å so as to cover the active layer.
An insulating film (silicon oxide film in this embodiment) having a thickness of (800 Å in this embodiment) containing silicon as a main component is formed by CVD or PV.
A film is formed by a vapor phase method typified by method D. At this time, the thickness of the silicon oxide film may be determined in consideration of the final withstand voltage. Further, a silicon oxynitride film or a silicon nitride film can be used instead of the silicon oxide film.

After the formation of the silicon oxide film is completed, the third heat treatment is again performed in an atmosphere containing a halogen element.
This heat treatment may be performed under the same conditions as the heat treatment (second heat treatment) in the atmosphere containing the halogen element in the first embodiment.

By the third heat treatment, the metal element such as nickel remaining in the active layer is further reduced, and the crystallinity of the monodomain region is further improved accordingly. Also,
At the interface between the active layer and the silicon oxide film described above, a thermal oxidation reaction proceeds to form a thermal oxide film of about 200 Å. At that time, the final thickness of the active layer is 200 to 300 Å (typically
Setting it to 250 Å) is effective in reducing the off current.

In this example, following the heat treatment in the atmosphere containing the halogen element, the nitrogen atmosphere was changed to
By performing heat treatment at 950 ° C. for about 1 hr, the quality of the thermal oxide film and the insulating film containing silicon as its main component is improved.

Further, as a result of performing the heat treatment in the atmosphere containing the halogen element, the halogen element remains at a high concentration near the interface between the active layer and the gate insulating film. According to SIMS measurement, it exists at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ .

Further, the thermal oxide film formed on the interface between the active layer and the above-mentioned silicon oxide film constitutes a gate insulating film together with the silicon oxide film. At this time, when the thermal oxide film is formed, the defect level at the interface of the active layer and the interstitial silicon atoms are reduced, so that the interface state between the active layer and the gate insulating film becomes very excellent.

Further, as described in Example 1, since the surface of the active layer is extremely flat, the thermal oxidation reaction proceeds uniformly and the thickness of the gate insulating film becomes uniform. This is preferable not only for improving the interface state but also for improving the breakdown voltage of the gate insulating film.

As described above, by carrying out this embodiment, not only the metal elements such as nickel are reduced but also the interface state between the active layer and the gate insulating film is made extremely excellent, and excellent electrical characteristics are obtained. It is possible to realize a semiconductor device having high reliability.

Note that the second heat treatment shown in Embodiment 1 and the third heat treatment shown in this embodiment can be combined at the same time. For that purpose, the crystalline silicon film 207 (the crystalline silicon film before the first heat treatment) in Example 1 is patterned to form an active layer, and the constitution as in this example may be adopted.

[Embodiment 13] This embodiment is an example in which the interface state between the active layer and the gate insulating film is improved under the conditions different from those of the embodiment 12.

First, a semiconductor thin film including a monodomain region is formed through the same steps as in Example 1, and then only the monodomain region is selectively used to form an active layer of a semiconductor device. Then, as in Example 12, a silicon oxide film having a thickness of 200 to 1500 Å is formed by the CVD method or the PVD method.

Under this condition, the temperature is 500 to 700 ° C (typically 640
Heat treatment (~ 650 ℃). This temperature range is a temperature close to the lower limit at which thermal oxidation can be performed. Further, this heat treatment may be performed in an atmosphere containing only oxygen or an atmosphere containing a halogen element. Alternatively, the atmosphere may be a wet atmosphere containing water vapor.

When heat treatment is performed under the conditions of this embodiment,
If it is processed for about 5 to 2 hours, it will be less than several tens of liters (eg
Å) thermal oxide film is formed. Then, the growth of the thermal oxide film is substantially converged to this thickness.

According to the findings of the present inventors, fixed charges and defect levels are formed near the polar interface between the active layer and the gate insulating film (a region of about 10 to 30 Å from the interface toward the active layer side and the gate insulating film side). It is not an exaggeration to say that this region determines the interface state between the active layer and the gate insulating film, since the above concentration occurs.

Therefore, in order to obtain a good interface state between the active layer and the gate insulating film, only 10 to 30 Å of the active layer interface is required.
Area is thermally oxidized (active layer is reduced by 10 to 30Å
It is only necessary to eliminate fixed charges and defect levels near the pole interface by forming a thermal oxide film of ~ 60Å). In other words, it is sufficient to form a thermal oxide film of less than several tens of liters in order to realize a good interface state.

In the thermal oxidation process as in this embodiment, since the processing temperature is low, the load on the device can be reduced and the throughput of the semiconductor device manufacturing process can be improved.

[Embodiment 14] This embodiment shows an example in which a crystalline silicon film (polysilicon film) is used as a gate electrode. FIG. 16 is used for the description.

In FIG. 16A, 1601 is a glass substrate, 1602 is a base film, 1603 is an active layer composed of the monodomain region obtained in the process shown in Example 1, and 1604.
Is a gate insulating film, and 1605 is a gate electrode made of a polysilicon film having one conductivity.

Next, in this state, impurity ions imparting one conductivity type to the active layer 1603 are implanted. Then, the impurity regions 1606, 1 are formed by this ion implantation process.
607 is formed.

After the implantation of impurity ions is completed, a silicon nitride film 1608 is formed to a thickness of 0.5 to 1 μm. The film forming method may be any of a low pressure thermal CVD method, a plasma CVD method and a sputtering method. Further, a silicon oxide film may be used instead of the silicon nitride film.

Thus, the state shown in FIG. 16B is obtained.
After the state of FIG. 16B is obtained, the silicon nitride film 16 is then removed.
08 is etched by the etch back method and left only on the side wall of the gate electrode 1605. The silicon nitride film left in this manner functions as a sidewall 1609.

At this time, the gate insulating film 1604 is removed except for the region where the gate electrode 1605 and the sidewall 1609 serve as a mask, and remains in the state shown in FIG. 16C.

Next, impurity ions are implanted again in the state shown in FIG. At this time, the dose amount is set higher than the dose amount for the ion implantation. At the time of this ion implantation, the region 161 immediately below the sidewall 1609.
No ion implantation is performed on the samples 0 and 1611, so that the concentration of impurity ions does not change. However, the exposed area 16
In 12 and 1613, impurity ions of higher concentration are implanted.

Through the second ion implantation as described above, low concentration impurity regions (LDD regions) 1610 and 1611 having an impurity concentration lower than that of the source region 1612, the drain region 1613 and the source / drain regions are formed. Immediately below the gate electrode 1605 is an undoped region, which becomes a channel formation region 1614.

When the state of FIG. 16C is obtained through the above steps, a titanium film (not shown) having a thickness of 300 Å is formed, and the titanium film and the silicon film are reacted with each other. Then, after the titanium film is removed, heat treatment such as lamp annealing is performed to perform the source region 1612 and the drain region 16
13. Titanium silicides 1615 to 1617 are formed on the exposed surface of the gate electrode 1605. (FIG. 16 (D))

In the above process, a tantalum film, a tungsten film, a molybdenum film or the like can be used instead of the titanium film.

Next, a silicon oxide film is formed as an interlayer insulating film 1618 to a thickness of 5000Å to form a source wiring 1619, a drain wiring 1620, and a gate wiring 1621. Thus, the TFT having the structure shown in FIG. 16D is completed.

The TFT of the structure shown in this embodiment has wiring and T
Since the connection with the FT is made through the titanium silicides 1615 to 1617, good ohmic contact can be realized.

[Embodiment 15] A semiconductor device in this specification refers to all devices that function by using a semiconductor, and is an active matrix electro-optical device having a structure as shown in Embodiment 11. (Liquid crystal display devices, EL display devices, EC display devices, etc.) and applied products incorporating such electro-optical devices are also included in the category.

In this embodiment, the applied product will be described with reference to the drawings. Examples of semiconductor devices utilizing the present invention include TV cameras, head mounted displays, car navigations, projections (front and rear types), video cameras, personal computers and the like. A brief description will be given with reference to FIG.

FIG. 17A shows a mobile computer, which has a main body 2001, a camera section 2002, and an image receiving section 200.
3, an operation switch 2004, and a display device 2005. The present invention is applied to the display device 2005 and an integrated circuit incorporated in the device.

FIG. 17B shows a head mounted display, which is composed of a main body 2101, a display device 2102, and a band portion 2103. Two display devices 2102 having a relatively small size are used.

FIG. 17C shows a car navigation system, which includes a main body 2101, a display device 2102, and operation switches 2.
103 and an antenna 2104. The present invention can be applied to the display device 2102 and an integrated circuit inside the device. The display device 2202 is used as a monitor, but since the main purpose is to display a map, it can be said that the allowable range of resolution is relatively wide.

FIG. 17D shows a mobile phone, which is a main body 23.
01, voice output unit 2302, voice input unit 2303, display device 2304, operation switch 2305, antenna 230
6. The present invention can be applied to the display device 2304 and an integrated circuit inside the device.

FIG. 17E shows a video camera, which is a main body 2401, a display device 2402, a voice input section 2403, operation switches 2404, a battery 2405, and an image receiving section 24.
06. The present invention can be applied to the display device 2402 and an integrated circuit inside the device.

FIG. 17F shows a front projection, which is composed of a main body 2501, a light source 2502, a reflection type display device 2503, an optical system (including a beam splitter and a polarizer) 2504, and a screen 2505.
Since the screen 2505 is a large screen used for presentations such as conferences and conference presentations, the display device 2503 is required to have high resolution.

In addition to the electro-optical device shown in this embodiment, the present invention can be applied to portable information terminal equipment such as rear projection and handy terminal. As described above, the application range of the present invention is extremely wide, and the present invention can be applied to display media in all fields.

[0260]

As an effect of the present invention, it is possible to realize the formation of a monodomain region which can be regarded as a substantially single crystal on a substrate having an insulating surface. That is, it becomes possible to form an active layer of a semiconductor device such as a thin film transistor using a crystalline silicon film having crystallinity comparable to that of a single crystal.

Therefore, it is possible to construct a semiconductor circuit having performance comparable to that of an integrated circuit using a known single crystal wafer.

[Brief description of drawings]

FIG. 1 is a diagram showing characteristics of a lateral growth region.

FIG. 2 is a diagram showing a process for forming a semiconductor thin film having a monodomain region.

3A to 3D are diagrams showing a manufacturing process of a semiconductor device.

FIG. 4 is a diagram showing the relationship between vapor pressure and temperature of nickel chloride.

FIG. 5 is a diagram showing electric characteristics of a thin film transistor.

FIG. 6 is a diagram showing a chlorine concentration distribution in a crystalline silicon film.

FIG. 7 is a diagram showing an active layer formed in a monodomain region.

FIG. 8 is a diagram showing a manufacturing process of a semiconductor device.

9A to 9C are diagrams illustrating a manufacturing process of a semiconductor device.

FIG. 10 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 11 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 12 is a diagram showing a structure of a DRAM.

FIG. 13 is a diagram showing a configuration of SRAM.

FIG. 14 is a diagram showing a problem of an SOI structure.

FIG. 15 is a diagram showing a composition table of an artificial quartz target.

16A to 16D are diagrams illustrating a manufacturing process of a semiconductor device.

FIG. 17 is a diagram for explaining an example of an applied product.

[Explanation of symbols]

 101 Nickel Introduced Region 102 Lateral Growth Region 103 Crystal Grain Boundary 104 Bonding Interface 201 Quartz Substrate or Silicon Substrate 202 Silicon Oxide Film 203 Amorphous Silicon Film 204 Silicon Oxide Film 205 Nickel Introduced Region 206 Water Film Containing Nickel 207 Crystalline Silicon Film 208 Crystal growth direction 209 Thermal oxide film 210 Crystalline silicon film 211 Crystalline silicon film

Continuation of the front page (72) Inventor Kenji Fukunaga 398 Hase, Atsugi, Kanagawa Prefecture Semiconductor Energy Laboratory Co., Ltd.

Claims (32)

[Claims] 1. A semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film has a monodomain region formed by collecting a plurality of columnar or acicular crystals substantially parallel to the substrate. A semiconductor thin film characterized in that 2. The semiconductor thin film according to claim 1, wherein the monodomain region is substantially free of crystal grain boundaries. 3. A semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film has a monodomain region formed by collecting a plurality of columnar or acicular crystals substantially parallel to the substrate. A semiconductor thin film having substantially no crystal grain boundaries in the monodomain region. 4. A semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film has a monodomain region formed by collecting a plurality of columnar or acicular crystals substantially parallel to the substrate. The monodomain region does not substantially have a grain boundary, and the semiconductor thin film forming the monodomain region contains hydrogen and a halogen element at a concentration of 5 atomic% or less, and the halogen element is chlorine. A semiconductor thin film characterized by being an element selected from bromine and fluorine. 5. A step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, a step of selectively forming a silicon oxide film on the amorphous silicon film, A step of holding a metal element that promotes crystallization in the amorphous silicon film; a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by the first heat treatment; A step of removing the silicon film and a second heat treatment in an atmosphere containing a halogen element to form a thermal oxide film containing the halogen element on the amorphous silicon film and / or the crystalline silicon film. At the same time, the semiconductor thin film is manufactured through at least the step of transforming the crystalline silicon film into a monodomain region and the step of removing the thermal oxide film. 6. The semiconductor thin film according to claim 5, wherein the halogen element has a high concentration distribution near the surface of the semiconductor thin film. 7. The semiconductor thin film according to claim 1, wherein the monodomain region has a film thickness of 150 to 450 Å. 8. The semiconductor thin film forming the monodomain region according to claim 1, wherein hydrogen is 1 × 10 ^15.
A semiconductor thin film, which is added at a concentration of 1 × 10 ²¹ atoms / cm ³ . 9. A step of forming an amorphous silicon film by a low pressure thermal CVD method on a substrate having an insulating surface, a step of selectively forming a silicon oxide film on the amorphous silicon film, A step of holding a metal element that promotes crystallization in the amorphous silicon film; a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by the first heat treatment; A step of removing the silicon film and a second heat treatment in an atmosphere containing a halogen element to form a thermal oxide film containing the halogen element on the amorphous silicon film and / or the crystalline silicon film. And a step of removing the thermal oxide film, wherein the crystalline silicon film is transformed into a monodomain region by the second heat treatment. 10. The method for producing a semiconductor thin film according to claim 9, wherein the crystalline silicon film is formed by assembling a plurality of columnar or acicular crystals substantially parallel to the substrate. 11. A quartz substrate having a silicon oxide film formed on a surface thereof by a sputtering method using an artificial quartz target or a silicon substrate having a thermal oxide film formed on a surface thereof is used as a substrate. And a method for manufacturing a semiconductor thin film. 12. The metal element for promoting crystallization according to claim 9, wherein Fe, Co, Ni, Ru, Rh, Pd,
A method of manufacturing a semiconductor thin film, wherein one or more kinds selected from Os, Ir, Pt, Cu, and Au are used. 13. The atmosphere according to claim 9, wherein the halogen-containing atmosphere is an O ₂ atmosphere containing HCl, HF, HBr, and Cl.
_{2. A} method for producing a semiconductor thin film, wherein one or more kinds of gases selected from ₂ , NF ₃ , F ₂ and Br ₂ are added. 14. The heat treatment according to claim 9, wherein the first heat treatment is 5
A method for manufacturing a semiconductor thin film, which is performed in a temperature range of 00 to 700 ° C. and the second heat treatment is performed in a temperature range of 700 ° C. to 1100 ° C. 15. A semiconductor device having an active layer made of a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is formed by assembling a plurality of columnar or needle crystals substantially parallel to the substrate. The semiconductor device according to claim 1, wherein the active layer includes only the monodomain region. 16. The semiconductor device according to claim 15, wherein the active layer has substantially no crystal grain boundaries. 17. A semiconductor device having an active layer made of a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is formed by assembling a plurality of columnar or acicular crystals substantially parallel to the substrate. A semiconductor device having a mono-domain region defined as described above, and substantially no crystal grain boundaries are present in an active layer composed only of the mono-domain region. 18. Low pressure thermal CVD on a substrate having an insulating surface.
A step of forming an amorphous silicon film by a method, a step of selectively forming a silicon oxide film on the amorphous silicon film, and a metal element that promotes crystallization of the amorphous silicon film. In the atmosphere containing a halogen element; a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by a first heat treatment; a step of removing the silicon oxide film; Forming a thermal oxide film containing a halogen element on the amorphous silicon film and the crystalline silicon film by performing a second heat treatment, and at the same time transforming the crystalline silicon film into a monodomain region; And a step of removing the thermal oxide film, wherein the active layer is composed of only the monodomain region. 19. In manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, and the amorphous silicon film. A step of selectively forming a silicon oxide film thereon, a step of holding a metal element that promotes crystallization in the amorphous silicon film, and a step of heating at least part of the amorphous silicon film. A step of transforming into a crystalline silicon film, a step of removing the silicon oxide film, a step of forming an active layer using only the crystalline silicon film, and an insulating film containing silicon as a main component to cover the active layer. A step of forming a film by a vapor phase method and a heat treatment in an atmosphere containing a halogen element to form a thermal oxide film at the interface between the active layer and the insulating film containing silicon as a main component, and From the crystal A step of transforming the active layer into a mono-domain region by gettering and removing a metal element that promotes, and a film quality of the silicon-based insulating film including the thermal oxide film by heat treatment in a nitrogen atmosphere. And a step of improving the semiconductor device. 20. A semiconductor device having an active layer made of a semiconductor thin film formed on a substrate having an insulating surface, wherein the semiconductor thin film is formed by assembling a plurality of columnar or acicular crystals substantially parallel to the substrate. And a halogen element of 5 atomic% or less is contained in the inside of the active layer composed of only the monodomain region. A semiconductor device characterized in that the element is an element selected from chlorine, bromine, and fluorine. 21. The semiconductor device according to claim 18, wherein the halogen element has a high concentration distribution near the surface of the active layer. 22. The semiconductor device according to claim 15, wherein the thickness of the active layer is 150 to 450 Å. 23. The active layer according to claim 15, wherein hydrogen is 1 × 10 ¹⁵ to 1 × 10 ²¹ atoms / cm 3.
A semiconductor device characterized by being added at a concentration of ³ . 24. A semiconductor device having an active layer made of a semiconductor thin film formed above an IC integrated on a silicon substrate, wherein the semiconductor thin film has columnar or acicular crystals substantially parallel to the base. A semiconductor device having a mono-domain region formed by a plurality of aggregates, wherein the active layer constituted only by the mono-domain region has substantially no crystal grain boundaries. 25. The active layer according to claim 24, wherein hydrogen and a halogen element are contained in a concentration of 5 atomic% or less, and the halogen element is an element selected from chlorine, bromine and fluorine. Semiconductor device. 26. In manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, and the amorphous silicon film. A step of selectively forming a silicon oxide film thereon, a step of holding a metal element that promotes crystallization in the amorphous silicon film, and a step of performing a first heat treatment on at least the amorphous silicon film. A step of transforming a part of the amorphous silicon film into a crystalline silicon film; a step of removing the silicon oxide film; and a second heat treatment in an atmosphere containing a halogen element to perform the amorphous silicon film and the crystalline silicon film. At least a step of forming a thermal oxide film containing a halogen element on the film, and a step of removing the thermal oxide film, and converting the crystalline silicon film into a monodomain region by the second heat treatment. Allowed, a method for manufacturing a semiconductor device characterized by forming the active layer by using only the monodomain region. 27. In manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming an amorphous silicon film on a substrate having an insulating surface by a low pressure thermal CVD method, and the amorphous silicon film. A step of selectively forming a silicon oxide film thereon, a step of holding a metal element that promotes crystallization in the amorphous silicon film, and a step of heating at least part of the amorphous silicon film. A step of transforming into a crystalline silicon film; a step of removing the silicon oxide film; a step of forming an active layer using only the crystalline silicon film; A step of forming a film by a vapor phase method, and a heat treatment in an atmosphere containing a halogen element to form a thermal oxide film at the interface between the active layer and the insulating film containing silicon as a main component, and from the active layer. The crystallization And a step of improving the film quality of the insulating film containing silicon as a main component including the thermal oxide film by a heat treatment in a nitrogen atmosphere by gettering and removing the promoting metal element. A method for manufacturing a semiconductor device, characterized in that the active layer is transformed into a monodomain region by heat treatment in an atmosphere containing an element. 28. In Claim 26 or Claim 27,
A method for manufacturing a semiconductor device, wherein the crystalline silicon film is formed by collecting a plurality of columnar or needle-like crystals that are substantially parallel to the substrate. 29. The method according to claim 26 or 27.
A method for manufacturing a semiconductor device, wherein a quartz substrate having a silicon oxide film formed on a surface thereof by a sputtering method using an artificial quartz target or a silicon substrate having a thermal oxide film formed on a surface thereof is used as a substrate. 30. In claim 26 or claim 27,
Metal elements that promote crystallization include Fe, Co, Ni,
A method for manufacturing a semiconductor device, wherein one or more kinds selected from Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used. 31. In Claim 26 or Claim 27,
The atmosphere containing the halogen element is HCl, H in the O ₂ atmosphere.
A method for manufacturing a semiconductor device, wherein one or more gases selected from F, HBr, Cl ₂ , NF ₃ , F ₂ , and Br ₂ are added. 32. The semiconductor according to claim 26, wherein the first heat treatment is performed in a temperature range of 500 to 700 ° C. and the second heat treatment is performed in a temperature range of 700 ° C. to 1100 ° C. Method for manufacturing device.