JPH10125927A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a high-performance electrooptical device by selectively holding a metal element form-assisting the crystallization on an amorphous Si film formed on a substrate, heat-treating the amorphous Si film to modify a part thereof into a crystalline Si film and forming an island-like semiconductor layer with only the crystalline Si film to be an active layer. SOLUTION: A silicon oxide film 104 is formed and only regions into which a crystallization assisting metal element is to be introduced later are selectively etched to form openings through which regions 105 formed like slits are exposed. A nickel nitrate soln. of specified concn. is dripped to form a thin water film 106. After dehydrogenizing in an inert atmosphere, it is heat treated to crystallize an amorphous Si film 103 into a crystalline Si film 107. Gettering is applied to obtain an island-like semiconductor layer 110 not contg. Ni or reduced enough to have no influence on the device characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor device using a semiconductor thin film formed on a substrate having an insulating surface as an active layer. In particular, the present invention relates to a thin film transistor having an active layer formed of a crystalline silicon film.

[0002]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several hundred to several thousand square meters) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

For example, in a liquid crystal display device, a pixel matrix circuit for individually controlling pixel areas arranged in a matrix, a driving circuit for controlling the pixel matrix circuit, and a logic circuit (processor circuit) for processing an external data signal Attempts have been made to apply TFTs to any electric circuit such as a semiconductor device and a memory circuit.

An important part which can be called the heart of such a TFT is a channel forming region and a junction portion which joins the channel forming region and the source / drain region. That is, it can be said that the active layer most affects the performance of the TFT.

[0005] As a semiconductor thin film constituting an active layer of a TFT, a silicon (silicon) film formed by a plasma CVD method or a low pressure thermal CVD method is generally used.

At present, TFTs using an amorphous silicon film (amorphous silicon film) have been put to practical use. However, electric circuits which require higher speed operation performance, such as driving circuits and logic circuits, are required. In addition, a TFT using a crystalline silicon film (polysilicon film) is required.

As a method of forming a crystalline silicon film on a substrate, Japanese Patent Application Laid-Open Nos. Hei 6-232059 and
The technique described in 244103 is known. The technique described in this publication utilizes a metal element (especially nickel) which promotes crystallization of silicon, thereby making it possible to use a metal element of 500 to 60%.
This makes it possible to form a crystalline silicon film having excellent crystallinity by heat treatment at 0 ° C. for about 4 hours.

The technique described in Japanese Patent Application Laid-Open No. Hei 7-321339 is a technique for performing crystal growth substantially parallel to a substrate by applying the above-described technique. It is called the region (or lateral growth region).

The crystalline silicon film formed by such a technique has a feature that it has excellent crystallinity because it has a crystal structure in which columnar or needle-like crystals are gathered in a state where the traveling directions are almost aligned. Therefore, it is known that a TFT having high operation performance can be manufactured by using a crystalline silicon film formed by using the technique described in the above publication as an active layer of the TFT.

However, even if a driving circuit is constructed using such TFTs, the required performance is still not fully satisfied. In particular, it is impossible at present to configure a high-speed logic circuit that requires extremely high-performance electrical characteristics for realizing high-speed operation and high withstand voltage characteristics at the same time using conventional TFTs.

[0011]

As described above, in order to improve the performance of an electro-optical device or the like, it is necessary to realize a TFT having a performance comparable to a MOSFET formed using a single crystal silicon wafer. Not be.

It is an object of the invention disclosed in this specification to provide an extremely high performance thin film semiconductor device which can be a breakthrough for realizing higher performance of an electro-optical device and a method of manufacturing the same. .

[0013]

Means for Solving the Problems In the conventional method, a high-performance TFT as described above could not be obtained because of a crystal grain boundary of a needle-like or columnar crystal (a crystal grain boundary in the present specification). Carriers (electrons or holes) are trapped in the boundary between the needle-like or columnar crystals unless otherwise noted), and the improvement of the field-effect mobility, which is one of the parameters showing the TFT characteristics, has been hindered. It is possible.

For example, there are many dangling bonds and defect (capture) levels of silicon atoms in the crystal grain boundaries. Further, it is known that when a metal element that promotes crystallization is used during crystallization, the metal element segregates at the crystal grain boundary.

Therefore, carriers moving inside the individual needle-like or columnar crystals are easily trapped by dangling bonds or defect levels when approaching or contacting the crystal grain boundaries. It is thought that it behaved as a “malignant grain boundary” that hindered the movement of GaN.

In order to realize the semiconductor device of the present invention, it is indispensable to use a technique for changing the structure of such a "malignant crystal grain boundary" to transform the carrier into a "benign crystal grain boundary". That is, it can be said that it is important to form a crystal grain boundary having a small probability of capturing carriers and having a small possibility of hindering the movement of carriers.

For this purpose, the structure of the invention disclosed in the present specification includes a step of forming an amorphous silicon film on a substrate having an insulating surface when manufacturing a semiconductor device having an active layer formed of a semiconductor thin film; A step of selectively forming a mask insulating film on the amorphous silicon film, a step of selectively holding a metal element for promoting crystallization on the amorphous silicon film, and a first heat treatment Transforming at least a portion of the amorphous silicon film into a crystalline silicon film, removing the mask insulating film, and forming an active layer later only by the crystalline silicon film by patterning A step of forming an island-shaped semiconductor layer and a second heat treatment in an atmosphere containing a halogen element to remove the metal element in the island-shaped semiconductor layer by gettering and remove the metal element from the thermal oxide film. It includes a step of forming an insulating film, at least, the active layer, wherein the substrate substantially parallel acicular or columnar crystals are formed by a plurality sets.

According to another aspect of the present invention, there is provided a semiconductor device having an active layer made of a semiconductor thin film, wherein an amorphous silicon film is formed on a substrate having an insulating surface; A step of selectively forming a mask insulating film on the silicon film; a step of selectively holding a metal element that promotes crystallization to the amorphous silicon film; Transforming at least a part of the crystalline silicon film into a crystalline silicon film, removing the mask insulating film, and forming an island-like semiconductor layer comprising only the crystalline silicon film by patterning as an active layer later A step of performing gettering removal of the metal element in the island-shaped semiconductor layer by performing a second heat treatment in an atmosphere containing a halogen element, and a step of performing the second heat treatment in an atmosphere containing a halogen element. Removing the oxide film; and performing a third heat treatment to form a thermal oxide film functioning as a gate insulating film on the surface of the island-shaped semiconductor layer. And a plurality of needle-like or columnar crystals substantially parallel to each other are formed.

When a crystalline silicon film is formed by the manufacturing method according to the above configuration, a thin film having an appearance as shown in FIG. 9 is obtained. FIG. 9 shows a method of crystallizing an amorphous silicon film disclosed in
FIG. 3 is an enlarged micrograph of a case where the present invention is implemented using the technique described in Japanese Patent No. 1339, in which a lateral growth region 901 having a length of several hundred μm is formed.

The lateral growth region 901 grows in a direction substantially perpendicular to a region (shown by 902) in which a needle-like or columnar crystal is added with a metal element which promotes crystallization, and substantially parallel to each other. Therefore, there is a feature that the crystal directions are aligned. Further, what is indicated by 903 is a macroscopic crystal grain boundary formed by collision of needle-like or columnar crystals extending from the opposite addition region 902 (to be distinguished from a crystal grain boundary between needle-like or columnar crystals). ).

FIG. 10A is a TEM photograph in which the inside of the crystal grain is magnified up to 250,000 times by focusing on the inside of the lateral growth region shown in FIG. FIG. 14B schematically shows the structure of FIG.

That is, although the crystalline silicon film of the present invention macroscopically appears to be composed of a large lateral growth region 901 as shown in FIG. 9, when the lateral growth region 901 is observed microscopically,
As shown in FIG. 10B, the crystal structure has a structure in which a plurality of needle-like or columnar crystals 1001 are assembled.

In FIG. 10B, reference numeral 1002 denotes a crystal grain boundary indicating a boundary between the acicular or columnar crystals, and the acicular or columnar crystals 1001 are mutually separated from the extending direction of the grain boundary 1002. It can be confirmed that the crystals grew in directions substantially parallel to each other.

Further, in the semiconductor device of the present invention, a metal element (mainly nickel in this specification) which promotes crystallization is gettered and removed by heat treatment in an atmosphere containing a halogen element, and 1 × 10 ¹⁸ SIMS analysis (secondary ion mass) indicates that nickel remaining at a concentration of atoms / cm ³ or more is reduced to 1 × 10 ¹⁸ atoms / cm ³ or less (preferably 1 × 10 ¹⁷ atoms / cm ³ or less). Analysis).

Of course, it is considered that other metal elements (Cu, Al, etc.) mixed due to contamination or the like have been similarly gettered and removed.

At this time, the silicon atoms bonded to the nickel are broken and form many dangling bonds. However, during the heat treatment in the halogen atmosphere, the silicon atoms are bonded to oxygen to form oxides. (Silicon oxide) is formed. As a result, it is considered that silicon oxide is formed in the region that was the “malignant crystal grain boundary”, and silicon oxide substantially functions as a crystal grain boundary.

The thus formed grain boundary 1002
Is presumed to be in a state where the interface between silicon oxide and crystalline silicon is excellent in matching with almost no lattice defects. this is,
Interstitial silicon atoms that cause defects are formed by a synergistic effect between the process of forming silicon oxide by thermal oxidation and the process of promoting the recombination of silicon atoms or the combination of silicon and oxygen atoms by the catalytic action of nickel. Because it is consumed.

That is, the crystal grain boundary indicated by 1002 in FIG. 10 has almost no defects such as capturing carriers,
For carriers moving inside needle or columnar crystals,
It is thought to behave as a "benign grain boundary" that only functions as an energy barrier.

Further, since such a crystal grain boundary preferentially undergoes a thermal oxidation reaction, a thermal oxide film is formed thicker than other regions. Therefore, when the thermal oxide film is used as a gate insulating film, it is presumed that an apparently small gate voltage applied in the vicinity of a crystal grain boundary can also be an energy barrier.

However, considering the TFT characteristics described later,
The energy barrier of the grain boundary 1002 is not so high as to completely hinder the movement of carriers, and it is assumed that carriers moving beyond the grain boundary exist with a considerable probability.

When this heat treatment is performed at a relatively high temperature exceeding 700 ° C. (typically 800 to 1100 ° C.), crystal defects such as dislocations and stacking faults existing inside needle-like or columnar crystals are obtained. Almost disappears. Furthermore, the dangling bonds of the remaining silicon atoms are terminated by hydrogen and halogen elements contained in the film.

Accordingly, in the state shown in FIG. 10A obtained as described above, the present inventors defined the region inside a plurality of needle-like or columnar crystals as “a region that can be substantially regarded as a single crystal for a carrier”. Is defined as

The phrase "can be regarded substantially as a single crystal for the carrier" means that there is no barrier that hinders the movement of the carrier when the carrier moves. In other words, there is no potential barrier.

According to the present invention, an active layer of a semiconductor device typified by a TFT is formed by using the crystalline silicon film having the above structure, and a high-performance semiconductor device sufficient for forming a driving circuit or a logic circuit. Is realized.

The configuration of the present invention as described above will be described in detail with reference to the embodiments described below.

[0036]

【Example】

[Embodiment 1] This embodiment shows an example in which a crystalline silicon film formed according to the manufacturing method of the present invention is used as an active layer of a thin film transistor (TFT). FIG. 1 shows a TFT
This is an embodiment of the manufacturing process of the present invention.

The means for crystallizing the amorphous silicon film used in this embodiment is a technique described in Japanese Patent Application Laid-Open No. 7-321339. Therefore, in the present embodiment, only the outline is described.

First, a substrate 101 having an insulating surface is prepared. In this embodiment, a silicon oxide film 102 is formed as a base film on a quartz substrate to a thickness of 2000 mm. As a method for forming the silicon oxide film 102, a low pressure thermal CVD method, a plasma CVD method,
A sputtering method or the like may be used. Further, when the upper limit temperature of the TFT manufacturing process is 700 ° C. or lower, a glass substrate can be used as the base 101.

When the amorphous silicon film is crystallized later,
The present inventors have found that the denser the base film, the better the crystallinity of the obtained crystalline silicon film. It is preferable that the film contain oxygen of 5 × 10 ¹⁷ to 2 × 10 ¹⁹ atoms / cm ³ . Oxygen contained in the film plays an important role in later crystal gettering treatment of the metal element which promotes the crystal.

Next, an amorphous silicon film 103 is formed to a thickness of 750.degree. Disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), or the like may be used as a deposition gas. Note that an amorphous silicon film formed by a low-pressure thermal CVD method has a low natural nucleation rate during subsequent crystallization. This is desirable in order to increase the lateral growth width, since the rate at which individual crystals interfere with each other (collision stops growth) is reduced.

Of course, as a method of forming the amorphous silicon film 103, a plasma CVD method, a sputtering method, or the like can be used.

Next, a silicon oxide film 1 having a thickness of 500 to 1200.degree.
04 is formed by a plasma CVD method or a sputtering method, and only a region where a metal element for promoting crystallization is introduced is selectively removed by etching. That is, the silicon oxide film 104 functions as a mask insulating film for selectively introducing nickel to the amorphous silicon film 103.

The region 105 exposed by the silicon oxide film 104 is formed in a slit shape having a longitudinal direction in a direction perpendicular to the paper surface. (Fig. 1 (A))

Next, UV light is irradiated in an oxygen atmosphere to form an extremely thin oxide film (not shown) on the surface of the amorphous silicon film 103 exposed by the region 105. This oxide film is for improving the wettability of the solution in the solution coating step when introducing a metal element that promotes crystallization later.

The metal elements that promote crystallization include Fe, Co, Ni, Ru, Rh, Pd, Os, and I.
One or more elements selected from r, Pt, Cu, and Au are used. In this embodiment, Ni (nickel) is used.
Will be described as an example.

Next, a nickel nitrate solution (or nickel acetate solution) containing nickel at a predetermined concentration (10 ppm in terms of weight in this embodiment) is dropped, and a thin water film 106 containing nickel is spin-coated. To form The concentration of nickel added to the amorphous silicon film can be easily controlled by adjusting the concentration of the nickel salt solution in the solution coating step. (FIG. 1 (B))

Next, at 450 ° C. in an inert atmosphere,
After degassing for about an hour, heat treatment at 500-700 ° C, typically 550-600 ° C, for 4-8 hours (No. 1)
Is performed, and the amorphous silicon film 103 is crystallized. Thus, a crystalline silicon film 107 is obtained. (Figure 1
(C))

At this time, in the crystal growth, needle-like or columnar crystals proceed in a direction substantially parallel to the substrate. In the case of this embodiment,
Since the region indicated by 105 has a slit shape having a longitudinal direction from the near side to the far side of the drawing, the arrow 1
As indicated by 08, crystal growth proceeds in substantially one direction. At this time, the crystal growth can be performed over several hundred μm.

It is to be noted that reference numeral 109 denotes a nickel-added region, which contains nickel at a higher concentration than the lateral growth region 107. The crystallinity of the added region 109 is not so good because the crystal nuclei grow excessively densely and crystal grow. Therefore, an active layer to be formed later is formed of a region excluding the addition region 109.

During crystallization, nickel contained in the water film 106 diffuses through the oxide film (not shown) into the amorphous silicon film 103 and functions as a catalyst for promoting crystallization. Specifically, nickel and silicon react with each other to form silicide, which serves as a crystal nucleus to promote crystallization.

At this time, the crystal growth proceeds with a needle-like or columnar crystal extending in a direction substantially parallel to the substrate from the region where the crystal nuclei are generated. At this time, if the temperature of the heat treatment exceeds 600 ° C., spontaneous nucleation occurs irrespective of the catalytic action of nickel. Then, the crystal growth of needle-like or columnar crystals having nickel silicide as a crystal nucleus is inhibited, and the growth width of the crystal growth becomes short, which is not preferable. Therefore, it is desirable that the conditions are such that natural nuclei are less generated and crystal nuclei are generated only by the introduced nickel.

Next, after the heat treatment for crystallization is completed, the silicon oxide film 104 serving as a mask insulating film for selectively adding nickel is removed. This step is easily performed with buffered hydrofluoric acid or the like.

The crystalline silicon film 105 before and / or after the subsequent heat treatment in an atmosphere containing a halogen element.
May be subjected to laser annealing using an excimer laser. However, although the crystallinity of the crystalline silicon film can be improved by laser irradiation, care must be taken because irregularities are easily formed on the surface of the silicon film.

Next, the obtained crystalline silicon film 107 is patterned to form an island-like semiconductor layer 110. The island-shaped semiconductor layer 110 functions later as an active layer of the TFT. In the present invention, the arrangement of the island-shaped semiconductor layers is important. This will be described later.

In this embodiment, after the island-shaped semiconductor layer 116 is formed, a heat treatment is performed in the atmosphere containing the next halogen element. Conversely, before the island-shaped semiconductor layer is formed, the heat treatment is performed in the atmosphere containing the halogen element. Heat treatment in the inside may be performed.

However, processing the crystalline silicon film 107 into an island shape increases the surface area, and is therefore preferable for efficiently gettering nickel.

Although the island-shaped semiconductor layer 110 is formed by dry etching, plasma damage remaining at the edge of the island-shaped semiconductor layer at that time may cause a leak current of the TFT. In the case of the present embodiment, the island-shaped semiconductor layer 11
Since the 0 edge is thermally oxidized, it also serves to remove plasma damage.

Next, heat treatment (second heat treatment) is performed on the island-shaped semiconductor layer 110 obtained in the above step in an atmosphere containing a halogen element. The temperature range of the heat treatment is a temperature exceeding 700 ° C, preferably 800 to 1000 ° C.
(Typically 950 ° C) and the treatment time is 1 to 24 hours, typically 6 to 12 hours.

In this embodiment, heat treatment is performed at 950 ° C. for 30 minutes in an atmosphere containing hydrogen chloride (HCl) at a concentration of 0.5 to 10% by volume in an oxygen (O ₂ ) atmosphere. If the HCl concentration is higher than the above-mentioned concentration, the surface of the crystalline silicon film is not preferable because the surface of the film has asperities as the film thickness.

The heat treatment oxidizes the silicon film of about 250 ° on the surface of the island-like semiconductor layer 110 to 500 °
Is formed, and the thickness of the island-shaped semiconductor layer 110 is about 500 °.

It is important that the heat treatment for gettering is performed at a temperature of 700 ° C. or more in order to obtain the effect. At a temperature lower than that, the thermal oxide film formed on the film surface becomes a blocking layer and a sufficient gettering effect cannot be obtained.

In the gettering process, various conditions can be set by appropriately setting the processing temperature, the processing atmosphere, and the processing time. For example, when it is desired to set a longer processing time and a longer effective gettering time, this can be achieved by lowering the processing temperature or reducing the content of the halogen element.

In this embodiment, the island-shaped semiconductor layer 110
The purpose of gettering and removing nickel contained in the steel (strictly segregated at the grain boundaries of needle-like or columnar crystals) with a halogen element, and forming a thermal oxide film and using it as a gate insulating film It serves both purpose and purpose.

Of course, both purposes are separately divided, and a heat treatment for gettering and a thermal oxide film (gate insulating film)
Heat treatment for formation (third heat treatment) can be performed separately.

A gate insulating film made of a silicon oxide film is formed on the island-shaped semiconductor layer by a plasma CVD method, a low pressure thermal CVD method,
Deposited by any means of sputtering method, then
Heat treatment may be performed in an atmosphere containing the halogen element.

In this embodiment, an example in which HCl gas is used as a compound containing a halogen element has been described. However, HF, NF ₃ , HBr, Cl ₂ , ClF
_One or more compounds selected from halogen-containing compounds such as ₃ , BCl ₃ , F ₂ , and Br ₂ can be used. In general, a hydride or an organic substance (hydrocarbon) of a halogen can also be used.

In this step, it is considered that nickel segregated at the crystal grain boundaries of the needle-like or columnar crystals is gettered by the action of the halogen element, becomes volatile nickel chloride, is released to the atmosphere and is removed. .

The above-described gettering step does not include nickel or does not affect device characteristics (1).
× 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³
It has been confirmed by SIMS analysis that the island-shaped semiconductor layer 110 reduced to the following) can be obtained. Further, the impurity concentration in this specification is defined by the minimum value of the measurement value obtained by the SIMS analysis. (Fig. 1 (D))

According to the knowledge of the present inventors, nickel used to promote crystallization tends to segregate at the crystal grain boundaries of acicular or columnar crystals, and substantially nickel is contained inside the acicular or columnar crystals. Is considered to be hardly included.

However, in the current SIMS analysis, information on both the inside of the crystal and the grain boundary is picked up. Therefore, strictly speaking, the nickel concentration in this specification refers to the nickel contained in the inside of the crystal and the grain boundary. The average density is an average density.

When the gettering step is performed,
The halogen element used for the gettering process remains in the crystalline silicon film at a concentration of 1 × 10 ¹⁵ to 1 × 10 ²⁰ atoms / cm ³ . At that time, there is a tendency that a high concentration is distributed between the crystalline silicon film and the thermal oxide film.

The nickel removed in the gettering step is extruded and segregated to the needle or columnar crystal grain boundaries during crystallization. That is, it is considered that nickel silicide was present at the crystal grain boundaries.

Nickel which has been present as nickel silicide is separated as nickel chloride and is separated, and a large number of dangling bonds of silicon disconnected from nickel are present at crystal grain boundaries.

However, since the above process is performed at a relatively high temperature in an oxidizing atmosphere, the formed dangling bonds are easily combined with oxygen to form an oxide (silicon oxide represented by SiO _X ). It is thought that. That is, the present inventors believe that the crystalline silicon film becomes a crystalline structure in which silicon oxide functions as a crystal grain boundary by the above-described series of heating steps.

The remaining dangling bonds are terminated by hydrogen or a halogen element contained in the island-shaped semiconductor layer 110 or compensated by recombination between silicon. Further, crystal defects such as dislocations and stacking faults are reduced. It is considered that the crystallinity inside the needle-like or columnar crystal is also remarkably improved because it is almost eliminated by recombination or rearrangement of silicon atoms.

Accordingly, the island-like semiconductor layer 110 is sufficiently removed by heat treatment in a halogen atmosphere to such an extent that nickel does not affect the device characteristics.
The needle-like or columnar crystal constituting 10 has remarkably improved crystallinity and is composed of a crystal structure having a region that can be regarded as a substantially single crystal for the carrier.

As described above, when the formation of the gate insulating film (thermal oxide film) 111 is completed, an aluminum film (not shown) for forming the gate electrode is formed by sputtering to a thickness of 2500 °. Form a film. The aluminum film contains 0.2% by weight of scandium to prevent hillocks and whiskers.

In this embodiment, a material mainly composed of aluminum is used as a material for forming the gate electrode (including the gate line). However, tungsten, tantalum, molybdenum, or the like may be used. Further, a crystalline silicon film provided with conductivity may be used as a gate electrode.

After forming the aluminum film, an extremely thin anodic oxide film (not shown) is formed on the surface. This anodic oxide film is obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid with aqueous ammonia as an electrolytic solution. That is, in this electrolytic solution, the aluminum film is used as an anode,
Anodization is performed using platinum as a cathode.

The anodic oxide film formed in this step has a dense film quality and functions to improve the adhesion to a resist mask to be formed later. The thickness of this anodic oxide film is set to about 100 mm. The film thickness can be controlled by the applied voltage.

Next, as shown in FIG. 1D, the aluminum film is patterned to form an island-shaped aluminum film pattern 112 serving as a gate electrode prototype. The resist mask (not shown) used at this time is left as it is. (Fig. 2 (A))

Then, the pattern 1 of the aluminum film is again
Anodization is performed using 12 as an anode. Here, a 3% oxalic acid aqueous solution is used as the electrolytic solution. In this anodic oxidation step, anodic oxidation proceeds only on the side surfaces of the aluminum pattern 112 due to the presence of a resist mask (not shown). Therefore, in FIG.
An anodic oxide film is formed as shown by 3.

The anodic oxide film 11 formed in this step is
3 has a porous shape and can be grown up to several μm. This porous anodic oxide film 1
13 has a thickness of 0.7 μm. The anodic oxide film 11
The film thickness of No. 3 can be controlled by the anodic oxidation time.

The porous anodic oxide film 1 shown in FIG.
After the formation of the resist 13, the resist mask (not shown) is removed. Then, by performing anodic oxidation again, a dense anodic oxide film 114 is formed. This anodic oxidation step is performed under the same conditions as those for forming the dense anodic oxide film described above.

Note that the film thickness to be formed is 900 °. In this step, an anodic oxide film 114 is formed as shown in FIG. 2B because the electrolytic solution enters the inside of the porous anodic oxide film 113. Also, the anodic oxide film 114
When the thickness of the film is increased to 1500 ° or more, an offset gate region can be formed in a subsequent impurity ion implantation step.

Further, through the above steps, the gate electrode 115
Is defined. The dense anodic oxide film 114 functions to protect the surface of the gate electrode 115 in a later step and to suppress generation of hillocks and whiskers.

Next, after the formation of the dense anodic oxide film 114, impurity ions for forming source / drain regions are implanted in this state. N-channel type T
To make FT, P (phosphorus) ions are implanted,
If a P-channel type TFT is manufactured, B (boron) ions may be implanted.

In this step, a source region 116 and a drain region 117 to which impurities are added at a high concentration are formed.

Next, using a mixed acid obtained by mixing acetic acid, phosphoric acid and nitric acid, the porous anodic oxide film 113 is selectively removed, and then P ions are implanted again. This ion implantation is performed at a lower dose than when the source / drain regions are formed. (Fig. 2 (C))

As a result, low-concentration impurity regions 118 and 119 having a lower impurity concentration than the source region 116 and the drain region 117 are formed. And the gate electrode 115
A region indicated by 120 immediately below becomes a channel forming region in a self-aligned manner.

The low-concentration impurity region 119 disposed between the channel formation region 120 and the drain region 117
Is particularly called an LDD (lightly doped drain region) region and has an effect of relaxing a high electric field formed between the channel forming region 120 and the drain region 117.

The channel forming region 120 (strictly, inside the needle or columnar crystal) is an intrinsic or substantially intrinsic region. An intrinsic or substantially intrinsic region is a region where the activation energy is almost half (the Fermi level is located at the center of the forbidden band) and the impurity concentration is lower than the spin density. Or an undoped region in which impurities such as P and B are not intentionally added.

Further, after the above-described impurity ion implantation step, the region where the ion implantation has been performed is annealed by irradiating laser light, infrared light or ultraviolet light. This process activates the added ions and recovers the damage caused to the active layer during the ion implantation.

[0094] Here, the plasma hydrogenation treatment is performed at 300 to
It is effective to carry out at a temperature of 350 ° C. for 0.5 to 1 hour.
In this step, dangling bonds generated by desorption of hydrogen from the active layer are terminated with hydrogen again. By performing this step, hydrogen is added to the active layer at a concentration of 1 × 10 ²¹ atoms / cm ³ or less, preferably 1 × 10 ¹⁵ to 1 × 10 ²¹ atoms / cm ³ .

When the state shown in FIG. 2C is obtained, the interlayer insulating film 121 is formed next. Interlayer insulating film 121
Is composed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film of these films. (FIG. 2 (D))

The use of a silicon nitride film is preferable because the hydrogen added in the previous step can be prevented from being re-emitted to the outside of the device.

Further, when polyimide, which is an organic resin film, is used, since the relative dielectric constant is small, the parasitic capacitance between the upper and lower wirings can be reduced. Further, since the film can be formed by the spin coating method, the film thickness can be easily increased, and the throughput can be improved.

Next, a contact hole is formed in the interlayer insulating film 121, and the source electrode 122 and the drain electrode 123 are formed.
And are formed. Further, by performing a heat treatment in a hydrogen atmosphere at 350 ° C., hydrogenation of the entire device is performed.
The TFT shown in FIG. 2D is completed.

Although the TFT shown in FIG. 2D has the simplest structure for explanation, a desired TFT structure can be obtained by making some changes and additions to the manufacturing process procedure of this embodiment. Is easy. According to this, a pixel TFT constituting a pixel matrix circuit of an active matrix display device
Alternatively, a circuit TFT (an inverter circuit, a shift register circuit, a processor circuit, a memory circuit, or the like) included in a logic circuit can be manufactured.

Here, the reason why the arrangement is important in forming the island-shaped semiconductor layer 110 as described above will be described. The description will be made with reference to FIG.

The present embodiment is characterized in that needle-like or columnar crystals grow substantially parallel to each other, and thus the crystal grain boundaries are aligned in one direction. Further, by selectively adding a metal element that promotes crystallization, it is possible to freely control the direction in which needle-like or columnar crystals grow. This has very important implications.

FIG. 3 shows an embodiment in which an island-like semiconductor layer is formed on a substrate having an insulating surface. FIG. 3 shows island-shaped semiconductor layers arranged in a matrix on a substrate 301 in manufacturing an active matrix liquid crystal display device.

The area indicated by the broken line 302 is where the area for selectively introducing nickel was present. Reference numeral 303 denotes a place where a macroscopic grain boundary formed by colliding lateral growth regions with each other is present. Since these cannot be confirmed after the island-shaped semiconductor layer is formed, they are indicated by dotted lines.

When crystallization is performed by the means described in this embodiment, the needle-like or columnar crystals are formed in the nickel-added region 30.
2 grows in a direction substantially perpendicular to (the direction indicated by the arrow in the figure).

Therefore, by arranging the island-shaped semiconductor 304 as shown in FIG. 3, the channel direction and the crystal grain boundary of the acicular or columnar crystal can be aligned in the same direction. Moreover,
By designing the nickel-added region 302 to extend from one end of the substrate 301 to the other, the above-described configuration can be realized over the entire surface of the substrate.

With such a configuration, the channel direction coincides with the direction in which the needle-like or columnar crystals are arranged.
In other words, the direction of the channel and the moving direction of the carrier moving inside the needle-like or columnar crystal are the same.

That is, it means that when functioning as the active layer of the TFT, the energy barrier that hinders the movement of carriers in the channel formation region is extremely small, and further improvement in the operation speed can be expected.

Therefore, the TFT shown in this embodiment can realize a very high-speed operation by adopting a configuration in which the direction in which the needle-like or columnar crystal extends and the channel direction coincide with each other.

Here, FIG. 4 shows the electrical characteristics of the semiconductor device shown in FIG. 2D manufactured by the present inventors according to this embodiment. FIG. 4A shows the electric characteristics (Id-Vg characteristics) of the N-channel TFT, and FIG. 4B shows the electric characteristics of the P-channel TFT. The graph showing the Id-Vg characteristics collectively displays the measurement results for ten points.

VG on the horizontal axis is the gate voltage value, and ID on the vertical axis is the current value flowing between the source and the drain. Also, 40
Id-Vg characteristics (Id-Vg curves) indicated by 1, 403 indicate characteristics when the drain voltage VD = 1V, and 402, 404
The Id-Vg characteristic shown by the symbol indicates the characteristic when the drain voltage VD = 5V. Reference numerals 405 and 406 denote leakage currents when the drain voltage VD = 1V.

The drain current (Ioff) in the off region (-1 V or less in FIG. 4A and -1 V or more in FIG. 4B).
And the leakage current (IG) in the on and / or off regions
Since it is less than 1 × 10 ^-13 A (lower limit of measurement), FIG.
(A) and (B) are confused with noise.

Tables 1 and 2 show typical characteristic parameters of the TFT according to the present invention obtained from the electric characteristics shown in FIGS. 4A and 4B. Table 1 shows the results of the electrical characteristics of the N-channel TFT (arbitrary 20-point measurement), and Table 2 shows the results of the electrical characteristics of the P-channel TFT (arbitrary 20-point measurement).

[0113]

[Table 1]

[0114]

[Table 2]

[0115] In Tables 1 and 2, it should be particularly noted that
Sub-threshold characteristic (S value, S-value) is 60-100m
It is small enough to fall within V / dec, and the mobility (μFE, mobility) is extremely large, such as 150 to 300 cm ² / Vs. Note that in this specification, mobility means field-effect mobility.

These measurement data are values that cannot be achieved with the conventional TFT, and just prove that the TFT according to the present invention is an extremely high-performance TFT comparable to a MOSFET formed on a single crystal.

At the same time, it has been confirmed by repeated acceleration measurements that the TFT according to the present invention is very resistant to deterioration. Empirically, a TFT operating at a high speed has a disadvantage that it is easily deteriorated, but it has been found that the TFT according to the present invention has no deterioration and has an extremely high withstand voltage characteristic.

Tables 1 and 2 also show the average value and standard deviation (σ value) for reference. The standard deviation is used as a measure of the variance (variation) from the mean. Generally, the measurement result (population) is normally distributed (Gaussian distribution)
According to the above, the total 6 within ± 1σ around the average value
It is known that 95.4% falls within 8.3%, ± 2σ, and 99.7% falls within ± 3σ.

For example, when 100 N-channel TFTs manufactured according to the present invention are measured, the S value of about 95 TFTs is 60 to 100 mV / dec (even for the P-channel TFT,
~ 100mV / dec).

The present inventors measured 540 TFTs in order to more accurately evaluate the dispersion of the TFT characteristics of the present embodiment, and obtained the average value and the aiming deviation from the results. As a result, the average value of the S value was 80.5 mV / dec (n-ch), 80.6 mV / dec (p
-ch), and the standard deviation was 5.8 (n-ch) and 11.5 (p-ch). The average value of mobility (max) is 194.0 cm ² / Vs (nc
h), 131.8 cm ² / Vs (p-ch) with a standard deviation of 38.5 (nc
h), 10.2 (p-ch).

That is, an N-channel type TF utilizing the present invention
In T, the following TFT characteristics can be obtained. (1) The σ value of the S value is within 10 mV / dec, preferably 5 mV / dec
Within. (2) S value is within 80 ± 30mV / dec, preferably 80 ± 15mV / d
Fit within ec. (3) The μFE σ value is within 40 cm ² / Vs, preferably 35 cm ² / Vs
Within.

Also, a P-channel type TF utilizing the present invention
In T, the following TFT characteristics can be obtained. (1) The σ value of the S value is within 15 mV / dec, preferably 10 mV / dec
Within. (2) S value within 80 ± 45mV / dec, preferably 80 ± 30mV
Fits within / dec. (3) The σ value of μFE is within 15 cm ² / Vs, preferably 10 cm ² / Vs
Within.

As described above, the TFT according to the present invention realizes extremely excellent electric characteristics, and a complicated SRAM circuit, DRAM circuit, etc., in which only a MOSFET fabricated on a single crystal has been used so far. It is possible to configure a logic circuit requiring high-speed operation.

In this embodiment, only an example of a manufacturing process of a single-gate structure TFT is described. However, the present invention is also applied to a double-gate structure TFT and a multi-gate structure TFT having more gate electrodes. be able to.

It is also possible to manufacture an inverted stagger type TFT using a crystalline silicon film as a gate electrode. That is, the present invention can be realized by increasing the crystallinity of the active layer, and can be implemented regardless of the TFT structure.

[Knowledge on Crystalline Structure Obtained by the Present Invention] The crystalline silicon film obtained by the present invention is shown in FIG.
It has already been described that the crystal structure is an aggregate of needle-like or columnar crystals as shown in (A). Here, a comparison is made between the crystal structure according to the present invention and a crystal structure formed by another method.

The photograph shown in FIG. 11 is a TEM photograph of a sample which has been subjected to the crystallization of the amorphous silicon film in the procedure of Example 1. That is, it shows the crystal structure of a crystalline silicon film which has not been subjected to a heat treatment containing a halogen element.

As can be seen from FIG. 11, a large number of dislocation defects (1
(Circle 101). However, in the TEM photograph shown in FIG. 10A, such a dislocation defect is not confirmed, and it can be seen that the crystal has a clear crystal structure.

This is evidence that the heat treatment in an atmosphere containing a halogen element in the present invention greatly contributes to the improvement of crystallinity.

The crystal structure shown in FIG. 12 is an example in which the crystallization conditions of the amorphous silicon film are different from those of the present invention. Specifically, the amorphous silicon film is crystallized by performing heat treatment at 600 ° C. for 48 hours in a nitrogen atmosphere,
Thermal oxidation treatment is performed at a temperature of about 1100 ° C.

The crystalline silicon film formed as described above
As shown in FIG. 12A, individual crystal grains are large and are divided by irregularly distributed grain boundaries.
FIG. 12A schematically shows FIG.
(B).

In FIG. 12B, a crystal grain 1201 is surrounded by an irregular grain boundary 1202. Therefore, the crystal structure shown in FIG.
When used as an active layer of FT, irregular grain boundaries 1202
The energy barrier caused by this hinders the movement of carriers.

On the other hand, in a crystal structure as shown in FIG. 10A, crystal grain boundaries 1002 are arranged with a certain degree of regularity as shown in FIG. 10B. Therefore, it is considered that there is no energy barrier that hinders the movement of carriers inside the acicular or columnar crystals.

As a result of observation by the present inventors of the arrangement state of the needle-like or columnar crystals in a wide field of view of about 10,000 to 50,000 times, the needle-like or columnar crystals may sometimes progress in a zigzag manner. Has been confirmed. This is a phenomenon caused by the fact that crystal growth proceeds in a direction that is stable in terms of energy, and it is assumed that a kind of grain boundary is formed at a portion where the crystal direction is changed.

However, the present inventors speculate that this grain boundary which may be formed inside the needle-like or columnar crystal may be like an energetically inert twin grain boundary. That is, it is considered that the grain boundary is a grain boundary which is different in crystal direction but is continuously bonded with good consistency, and does not become an energy barrier enough to hinder carrier movement (not substantially regarded as a grain boundary). I have.

As described above, a polycrystalline silicon (polysilicon) film crystallized by a normal process has a crystal structure as shown in FIG. 12A, and has an irregular structure so as to block carrier movement. Due to the distribution of grain boundaries, it is difficult to achieve high mobility.

However, the crystalline silicon film according to the present invention has a crystal structure as shown in FIG. 10A, the crystal grain boundaries are substantially aligned in one direction, and the inside of the acicular or columnar crystal is substantially It is considered that there is no grain boundary that serves as an energy barrier. That is, the carriers can move inside the crystal without any hindrance, so that extremely high mobility can be achieved.

In particular, the point of the needle-like or columnar crystal obtained by the present invention is that several tens to several hundreds of μm are formed while avoiding distortion due to unevenness or stress (changing the crystal direction).
The point is that the distance is thought to grow continuously.

If the present inventors speculate correctly, the crystalline silicon film according to the present invention is formed of a special crystal aggregate which grows without forming a grain boundary that can serve as a carrier trap inside the crystal. It can be said that this is a new crystal structure.

[Embodiment 2] This embodiment is an example in which a CMOS circuit is formed using the TFT shown in Embodiment 1. CM
The OS circuit has an N-channel type T having a structure as shown in the first embodiment.
The FT and the P-channel TFT are configured in a complementary manner.

One embodiment of a process for manufacturing a CMOS circuit in this embodiment will be described with reference to FIGS. The application range of the crystalline silicon film formed by the present invention is wide, and C
The method of forming the MOS circuit is not limited to this embodiment.

First, a silicon oxide film 502 is formed on a quartz substrate 501 according to the manufacturing procedure shown in Embodiment 1, and a crystalline silicon film (not shown) is obtained thereon. By patterning it, an island-shaped semiconductor layer 503 of an N-channel TFT and an island-shaped semiconductor layer 504 of a P-channel TFT are formed.

After the island-shaped semiconductor layers 503 and 504 are formed, heat treatment is performed in an atmosphere containing a halogen element. In this embodiment, the processing conditions are the same as in the first embodiment. Thus, the thermal oxide film 5 functioning as a gate insulating film
05, 506 are formed with a thickness of 500 °.

Here, for simplification of description, an example in which a pair of N-channel TFT and P-channel TFT is formed will be described. Actually, an N-channel TFT and a P-channel TFT are formed in units of several hundreds or more on the same glass substrate.

Next, an aluminum film (not shown) constituting a prototype of the gate electrode is formed and patterned to form aluminum film patterns 507 and 508 (resist mask used for patterning after pattern formation). Is kept).

As in the first embodiment, this aluminum film contains scandium at 0.2 wt% in order to suppress the generation of hillocks and whiskers. The aluminum film is formed by a sputtering method or an electron beam evaporation method.

Hillocks and whiskers are bar-like or needle-like protrusions caused by abnormal growth of aluminum. The presence of hillocks or whiskers causes a short circuit or crosstalk between adjacent wirings or between wirings separated between upper wirings.

As a material other than the aluminum film, an anodizable metal such as tantalum and molybdenum can be used. Further, instead of the aluminum film, a silicon film provided with conductivity can be used.

Thus, the state shown in FIG. 5A is obtained. After forming the aluminum film patterns 507 and 508,
Next, the porous anodic oxide film 5 was formed on the side surfaces of the aluminum film patterns 507 and 508 under the same conditions as in the first embodiment.
09 and 510 are formed. In this embodiment, the thickness of the porous anodic oxide films 509 and 510 is set to 0.7 μm.

Further, dense and strong anodic oxide films 511 and 512 are formed under the same conditions as in the first embodiment.
However, in this embodiment, the attained voltage is adjusted so that the film thickness becomes 700 Å. In addition, the gate electrode 51
3, 514 are defined. Thus, a state as shown in FIG. 5B is obtained.

Next, P (phosphorus) ions are doped on the entire surface as an impurity for imparting N-type. This doping is 0.2-5 × 10 ¹⁵ atoms / cm ² , preferably 1-2 × 10
^This is performed at a high dose of ¹⁵ atoms / cm ² . As a doping method, a plasma doping method or an ion doping method is used.

As a result of the step shown in FIG. 5C, regions 515 to 518 in which P ions are implanted at a high concentration are formed. These regions will later function as source / drain regions. (FIG. 5 (C))

Next, the porous anodic oxide films 509 and 510 are removed using a mixed acid solution obtained by mixing acetic acid, nitric acid and phosphoric acid. At this time, the active layer region located immediately below the anodic oxide films 509 and 510 is substantially intrinsic because no ions are implanted.

Next, P ions are implanted again as shown in FIG. This implantation of P ions reduces the dose.
0.1 to 5 × 10 ¹⁴ atoms / cm ² , preferably 0.2 to 1 × 10 ¹⁴ a
The value is as low as toms / cm ² .

That is, the P shown in FIG.
The dose of the ion implantation is set lower than the dose performed in the step illustrated in FIG. Then, as a result of this step, low-concentration impurity regions 519 to 522 having a lower impurity concentration than regions 515 to 518 are formed.

At the time when the step shown in FIG.
The active layer of the channel type TFT is completed. That is, the source region 515, the drain region 516, and the
Low concentration impurity regions (or LDD regions) 519, 52
0, a channel forming region 523 is defined.

Although not particularly shown, the anodic oxide film 511
The region blocked by the ion implantation is the channel forming region 523.
And low concentration impurity regions 519 and 520.
This region is called an offset region, and the anodic oxide film 511
The distance is determined by the thickness of the film.

The offset region is substantially intrinsic without being ion-implanted. However, since no gate voltage is applied, no channel is formed, and the offset region functions as a resistance component for relaxing electric field intensity and suppressing deterioration. However, if the distance (offset width) is short, it does not function as an effective offset area. In this embodiment, since the width is 700 mm, it does not function as an offset area.

Next, as shown in FIG. 6A, a resist mask 524 covering the left N-channel TFT is formed. Then, in the state shown in FIG. 6A, B (boron) ions are implanted as impurities imparting P-type.

Here, the dose of B ions is set to 0.2 to 10
× 10 ¹⁵ atoms / cm ² , preferably 1-2 × 10 ¹⁵ atoms / cm ²
Degree. This dose is approximately equal to or greater than the dose in the P ion implantation step shown in FIG.

By this step, impurity (P ion) region 5 is formed.
17, 518, 521, and 521 are all inverted from N-type to P-type, and the source region 52 of the P-channel TFT is
5, a drain region 526 is formed. Further, a channel formation region 527 is formed immediately below the gate electrode 514.

Next, after the step shown in FIG. 6A is completed, the resist mask 524 is removed, and the entire surface of the substrate is irradiated with laser light or strong light such as infrared light or ultraviolet light. The activation of the impurity ions added in this step and the recovery of the damage of the region into which the impurity ions have been implanted are performed. (FIG. 6
(B))

Next, after obtaining the state shown in FIG. 6B, an interlayer insulating film 528 is formed to a thickness of 4000 °. The interlayer insulating film 528 may be any of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, and an organic resin film, and may have a multilayer structure.
These insulating films can be formed by plasma CVD, thermal CV
Method D and spin coating may be used.

Next, a contact hole is formed, and a source electrode 529 of an N-channel TFT and a P-channel TF
A T source electrode 530 is formed. Further, a CMOS circuit is realized by having a configuration in which the drain electrode 531 is shared by the N-channel TFT and the P-channel TFT. (FIG. 6 (C))

Through the above process, a CMOS circuit having the structure shown in FIG. 6C can be manufactured. CM
The OS circuit is an inverter circuit having the simplest configuration.
A closed circuit formed by connecting an odd number of MOS inverter circuits in series is called a ring oscillator, and is used when evaluating the operation speed of a semiconductor device.

Here, the top photograph shown in FIG. 7A is a ring oscillator circuit formed by combining CMOS circuits manufactured according to this embodiment. The present inventors made a prototype of an active matrix type liquid crystal display device using the present invention, and confirmed the operation performance of the driving circuit using a ring oscillator.

The gate electrode width of the CMOS circuit forming the ring oscillator shown in FIG. 7A is as thin as about 0.6 μm, and the channel formation region is usually miniaturized to such an extent that a short channel effect occurs. I have.

FIG. 7B shows a photograph of the shift register circuit for reference. The shift register circuit illustrated in FIG. 7B is one of important circuits included in a peripheral driving circuit that is prototyped, and is a logic circuit that specifies an address of a pixel region. In particular, the shift register circuit for horizontal scanning (for the source side) is required to be driven at a very high frequency of about several MHz to several tens MHz in actual operation.

The oscillation frequency of the ring oscillator circuit is 9,
The measurement was performed using a ring oscillator to which 19 and 51 sets (stages) of CMOS circuits were connected. As a result, a power supply voltage of 3 to 5 V, 9
300MHz or higher in a ring oscillator with 500MHz
Oscillation frequency exceeding Hz was obtained, and it was found that the operation speed was extremely high.

These values indicate that the operating speed is nearly 20 times as high as that of the ring oscillator manufactured by the conventional manufacturing process. Further, even when the power supply voltage is varied in the range of 1 to 5 V, an oscillation frequency of several tens to several hundreds MHz is always realized.

The ring oscillator circuit is a test pattern for evaluating the operation speed. When a logic circuit such as a shift register circuit or a processor circuit is actually formed, the operation speed cannot be reduced. This is because various additional capacitances are added to the logic circuit itself.

However, a CMOS circuit using the present invention can operate at high speed without any problem even in such a situation where added value is added, and has a performance that meets the requirements of all logic circuits.

Furthermore, despite the extremely miniaturized channel length of 0.6 μm, it also has high withstand voltage characteristics capable of withstanding extremely high-speed operation as shown in this embodiment. This means that the TFT according to the present invention is hardly affected by the short channel effect and has extremely high reliability.

[Inference derived from the configuration of the present invention] As shown in Embodiments 1 and 2, the TFT manufactured according to the present invention realizes extremely high performance (high-speed operation characteristics, high breakdown voltage characteristics). . In particular, conventional TFTs having an S value of 60 to 100 mV / dec and a field effect mobility (μFE) within a range of 150 to 300 cm ² / Vs (the actual field effect mobility is considered to be higher as described later) Then it was impossible to achieve.

The characteristic of having such high-speed operation characteristics but being resistant to deterioration can be said to be a peculiar phenomenon from experience. Therefore, the present inventors have considered why the TFT according to the present invention is so excellent in deterioration resistance, and have deduced one theory therefrom, which will be described below.

Breakdown voltage of TFT (breakdown voltage between source and drain)
In general, an offset region or an LDD region is provided between the channel forming region and the source / drain region in order to increase the density. However, the experience of the present inventors has shown that even with such a structure, if the mobility exceeds 150 cm ² / Vs, considerable deterioration occurs.

Therefore, the inventors of the present invention have proposed a TFT according to the present invention.
As a reason for the high pressure resistance, the influence of crystal grain boundaries of acicular or columnar crystals was emphasized. This crystal grain boundary is formed of an oxide (silicon oxide) at the same time that a metal element which promotes crystallization is removed by a heat treatment containing a halogen element, and a dangling bond of a silicon atom is combined with oxygen. I have.

In other words, the present inventors have found that a crystal grain boundary (oxide region) locally present in a channel formation region has a high electric field applied between a source region and a drain region, particularly between a channel formation region and a drain region. Was estimated to be effectively mitigating.

Specifically, an electric field formed by a depletion layer charge in which a crystal grain boundary composed of an oxide region particularly spreads from the drain region is suppressed, and a state where the drain voltage is increased (a state where the drain-side depletion layer charge is increased) ) Also considered to function so as not to change the diffusion potential on the source side.

In summary, when the crystalline silicon film according to the present invention is used for the active layer, it can be considered that the channel formation region satisfies the following configuration. (1) There is a substantially intrinsic region (within a needle or columnar crystal) where the carrier moves (for the carrier). (2) There is an impurity region (oxide region) for suppressing carrier movement or relaxing an electric field applied in a channel direction (a direction connecting a source and a drain).

Therefore, by adopting a structure that satisfies the above two structures, in other words, a structure having a channel formation region substantially intrinsic to carriers and an impurity region formed locally, the present invention has an excellent feature. It is considered that a TFT having the above characteristics can be manufactured.

The above configuration is derived from experimental data of the present inventors, though with some inference. Therefore, the present inventors have anticipated that a similar effect can be obtained by artificially creating this configuration.

As a result, the present inventors have proposed an effective configuration for suppressing the short channel effect. Here, the outline is described below. Note that the considerations described below are currently limited to speculation.

Generally, device elements (MOSFET, T
As the miniaturization of FT and the like progresses and the channel length becomes shorter, the short channel effect becomes a problem. The short channel effect is a general term for a decrease in threshold voltage, a deterioration in withstand voltage due to a punch-through phenomenon, a deterioration in sub-threshold characteristics, and the like.

The punch-through phenomenon which is particularly problematic is that the diffusion potential on the source side is reduced by the influence of the electric field on the drain side.
This is a phenomenon in which a current flows between a source and a drain even when a channel is not formed. That is, since the depletion layer on the drain side extends to the source region, the drain electric field affects the source side.

Therefore, the present inventors focused on the effect of the crystal grain boundary (oxide region) of the present invention, and found that the channel length was 0.01 to 2 μm.
In a short channel TFT of about m, it was presumed that the effect of suppressing the expansion of the drain side depletion layer can be obtained by artificially and locally providing the impurity region in the channel formation region.

It is considered that such a configuration can be achieved by forming the active layer as shown in FIG. In FIG. 8A, 801 is a source region, 802 is a drain region,
Reference numeral 803 denotes a channel forming region, and the channel forming region 8
An impurity region 804 is artificially formed in the region 03.
In the channel formation region 803, a region 805 other than the impurity region 804 is a substantially intrinsic region and serves as a region where carriers move.

Here, it is important that the structure shown in FIG. 8A is a structure imitating the crystal structure of the present invention shown in FIG. That is, the crystal grain boundary indicated by reference numeral 1001 in FIG. 10 corresponds to the impurity region 804 in FIG. 8A, and the needle-like or columnar crystal in FIG. 10 corresponds to the region 8 in FIG.
It corresponds to 05.

Therefore, impurity region 804 arranged in channel formation region 803 locally forms a region having a large built-in potential (energy barrier) in the channel formation region. It can be assumed that the spread is effectively suppressed.

FIG. 8B is a cross-sectional view taken along the line AA ′ of FIG. 806 is a substrate having an insulating surface. FIG. 8C is a cross-sectional view of FIG. 8A taken along a line BB ′.

Note that in FIG. 8C, wpi, n represents the width of the impurity region 804, and wpa, m represents the width of the region where carriers move. Here, n and m are channel formation regions 803
, Wpi, n is the width of the n-th impurity region,
wpa, m means the area where the m-th carrier moves.

The widths of wpi, n and wpa, m must satisfy a certain range of conditions. This will be described below.

In FIG. 8A, channel forming region 8 is formed.
The width of 03, that is, the channel width is W. Here, of the channel width W, the width occupied by the impurity region 804 is represented by Wpi
Is defined. Then, the width of an arbitrary impurity region is set to Wpi, ₁ ,
If Wpi, ₂ , Wpi, ₃ ... Wpi _{, n} , Wpi is represented by the following equation.

[0194]

(Equation 1)

However, in order to achieve this structure, it is necessary that at least one impurity region is formed in a region other than the end of the channel forming region, so that n must be an integer of 1 or more.

The width of the channel width W occupied by the carrier moving region 805 is defined as Wpa. Then, an arbitrary carrier moving area 805 is set to Wpa, ₁ , Wp
If a, ₂ , Wpa, ₃ ... Wpa _{, m} , Wpa is expressed by the following equation.

[0197]

(Equation 2)

However, since at least one impurity region is formed in a region other than the end of the channel forming region as described above, the channel forming region is divided into at least two and m must be an integer of 2 or more. .

That is, the total channel width W is W = Wpi + Wpa,
In addition, a relationship of n + m of 3 or more is established. It is desirable that the relationship between W and Wpi, the relationship between W and Wpa, and the relationship between Wpi and Wpa simultaneously satisfy the following conditions. Wpi / W = 0.1-0.9 Wpa / W = 0.1-0.9 Wpi / Wpa = 1 / 9-9

The meaning of these equations is that Wpa /
That is, W or Wpi / W must not be 0 or 1. For example, when Wpa / W = 0 (equivalent to Wpi / W = 1), the channel formation region is completely covered with the impurity region, so that the movement of carriers is hindered. Conversely, Wpa
When / W = 1 (same as Wpi / W = 0), since the impurity region does not exist at all in the channel formation region, the spread of the drain-side depletion layer cannot be suppressed.

Further, the knowledge regarding the equations (1) and (2) is described in Example 1.
And it plays an important role in explaining the TFT characteristics found in Example 2. This is shown below.

The present inventors have noticed that the oscillation frequency of the ring oscillator shown in the second embodiment is too high with respect to the value of the mobility shown in the first embodiment. That is, it was thought that the numerical value may differ between the actual mobility and the mobility obtained by the measurement.

The present inventors have found that the actually measured mobility value is the actual mobility (the mobility originally possessed by the TFT of the present invention).
I think it's smaller than that. The reason is,
In the measurement by the present inventors, the actually measured channel width W is substituted into the following equation for calculating the mobility.

ΜFE = 1 / Cox (ΔId / ΔVg) · 1 / Vd · L / W where Cox is the gate oxide film capacity, ΔId and ΔVg are the amounts of change in drain current Id and gate voltage Vg, Vd, respectively.
Is the drain voltage, and L and W are the channel length and channel width, respectively.

As is apparent from this equation, the field effect mobility (μFE) is inversely proportional to the channel width W. This W
Is calculated by substituting the channel width actually measured by the measuring instrument as a value.

However, as described using Equations (1) and (2), an oxide layer is actually formed between the acicular or columnar crystals, and the effective sum is obtained by subtracting the oxide layer. The channel width Wpa must be defined. That is, the substituted channel width W is a value larger than the effective channel width Wpa.

For the above reason, since the calculated mobility is obtained by substituting a channel width larger than the actual one, it is considered that the calculated mobility is apparently small. Thus, according to the present invention, in practice 40
It is presumed that a TFT achieving a mobility exceeding 0 cm ² / Vs has been realized. And it can be said that the oscillation frequency exceeding 500 MHz as shown in the second embodiment can be realized only because such mobility is achieved.

It is expected that providing the impurity regions in an arrangement as shown in FIG. 8A has a very significant effect on the improvement of the mobility. The reason will be described below.

The mobility (μFE) is determined by the scattering of carriers in a semiconductor film (here, a silicon film is taken as an example).
Scattering in a silicon film is roughly classified into lattice scattering and impurity scattering. Lattice scattering has a low impurity concentration in a silicon film and is dominant at a relatively high temperature, and impurity scattering has a high impurity concentration.
Dominant at relatively low temperatures. The overall mobility μ formed by these influences is expressed by the following equation.

[0210]

(Equation 5)

[0211] The equation expressed by the equation (5) indicates that the overall mobility μ is the mobility μ _l ( _l is
means inversely proportional to the sum of the reciprocal of lattice () and the reciprocal of mobility μ _i ( _i means impurity) under the influence of impurity scattering.

Here, in the lattice scattering, the acoustic phonon plays an important role if the drift electric field is not so strong,
The mobility μ _l of time that is proportional to the -3/2 power of the temperature as indicated by the following equation. Therefore, it is determined by the effective mass (m *) of the carrier and the temperature (T).

[0213]

(Equation 6)

The mobility μ _i due to impurity scattering is proportional to the temperature to the power of 3/2 and inversely proportional to the concentration N _i of ionized impurities as shown in the following equation. That can be varied by adjusting the concentration N _i of ionized impurities.

[0215]

(Equation 7)

According to these equations, when impurities are uniformly added to the entire channel formation region, mobility cannot be increased due to the influence of impurity scattering. However, in the case of the structure shown in FIG. 8, since the impurity region is locally formed, no impurity is added to the region where the carrier moves, and the region is substantially intrinsic to the carrier.

[0217] That is, it means that the closer to 0 without limit concentration N _i of impurities ionized in the number 7 in theory, the mobility mu _i will be approaching infinity as possible. That is, the overall mobility mu it means that the impurities are reduced to the extent that can be ignored to the section 1 / mu _i in the equation 5 is assumed that approaches the mobility mu _l as possible.

In FIG. 8A, impurity region 80 is formed.
It is important that 4 be arranged approximately parallel to the channel direction. Such an arrangement corresponds to the case where the direction in which the crystal grain boundaries of the needle-like or columnar crystals shown in FIG. 10 extend and the channel direction coincide.

In such an arrangement, impurity region 80
4 is expected to behave as a “benign crystal grain boundary”, so it is presumed that the carrier acts as a rail without capturing the carrier and regulates the moving direction of the carrier. This is a very important configuration for reducing the influence of scattering caused by collision between carriers.

It is expected that the above-described configuration can also suppress a decrease in threshold voltage, which is one of the short channel effects. This is a prediction based on the inference that a narrow channel effect generated when the channel width becomes extremely narrow can be artificially caused between impurity regions.

It is considered that the punch-through phenomenon can be suppressed by suppressing the spread of the drain-side depletion layer as described above. However, by suppressing the punch-through phenomenon, the withstand voltage can be improved and the sub-threshold characteristic can be improved. (S value) can also be improved.

The improvement in the sub-threshold characteristic can be explained as follows from the inference that the use of this structure can reduce the volume occupied by the drain-side depletion layer.

In the structure shown in FIG. 8A, if the expansion of the depletion layer is effectively suppressed, the volume occupied by the drain-side depletion layer should be able to be significantly reduced. Therefore, since the total depletion layer charge can be reduced,
It is considered that the capacity of the depletion layer can be reduced. Here, the formula for deriving the S value is represented by the following formula.

[0224]

(Equation 3)

This equation is obtained from the graph shown in FIG.
It shows the reciprocal of the slope of the rising portion (near the gate voltage 0 V) of the g characteristic. Further, the equation represented by Equation 3 can be approximately expressed as the following equation.

[0226]

(Equation 4)

In Equation 4, k is the Boltzmann constant, T is the absolute temperature, q is the electric charge, Cd is the depletion layer capacitance, Cit is the equivalent capacitance of the interface state, and Cox is the gate oxide film capacitance. Therefore, in this configuration, the depletion layer capacitance Cd is sufficiently smaller than in the prior art, so that the S value can be set to a small value of 85 mV / decade or less, that is, an excellent subthreshold characteristic can be obtained.

By setting the depletion layer capacitance Cd and the equivalent capacitance Cit of the interface state as close to 0 as possible, Cd = C
There is a possibility that an ideal state where it = 0, that is, a semiconductor device whose S value is 60 mV / decade can be realized.

By the way, in the present invention, the crystal grain boundaries of the needle-like or columnar crystals are composed of oxides. In the present configuration inferred therefrom, in the present structure, impurity regions other than oxygen are used as impurity regions corresponding to the crystal grain boundaries of the present invention. Alternatively, nitrogen or carbon may be used. This is because the purpose of this configuration is to artificially arrange an energy barrier in the channel formation region.

Therefore, from the viewpoint of forming an energy barrier, it can be said that an effect is obtained even in an impurity region having a conductivity type opposite to the conductivity type of the inversion layer. That is, it can be said that the impurity region may be formed using B ions in the case of an N-channel semiconductor device and P ions in the case of a P-channel H semiconductor device.

When the impurity region is composed of P or B ions, it is possible to directly control the threshold value by the concentration of the impurity ions to be added.

As described above, this configuration is a technology derived by the present inventors based on the configuration and experimental facts of the invention disclosed in this specification. It is presumed that by implementing this configuration, it is possible to effectively suppress the short channel effect which is a problem in a semiconductor device in a deep submicron region having a very short channel length.

[Embodiment 3] In this embodiment, an example will be described in which the crystalline silicon film shown in Embodiment 1 is formed on a silicon wafer. In this case, it is necessary to provide an insulating layer on the surface of the silicon wafer, but usually a thermal oxide film is often used.

The temperature range of the heat treatment is generally from 700 to 1300 ° C., and the treatment time varies depending on the desired oxide film thickness.

The thermal oxidation of a silicon wafer is usually
₂ , O ₂ -H ₂ O, H ₂ O, O ₂ -H ₂ combustion or the like. Also, oxidation in an atmosphere to which a halogen element such as HCl or Cl ₂ is added has been widely put to practical use.

A silicon wafer is one of the bases indispensable for a semiconductor device such as an IC, and a technique for forming various semiconductor elements on the wafer has been developed.

According to this embodiment, a crystalline silicon film having crystallinity comparable to that of a single crystal can be combined with a conventional technique using a silicon wafer to further expand the application range of the crystalline silicon film. .

In addition, TF is mounted on an IC on a silicon wafer.
It is also possible to form an integrated circuit in which semiconductor devices are arranged three-dimensionally by forming T.

[Embodiment 4] In this embodiment, a TFT manufactured by applying the present invention is used for a DRAM (Dynamic Rondom Access).
Memory) will be described. FIG. 13 is used for the description.

The DRAM is a type of memory in which information to be stored is stored as electric charges in a capacitor. The transfer of charge as information to and from the capacitor is controlled by a TFT connected in series to the capacitor. FIG. 13 shows a circuit of a TFT and a capacitor constituting one memory cell of a DRAM.
It is shown in (A).

When a gate signal is supplied by the word line 1301, the TFT denoted by reference numeral 1303 is turned on. In this state, the capacitor 13 is connected from the bit line 1302 side.
The information is read out when the electric charge is charged in 04, or the information is read out by extracting the electric charge from the charged capacitor.

FIG. 13B shows a sectional structure of the DRAM. Reference numeral 1305 denotes a base made of a quartz substrate or a silicon substrate.

A silicon oxide film 1306 is formed as a base film on the substrate 1305, and a TFT to which the present invention is applied is formed thereon. Note that when the base 1305 is a silicon substrate, a thermal oxide film can be used as the base film 1306. Reference numeral 1307 denotes an active layer formed according to the first embodiment.

The active layer 1307 is covered with a gate insulating film 1308, on which a gate electrode 1309 is formed.
Then, after an interlayer insulating film 1310 is laminated thereon,
A source electrode 1311 is formed. This source electrode 13
At the same time as the formation of 11, the electrodes indicated by the bit lines 1302 and 1312 are formed. Reference numeral 1313 denotes a protective film made of an insulating film.

The electrode 1312 maintains a fixed potential, and forms a capacitor 1304 between the electrode 1312 and the drain region of the active layer existing therebelow. That is, the charge stored in the capacitor is written or read by the TFT, thereby having a function as a storage element.

A feature of a DRAM is that the number of elements constituting one memory is very small only by a TFT and a capacitor.
It is suitable for forming a large-scale memory with a high integration density.
It is also the most widely used at present, as the price is kept low.

Further, as a feature of the case where a DRAM cell is formed using a TFT, the storage capacitance can be set small, so that operation at a low voltage can be performed.

[Embodiment 5] In this embodiment, a TFT manufactured by applying the present invention is replaced with an SRAM (Static Rondom Access).
Memory) will be described. FIG. 14 is used for the description.

An SRAM is a memory using a bistable circuit such as a flip-flop as a storage element.
A binary information value (0 or 1) is stored corresponding to the two stable states of N-OFF or OFF-ON. This is advantageous in that the memory is retained as long as power is supplied.

The storage circuit is composed of N-MOS and C-MOS. The SRAM circuit shown in FIG. 14A is a circuit using a high resistance as a passive load element.

Reference numeral 1401 denotes a word line.
1402 is a bit line. Reference numeral 1403 denotes a load element having a high resistance, and an SRAM is constituted by two sets of driver transistors as indicated by 1404 and two sets of access transistors as indicated by 1405.

FIG. 14B shows a cross-sectional structure of the TFT.
A silicon oxide film 1407 is formed as a base film over a base 1406 formed of a quartz substrate or a silicon substrate, and a TFT to which the present invention is applied can be manufactured thereover. 140
Reference numeral 8 denotes an active layer formed according to the first embodiment.

The active layer 1408 is covered with a gate insulating film 1409, on which a gate electrode 1410 is formed.
Then, after an interlayer insulating film 1411 is laminated thereon,
A source electrode 1412 is formed. This source electrode 14
At the same time as the formation of 12, a bit line 1402 and a drain electrode 1413 are formed.

An interlayer insulating film 1414 is again laminated thereon, and then a polysilicon film 1415 is formed as a high resistance load. It is also possible to adopt an SRAM structure in which the same function as a high resistance load is replaced by a TFT. Also,
Reference numeral 1416 denotes a protective film made of an insulating film.

The features of the SRAM having the above configuration are that it can operate at high speed, has high reliability, and is easily incorporated into a system.

[Embodiment 6] In this embodiment, an active matrix electro-optical device in which a pixel matrix circuit and a logic circuit are integrated on the same substrate using the semiconductor device of Embodiment 1 and the CMOS circuit of Embodiment 2 The example which comprises is shown. The electro-optical device includes a liquid crystal display device, an EL display device, an EC display device, and the like.

Note that a logic circuit refers to an integrated circuit for driving an electro-optical device, such as a peripheral drive circuit or a control circuit. In an active matrix type electro-optical device, an external IC is generally used as a logic circuit due to a limitation of operation performance and a problem of integration degree. Can be realized.

The control circuit includes a processor circuit, a memory circuit, a clock generation circuit, an A / D (D / A)
It includes all electric circuits necessary for driving an electro-optical device such as a converter circuit. Of course, the memory circuit includes the SRAM circuit and the DRAM circuit described in the fifth and sixth embodiments.

When the invention disclosed in this specification is used for such a structure, a logic circuit can be formed with TFTs having performance comparable to that of a MOSFET formed on a single crystal.

[Embodiment 7] In this embodiment, an example of manufacturing a TFT having a structure different from that of the embodiment 1 will be described. FIG. 15 is used for the description.

First, the same steps as those in the first embodiment are performed, and FIG.
The state shown in FIG. When the state shown in FIG. 2A is obtained, the resist mask (not shown) used for patterning the aluminum film is removed, and thereafter, anodizing treatment is performed in tartaric acid to obtain a dense anodic oxide film having a thickness of 1000 mm. .
This state is shown in FIG.

In FIG. 15A, 101 is a quartz substrate, 102 is a base film, 110 is an island-like semiconductor layer, and 111 is a thermal oxide film which functions later as a gate insulating film. Reference numeral 1501 denotes a gate electrode made of a material containing aluminum as a main component, and reference numeral 1502 denotes a dense anodic oxide film obtained by anodizing the gate electrode 1501.

Next, in this state, impurity ions for imparting one conductivity to the island-shaped semiconductor layer 110 are implanted.
Then, the impurity region 150 is formed by this ion implantation process.
3, 1504 are formed.

This impurity ion is an N channel type T
P (phosphorus) or As (arsenic) may be used for FT, and B (boron) may be used for P-channel TFT.
At this time, the dose is set to a low value of 0.1 to 5 × 10 ¹⁴ atoms / cm ² , preferably 0.2 to 1 × 10 ¹⁴ atoms / cm ² .

When the implantation of the impurity ions is completed, a silicon nitride film 1505 is formed to a thickness of 0.5 to 1 μm. The film formation method may be any one of a low pressure thermal CVD method, a plasma CVD method, and a sputtering method. Further, a silicon oxide film may be used instead of the silicon nitride film.

Thus, the state shown in FIG. 15B is obtained.
After the state of FIG. 15B is obtained, the silicon nitride film 15
05 is etched by an etch-back method, and is left only on the side wall of the gate electrode 1501. The silicon nitride film thus left functions as a sidewall 1506.

At this time, the thermal oxide film 111 is removed except for the region where the gate electrode is used as a mask, and remains in a state as shown in FIG.

In the state shown in FIG. 15C, impurity ions are implanted again. At this time, the dose is 0.2 to 10 × 10 ¹⁵
atoms / cm ² , preferably 1 to 2 × 10 ¹⁵ atoms / cm ^2, which is higher than the dose amount of the ion implantation.

At the time of this ion implantation, the side wall 15
Since the regions 1507 and 1508 just below 06 are not subjected to ion implantation, there is no change in the impurity ion concentration. However, the exposed regions 1509 and 1510 are implanted with a higher concentration of impurity ions.

As described above, through the second ion implantation, low concentration impurity regions (LDD regions) 1507 and 1508 having lower impurity concentrations than the source region 1509, the drain region 1510, and the source / drain regions are formed. Note that an area immediately below the gate electrode 1501 is an undoped region, which becomes a channel formation region 1511.

When the state shown in FIG. 15C is obtained through the above steps, a titanium film (not shown) having a thickness of 300 mm is formed, and the titanium film and the silicon (crystalline silicon) film are reacted. Then, after the titanium film is removed, a heat treatment such as lamp annealing is performed to form titanium silicide 151 on the surfaces of the source region 1509 and the drain region 1510.
2, 1513 are formed. (FIG. 15D)

In the above process, a tantalum film, a tungsten film, a molybdenum film, or the like can be used instead of the titanium film. In FIG. 15D, a part of the source / drain region is described as being silicided. However, depending on the thickness of the source / drain region or the condition of the heat treatment, the entire source / drain region may be silicided. It may be silicidated.

Next, a silicon oxide film is formed to a thickness of 5000 ° as an interlayer insulating film 1514, and a source electrode 1515 and a drain electrode 1516 are formed. Thus, a TFT having a structure shown in FIG. 15D is completed.

The TFT having the structure shown in this embodiment has a source /
Since the drain electrode is connected to the source / drain region via the titanium silicides 1512 and 1513, a good ohmic contact can be realized.

[Embodiment 8] In this embodiment, an example of manufacturing a TFT having a structure different from that of the embodiment 1 or the embodiment 7 will be described. FIG. 16 is used for the description.

First, through the same steps as in the first embodiment, FIG.
The state shown in FIG. However, in this embodiment, a crystalline silicon film having conductivity is used as a material of the gate electrode. This state is shown in FIG.

In FIG. 16A, 101 is a quartz substrate, 102 is a base film, 110 is an island-shaped semiconductor layer, and 111 is a thermal oxide film which functions later as a gate insulating film. Reference numeral 1601 denotes a gate electrode made of a crystalline silicon film (polysilicon film).

Next, in this state, impurity ions for imparting one conductivity to the island-shaped semiconductor layer 110 are implanted.
Then, the impurity region 160 is formed by this ion implantation process.
2, 1603 are formed. (FIG. 16 (B))

This impurity ion is an N channel type T
P (phosphorus) or As (arsenic) may be used for FT, and B (boron) may be used for P-channel TFT.
At this time, the dose is set to a low value of 0.1 to 5 × 10 ¹⁴ atoms / cm ² , preferably 0.2 to 1 × 10 ¹⁴ atoms / cm ² .

After the implantation of the impurity ions is completed, the sidewalls 16 are etched using the etch-back method as in the seventh embodiment.
04 is formed.

After forming sidewalls 1604, impurity ions are implanted again. At this time, the dose is
0.2 to 10 × 10 ¹⁵ atoms / cm ² , preferably 1 to 2 × 10 ¹⁵ ato
The dose is set to ms / cm ^2, which is higher than the dose amount of the ion implantation. (FIG. 16 (C))

At the time of this ion implantation, the side wall 16
Since the regions 1605 and 1606 just below the region 04 are not subjected to ion implantation, there is no change in the impurity ion concentration. However, the exposed regions 1607 and 1608 are further implanted with a higher concentration of impurity ions.

As described above, through the second ion implantation, the low concentration impurity regions (LDD regions) 1605 and 1606 having an impurity concentration lower than those of the source region 1607, the drain region 1608, and the source / drain regions are formed. Note that an area immediately below the gate electrode 1601 is an undoped region, which becomes a channel formation region 1609.

When the state shown in FIG. 16C is obtained through the above steps, a tungsten film (not shown) having a thickness of 500 ° is formed, and the tungsten film and the silicon film are reacted.
Then, after the tungsten film is removed, a heat treatment such as lamp annealing is performed, so that the gate electrode 1601,
Tungsten silicides 1610 to 1612 are formed on the surfaces of the source region 1607 and the drain region 1608. (FIG. 16 (D))

Of course, in addition to the tungsten film, a titanium film,
A molybdenum film or a tantalum film can be used. Further, in this embodiment, the time of the heat treatment is set longer so that the entire source / drain region is adjusted to be silicided.

Next, a silicon nitride film is formed to a thickness of 4000 ° as an interlayer insulating film 1613, and a source electrode 1614 and a drain electrode 1615 are formed. Thus, the TFT having the structure shown in FIG. 16D is completed.

In the TFT having the structure shown in this embodiment, a good ohmic contact can be realized because the gate electrode and the source / drain electrode are connected to the extraction electrode via the tungsten silicides 1610 to 1612.

[Embodiment 9] In this embodiment, an example of an electro-optical device (display device) incorporating a semiconductor device utilizing the present invention will be described. The electro-optical device may be used as a direct-view type or a projection type as needed. Further, an electro-optical device is also considered to be a device that functions using a semiconductor; therefore, an electro-optical device in this specification is included in the category of a semiconductor device.

Examples of applied products of the semiconductor device using the present invention include a TV camera, a head mounted display, a car navigation, a projection (a front type and a rear type), a video camera, a personal computer, and the like. A simple example of these applications will be described with reference to FIG.

FIG. 17A shows a TV camera, and the main body 3
001, a camera unit 3002, a display device 3003, and operation switches 3004. The display device 3003 is used as a viewfinder.

FIG. 17B shows a head-mounted display, which comprises a main body 3101, a display device 3102, and a band section 3103. Two display devices 3102 having relatively small sizes are used.

FIG. 17C shows a car navigation system, which includes a main body 3201, a display device 3202, and an operation switch 3.
203 and an antenna 3204. Display device 32
02 is used as a monitor, but since the main purpose is to display a map, it can be said that the allowable range of resolution is relatively wide.

FIG. 17D shows a portable information terminal device (mobile phone in this embodiment), which includes a main body 3301 and an audio output unit 3.
302, a voice input unit 3303, a display device 3304, operation buttons 3305, and an antenna 3306. It is expected that the display device 3303 will be required to display a moving image as a TV phone in the future.

FIG. 17E shows a video camera, which comprises a main body 3401, a display device 3402, an eyepiece 3403, operation switches 3404, and a tape holder 3405. Since a captured image projected on the display device 3402 can be viewed in real time through the eyepiece 3403, the user can capture an image while viewing the image.

FIG. 17D shows a front projection, which includes a main body 3501, a light source 3502, a reflective display device 3503, an optical system (including a beam splitter and a polarizer) 3504, and a screen 3505.
Since the screen 3505 is a large screen used for presentations such as conferences and conference presentations, the display device 3503 requires a high resolution.

In addition to the electro-optical device shown in this embodiment, a rear projection, a mobile computer,
It can be applied to portable information terminal devices such as handy terminals. As described above, the application range of the present invention is extremely wide, and it can be applied to display media in all fields.

Further, the TFT of the present invention is not limited to an electro-optical device, but may be incorporated in an integrated circuit in the form of, for example, an SRAM or a DRAM, and used as a drive circuit for an applied product as shown in this embodiment. .

[0298]

According to the invention disclosed in this specification, it is possible to realize a TFT having high performance comparable to a MOSFET manufactured on single crystal silicon. In addition, the ring oscillator constituted by the TFT of the present invention is a conventional TFT.
20 times faster operation than the ring oscillator constituted by

Further, despite having such high characteristics, it has extremely high withstand voltage characteristics even in a fine region having a channel length of 1 μm or less, and the short channel effect is effectively suppressed. Can be confirmed.

By applying an integrated circuit using the above-described TFT to the electro-optical device, it is possible to further improve the performance of the electro-optical device. Also, applied products to which the electro-optical device is applied can have high performance and high added value.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a semiconductor device.

FIG. 2 illustrates a manufacturing process of a semiconductor device.

FIG. 3 is a diagram showing an arrangement configuration of an island-shaped semiconductor layer.

FIG. 4 illustrates characteristics of a semiconductor device.

FIG. 5 is a view showing a semiconductor device manufacturing process.

FIG. 6 illustrates a manufacturing process of a semiconductor device.

FIG. 7 is a photograph showing a configuration of an electric circuit.

FIG. 8 is a diagram showing a configuration of an active layer.

FIG. 9 is a photograph showing the surface of a crystalline silicon film.

FIG. 10 is a photograph showing a crystal structure.

FIG. 11 is a photograph showing a crystal structure.

FIG. 12 is a photograph showing a crystal structure.

FIG. 13 is a diagram showing a configuration of a DRAM;

FIG. 14 is a diagram showing a configuration of an SRAM.

FIG. 15 illustrates a manufacturing process of a semiconductor device.

FIG. 16 illustrates a manufacturing process of a semiconductor device.

FIG. 17 illustrates an application example of a semiconductor device.

[Explanation of symbols]

 Reference Signs List 101 quartz substrate 102 base film 103 amorphous silicon film 104 silicon oxide film (mask insulating film) 105 region where amorphous silicon film is exposed 106 nickel-containing water film 107 crystalline silicon film 108 indicates the direction of crystallization Arrow 109 nickel-added region 110 island-shaped semiconductor layer 111 thermal oxide film 112 aluminum film pattern 113 porous anodic oxide film 114 dense anodic oxide film 115 gate electrode 116, 117 impurity region 118, 119 low-concentration impurity region 120 channel Formation region 121 interlayer insulating film 122 source electrode 123 drain electrode 301 quartz substrate 302 nickel-added region 303 macroscopic crystal grain boundary 304 island-like semiconductor layer 801 source region 802 drain region 803 channel formation region 804 impurity region 805 carriers move Grain boundary area 1001 needle-like or columnar crystals

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 12, 1996

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Fig. 7

[Correction method] Change

[Correction contents]

FIG. 7 is a micrograph showing the configuration of an electric circuit.

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Kenji Fukunaga 398 Hase, Atsugi-shi, Kanagawa Semiconductor Energy Laboratory Co., Ltd.

Claims (21)

[Claims] 1. A method of manufacturing a semiconductor device having an active layer comprising a semiconductor thin film, comprising: forming an amorphous silicon film on a substrate having an insulating surface; and selectively forming an amorphous silicon film on the amorphous silicon film. A step of forming a mask insulating film; a step of selectively holding a metal element that promotes crystallization in the amorphous silicon film; and at least a part of the amorphous silicon film by a first heat treatment. Transforming a crystalline silicon film into a crystalline silicon film; removing the mask insulating film; forming an island-like semiconductor layer composed of only the crystalline silicon film by patterning as a later active layer; Performing a second heat treatment in an atmosphere containing an element to remove the metal element in the island-like semiconductor layer by gettering and forming a gate insulating film made of a thermal oxide film. Has the active layer is a method for manufacturing a semiconductor device, characterized in that said substrate substantially parallel acicular or columnar crystals are formed by a plurality sets. 2. A method for fabricating a semiconductor device having an active layer comprising a semiconductor thin film, comprising: forming an amorphous silicon film on a substrate having an insulating surface; and selectively forming an amorphous silicon film on the amorphous silicon film. A step of forming a mask insulating film; a step of selectively holding a metal element that promotes crystallization in the amorphous silicon film; and at least a part of the amorphous silicon film by a first heat treatment. Transforming a crystalline silicon film into a crystalline silicon film; removing the mask insulating film; forming an island-like semiconductor layer composed of only the crystalline silicon film by patterning as a later active layer; A step of performing gettering removal of the metal element in the island-shaped semiconductor layer by performing a second heat treatment in an atmosphere containing the element; and removing a thermal oxide film formed by the second heat treatment. And a step of forming a thermal oxide film functioning as a gate insulating film on the surface of the island-like semiconductor layer by performing a third heat treatment, wherein the active layer is a needle substantially parallel to the base. A method for manufacturing a semiconductor device, comprising forming a plurality of aggregated or columnar crystals. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the amorphous silicon film is formed by a low pressure thermal CVD method. 4. The method of claim 1, wherein Fe, Co, Ni, Ru, R
A method for manufacturing a semiconductor device, wherein one or more elements selected from h, Pd, Os, Ir, Pt, Cu, and Au are used. 5. The method according to claim 1, wherein the atmosphere containing a halogen element is HCl, HF, H
Br, Cl ₂ , ClF ₃ , BCl ₃ , NF ₃ , F ₂ , B
A method for manufacturing a semiconductor device, wherein one or more kinds of gases selected from compounds containing r ₂ are added. 6. The method according to claim 1, wherein the first heat treatment is performed in a temperature range of 450 to 700 ° C., and the second or third heat treatment is performed in a temperature range exceeding 700 ° C. A method for manufacturing a semiconductor device, comprising: 7. An insulating gate having at least an active layer made of a crystalline silicon film formed on the base, a gate insulating film formed on the surface of the active layer, and a gate electrode on the gate insulating film. -Type semiconductor device, wherein a metal element for promoting crystallization is 1 × 10 ^{18 in the} active layer.
exists at an average concentration of atoms / cm ³ or less, and the standard deviation of the S value representing the electrical characteristics of the semiconductor device is within 10 mV / dec for the N-channel type and / or
A semiconductor device characterized by being within 15 mV / dec. 8. An insulating gate having at least an active layer made of a crystalline silicon film formed on the base, a gate insulating film formed on the surface of the active layer, and a gate electrode on the gate insulating film. -Type semiconductor device, wherein a metal element for promoting crystallization is 1 × 10 ^{18 in the} active layer.
exists in an average concentration of atoms / cm ³ or less, and the S value representing the electrical characteristics of the semiconductor device is an N-channel type.
Within 80 ± 30mV / dec and / or 80 ± 45 for P-channel type
A semiconductor device characterized by being within mV / dec. 9. A structure having at least an active layer made of a crystalline silicon film formed on the base, a gate insulating film formed on the surface of the active layer, and a gate electrode on the gate insulating film. In the active layer, a metal element that promotes crystallization is 1 × 10 ¹⁸
An insulated gate semiconductor device that is present at an average concentration of atoms / cm ³ or less and has a standard deviation of an S value representing electric characteristics within 10 mV / dec for an N-channel type and / or within 15 mV / dec for a P-channel type A semiconductor device comprising: 10. A structure having at least an active layer made of a crystalline silicon film formed on the base, a gate insulating film formed on the surface of the active layer, and a gate electrode on the gate insulating film. In the active layer, a metal element that promotes crystallization is 1 × 10 ¹⁸
An insulated gate semiconductor that exists at an average concentration of atoms / cm ³ or less and has an S value representing electric characteristics within 80 ± 30 mV / dec for an N-channel type and / or within 80 ± 45 mV / dec for a P-channel type A semiconductor device comprising a device. 11. The semiconductor device according to claim 7, wherein at least a film surface of said gate insulating film in contact with said active layer is a thermal oxide film. 12. A step of forming an amorphous silicon film on a substrate having an insulating surface; a step of selectively forming a mask insulating film on the amorphous silicon film; Selectively holding a metal element that promotes crystallization with respect to: a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by a first heat treatment; A step of forming an island-shaped semiconductor layer composed only of the crystalline silicon film by patterning as an active layer later, and performing a second heat treatment in an atmosphere containing a halogen element. A step of removing the metal element in the island-shaped semiconductor layer by gettering and forming a gate insulating film made of a thermal oxide film; and forming the active layer in a needle shape or a column shape substantially parallel to the base. Wherein a the crystal is formed by a plurality sets. 13. A step of forming an amorphous silicon film on a substrate having an insulating surface; a step of selectively forming a mask insulating film on the amorphous silicon film; Selectively holding a metal element that promotes crystallization with respect to: a step of transforming at least a part of the amorphous silicon film into a crystalline silicon film by a first heat treatment; A step of forming an island-shaped semiconductor layer composed only of the crystalline silicon film by patterning as an active layer later, and performing a second heat treatment in an atmosphere containing a halogen element. A step of gettering and removing the metal element in the island-shaped semiconductor layer, a step of removing a thermal oxide film formed by the second heat treatment, and a step of performing a third heat treatment on the island-shaped semiconductor On the layer surface A step of forming a thermal oxide film functioning as a site insulating film, wherein the active layer is formed by collecting a plurality of needle-like or columnar crystals substantially parallel to the base. apparatus. 14. The method according to claim 12, wherein
A semiconductor device, wherein the first heat treatment is performed in a temperature range of 450 to 700 ° C, and the second or third heat treatment is performed in a temperature range exceeding 700 ° C. 15. The method according to claim 12, wherein
In the active layer, a metal element that promotes crystallization is 1 × 10 ¹⁸
An insulated gate semiconductor device that is present at an average concentration of atoms / cm ³ or less and has a standard deviation of an S value representing electric characteristics within 10 mV / dec for an N-channel type and / or within 15 mV / dec for a P-channel type A semiconductor device comprising: 16. The method according to claim 12, wherein
In the active layer, a metal element that promotes crystallization is 1 × 10 ¹⁸
An insulated gate semiconductor that exists at an average concentration of atoms / cm ³ or less and has an S value representing electric characteristics within 80 ± 30 mV / dec for an N-channel type and / or within 80 ± 45 mV / dec for a P-channel type A semiconductor device comprising a device. 17. The method according to claim 7, wherein the control information is stored in the storage device.
17. The semiconductor device according to claim 5, wherein a length of the channel formation region in the active layer is 0.01 to 2 [mu] m. 18. The semiconductor device according to claim 7, wherein one or more elements selected from Cl, F, and Br are contained in the active layer at a concentration of 1 × 10 ¹⁵ to 1 × 10 ²⁰ atoms / cm ³ . A semiconductor device characterized by being present at a concentration. 19. The semiconductor device according to claim 7, wherein the active layer contains one or more kinds of elements selected from Cl, F, and Br, and the elements include the active layer and the gate insulating film. A semiconductor device which is distributed at a high concentration at an interface with the semiconductor device. 20. Claims 7 to 10 or 1
14. The method according to claim 12, wherein the metal element promoting crystallization is Fe, Co, Ni, Ru, Rh, Pd, or O.
A semiconductor device, which is one or more elements selected from s, Ir, Pt, Cu, and Au. 21. Claim 7 to Claim 10 or Claim 1
14. The semiconductor device according to claim 2, wherein the crystalline silicon film is obtained by crystallizing an amorphous silicon film formed by a low pressure thermal CVD method.