JP2004247747A - Semiconductor device, method of manufacturing the same, liquid crystal display device, electroluminescence display device, erectrochromic display device, tv, personal computer, car-navigation system, camera, and video camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique by which a thin semiconductor film having the crystallinity corresponding to single crystals can be formed by using the other method than the SOI (silicon-on-impurity) technique, because, when an enhancement TFT is manufactured by using the SOI technique, such a demerit occurs that the number of ion implanting steps increases due to the necessity of injecting impurities into channel regions and, in addition, high-performance semiconductor device having excellent electrical characteristics can be formed by utilizing the thin semiconductor film. <P>SOLUTION: The semiconductor device has a crystalline silicon film having a film thickness of 10-85 nm, an oxide film formed on the silicon film, and a thin film transistor formed on the oxide film and having a gate electrode. The semiconductor device also has an S-value of ≤60-85 mV/dec. The crystalline silicon film is formed by introducing a metallic element which promotes the crystallization of silicon into an amorphous silicon film and crystallizing the amorphous silicon film by performing first heat treatment on the film. Then a thermally oxidized film is formed on the surface of the crystalline silicon film by performing second heat treatment in an oxidizing atmosphere containing chlorine. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The invention disclosed in this specification relates to a semiconductor thin film formed on a substrate having an insulating surface and a semiconductor device formed using the semiconductor thin film. In particular, the present invention relates to a crystalline silicon film as a semiconductor thin film.

A thin film transistor (TFT) is typically known as the semiconductor device, and the thin film transistor can constitute a liquid crystal display device, an EL device, an EC device, and the like.

  A technique of forming an active layer of a TFT on a single crystal silicon film by using the SOI technique is known, but the thickness of the single crystal is required to be 1 μm or more due to the problem of uniformity and controllability. Was. The energy band gap (hereinafter, simply referred to as Eg) of a silicon film formed by using such an SOI technique is approximately 1.1 eV, which is almost equal to the bulk Eg of a single crystal silicon film.

  Here, for example, as shown in FIG. 2A, the active layer of the TFT using the SOI technique has a conductive layer (N-type layer 201 or P-type layer 202) and an I layer (intrinsic semiconductor layer) 203 forming a channel. Consider the case of At this time, the band at the junction is bent to match the Fermi level indicated by the broken line, and a band difference occurs between the I layer 203 and the conductive layers 201 and 202.

  In this case, since the energy band difference between the conductive layers 201 and 202 and the I layer 203 is small, for example, about 0.5 eV, the movement of carriers does not occur even when no voltage is applied to the gate electrode (when there is no electric field). Relatively easy to do.

  That is, in a graph in which the horizontal axis shows the gate voltage (Vg) and the vertical axis shows the current (Id) flowing between the source and the drain, the Id-Vg characteristic 204 of the N-channel TFT is negative, and the P-channel TFT is negative. The threshold value of the Id-Vg characteristic 205 of the TFT is shifted to the plus side and is in a normally-on state.

  When the electrical characteristics of the TFT are in a normally-on state, the TFT is a so-called depression type TFT. Such a depletion type TFT is characterized in that the TFT is always on. Conversely, a type in which a TFT is always in an off state, that is, a normally-off type, is called an enhancement type TFT. However, for the above-mentioned reason, when an attempt is made to form a channel formation region of an SOI structure with an intrinsic semiconductor, a depletion type TFT is inevitably formed.

  Therefore, in order to manufacture an enhancement type TFT, as shown in FIG. 2B, if the conductive layer is an N-type layer 206, the P-type is used. Impurities to be provided have been implanted into the channel region 208 to perform threshold control.

  As a result, as shown in FIG. 2B, the energy band difference between the conductive layers 206 and 207 and the I layer 208 is widened, for example, to about 0.7 eV, and can be a sufficient barrier for carrier movement. . That is, the threshold value of the Id-Vg characteristic 209 of the N-channel TFT is shifted to the positive side, and the threshold value of the Id-Vg characteristic 210 of the P-channel TFT is shifted to the negative side, so that the TFT can be in a normally-off state.

  As described above, when fabricating an enhancement-type TFT using the SOI technology, it is necessary to implant impurities into the channel region, so that some disadvantages such as an increase in the number of ion implantation steps are unavoidable at present. Was.

  Further, it is known that when the thickness of the active layer is large, the characteristics of the TFT are easily deteriorated due to a punch-through phenomenon, a short channel effect, and the like. It has been reported that it is effective to reduce the thickness of the active layer in order to solve this problem. However, it is necessary to reduce the thickness to about 50 nm or less. Was extremely difficult to achieve.

  An object of the invention disclosed in this specification is to form a semiconductor thin film having crystallinity comparable to a single crystal by a method other than the SOI technique, and to solve the above problems. Another object is to provide a technique for forming a high-performance semiconductor device having excellent electric characteristics using the semiconductor thin film.

  The structure of the invention disclosed in this specification is a semiconductor thin film formed over an insulating substrate, wherein the semiconductor thin film is a silicon film having a region substantially regarded as a single crystal, The energy band gap is 1.3 to 1.9 eV at room temperature. The thickness of the silicon film is in the range of 10 to 85 nm.

  An active layer formed by using a semiconductor thin film as described above has excellent performance that can solve the problems of the SOI technology as described in the conventional example. The reason will be described below.

  First, a crystalline silicon film (crystalline silicon film) having a structure as shown in the present invention can be formed as a thin film having a thickness of 10 to 85 nm. In order to obtain a crystalline silicon film, an amorphous silicon film may be crystallized, or a crystalline silicon film may be formed directly on a substrate.

  According to the present invention, a region that can be substantially regarded as a single crystal can be formed in a silicon thin film having a thickness of 10 to 85 nm. Can be reduced.

  Note that a region that can be substantially regarded as a single crystal means that there is no barrier that hinders the movement of carriers in that region. In other words, it can be rephrased that there is substantially no grain boundary.

  A notable feature of the present invention is that it focuses on the energy band gap (Eg) of the silicon film. The fact that the Eg is 1.3 to 1.9 eV (preferably 1.4 to 1.7 eV) at room temperature (10 to 30 ° C.) has the following advantages.

  As shown in FIG. 1A, the active layer of a TFT according to the present invention is composed of a conductive layer (N-type layer 101 or P-type layer 102) and an I layer (intrinsic semiconductor layer) 103 forming a channel. think of. However, unlike the conventional example shown in FIG. 2, it is assumed that the Eg of the silicon film is between 1.3 and 1.9 eV, for example, 1.4 eV.

  In this case, the energy band difference between the conductive layers 101 and 102 and the I layer 103 is, for example, about 0.7 eV, which is larger than when the SOI technology described in the conventional example is used. Is not moved.

  That is, it is possible to realize a TFT in which a normally-off state is ensured even when a region where a channel is formed is an I layer (intrinsic semiconductor layer). According to the findings of the present inventors, such an effect can be obtained if Eg is 1.3 eV or more, preferably 1.4 eV or more.

  Here, the energy band gap (Eg) is determined by measuring the optical absorption spectrum to determine the light wavelength dependence of the effective transmittance of the silicon film, and determining the value of the light wavelength at the absorption edge at which the effective transmittance starts to decrease. Is converted into an energy value using an equation represented by E = hc / λ.

  Another embodiment of the present invention is a semiconductor device formed over an insulating substrate, wherein a semiconductor thin film forming an active layer of the semiconductor device is a silicon film having a region substantially regarded as a single crystal. The energy band gap of the silicon film is 1.3 to 1.9 eV at room temperature.

  The schematic structure of such a semiconductor device is as shown in FIG. It is noted that the detailed description of the structure of the semiconductor device is given to the embodiment, and the thickness of the active layer is in the range of 10 to 85 nm. Of course, it is possible to form a film with a larger thickness, but it is preferable to suppress the film thickness to 50 nm or less.

  This active layer has a structure in which an I layer 106 serving as a channel formation region is sandwiched between an N-type layer or P-type layers 104 and 105 serving as source / drain regions. The semiconductor device according to the present invention is formed by forming a silicon film having crystallinity comparable to that of a single crystal with a thickness of 10 to 85 nm to form an active layer, and thus has a feature of extremely excellent electric characteristics. .

  In addition, since the energy band gap (Eg) of the I layer 106 serving as a channel formation region is 1.3 to 1.9 eV, which is larger than that of a single crystal silicon film, a threshold value which is a problem when using the SOI technology. A normally-off thin film transistor can be formed without performing control.

The effects of the present invention include:
(1) The active layer can be formed of a silicon film having a thin film thickness of 10 to 85 nm and having a region substantially regarded as a single crystal.
(2) When Eg is 1.3 to 1.9 eV, preferably 1.4 to 1.7 eV, good normally-off characteristics can be realized even when the intrinsic semiconductor layer is used as a channel formation region. That is, an enhancement type TFT can be easily manufactured.

  The effects described above show that the present invention is an industrially useful technology that can overcome the problems of the conventional SOI technology. In addition, it can be said that the experimental data shown in FIGS. 6 and 10 remarkably prove the above effect.

  The present invention having the above-described configuration will be described in detail with embodiments described below.

  In this embodiment, formation of a semiconductor thin film having crystallinity comparable to that of a single crystal and its physical properties will be described. Specifically, the knowledge obtained by the present inventors regarding a crystalline silicon film having excellent crystallinity will be described.

  The present inventors have already disclosed the technique described in JP-A-6-64834 as a method for forming a semiconductor thin film having crystallinity comparable to that of a single crystal. The method of this embodiment is to add another value to the technique by adding a relatively high temperature thermal oxidation step to the technique to further improve the crystallinity.

  First, a process of forming a semiconductor thin film will be described with reference to FIG. In FIG. 3A, reference numeral 301 denotes a substrate having an insulating surface. However, it is preferable to use a quartz substrate or the like having excellent heat resistance in consideration of a heating step in a subsequent crystallization step. A silicon oxide film is formed as a base film 302 on the quartz substrate 301.

  Next, an amorphous silicon film 303 is formed to a thickness of 100 nm by a low pressure thermal CVD method. Since the film thickness is reduced in the subsequent thermal oxidation step, it is preferable that the thickness be larger than a desired film thickness in consideration of the calculation.

  Thus, the state shown in FIG. 3A is obtained. When the state shown in FIG. 3A is obtained, the amorphous silicon film is crystallized by a heat treatment, a laser annealing treatment, or a combination of both.

  In this embodiment, crystallization is performed by using the technique described in JP-A-6-232059 or JP-A-7-321339 by the present inventors. In these techniques, a heat treatment is performed for 1 to 24 hours, typically 4 to 12 hours in a temperature range of 500 to 700 ° C., typically 600 to 650 ° C. while holding a metal element (for example, nickel element). By doing so, a silicon film having excellent crystallinity is obtained.

  First, in the state shown in FIG. 3A, the surface of the amorphous silicon film 303 is irradiated with UV light to form a thin oxide film (not shown). The purpose of this oxide film is to improve the wettability of the film surface when a nickel salt solution is applied later.

  Then, a nickel acetate solution adjusted to contain 10 ppm by weight of nickel element is dropped on an oxide film (not shown), and a thin nickel-containing layer 304 is formed by spin coating. (FIG. 3 (B))

  When the state shown in FIG. 3B is obtained, heat treatment is performed to crystallize the amorphous silicon film 303, so that a crystalline silicon film 305 is obtained. In this embodiment, the temperature of this heat treatment is 600 ° C., and the treatment time is 4 hours. (FIG. 3 (C))

  The crystalline silicon film 305 thus obtained has excellent crystallinity as compared with the case where the technique described in the above publication is not used. According to the findings of the present inventors, it is possible to further improve the crystallinity by performing laser annealing after crystallization by heat treatment.

  However, in the present invention, a heat treatment step at a relatively high temperature is performed as a means for further improving the crystallinity. Specifically, thermal oxidation treatment is performed at 800 to 1000 ° C., preferably 950 ° C. for 30 minutes in an oxidizing atmosphere containing 3% of chlorine with respect to oxygen.

  The crystalline silicon film 306 thus formed has large individual crystal grains, and the crystal grains have extremely excellent crystallinity. The crystallinity is substantially equivalent to that of a single crystal, and the present inventors call this region a monodomain region. Although not shown, a thermal oxide film having a thickness of 50 nm is formed on the surface of the crystalline silicon film 306. (FIG. 3 (D))

The following effects can be expected as effects of the thermal oxidation treatment on the crystalline silicon film 305.
(1) Removal of metal elements (nickel, etc.) existing in the film or on the film surface (2) Improvement of crystallinity by removing crystal defects and the like (3) Thinning of silicon film

  (1) is due to the gettering effect of chlorine contained in the heating atmosphere, and contributes to removal of crystal defects such as lattice distortion and dislocation caused by the presence of a metal element. The reason (2) is due to the rearrangement of silicon (silicon) atoms caused by the heat treatment at a relatively high temperature, thereby improving the matching between lattices. (3) is an effect that contributes to various advantages (such as suppression of a short channel effect) due to the thinning of the silicon film.

  The present inventors have examined the crystalline silicon film obtained as described above, and have found the following facts.

  The graph shown in FIG. 4 shows experimental data when measuring the optical absorption spectrum of the crystalline silicon film obtained through the formation process shown in this example. In FIG. 4, the horizontal axis is the light wavelength in the normal visible light range, and the vertical axis is the effective transmittance (calculated by excluding the reflected light component on the film surface), which is the ratio of the light intensity before and after passing through the film. Transmittance). The thickness of the silicon film was measured in two types, 40 nm and 60 nm.

  The present inventors consider that there is an energy loss corresponding to the energy band gap (Eg) of the silicon film when light passes through the silicon film, and light in a wavelength region having no energy equal to or higher than Eg is emitted from the silicon film. Could not be transmitted, and as a result, the transmittance was estimated to be small. In other words, it is expected that the light in the wavelength region where the transmittance starts to decrease has the energy equivalent to the Eg of the silicon film.

  In FIG. 3, the transmittance starts to decrease in a region where the light wavelength is about 800 nm or less, and when Eg is obtained from the wavelength of 800 nm, it is about 1.5 eV. This calculation was obtained from Einstein's photon energy equation, Eg = hc / λ (h: Planck constant, c: speed of light, λ: light wavelength).

  That is, the crystalline silicon film formed according to this embodiment has an Eg of about 1.5 eV, and it is considered that only light in a wavelength region having energy of more than that can be easily transmitted.

  As described above, a point to which attention is paid to Eg of the crystalline silicon film which can be substantially regarded as a single crystal is a remarkable feature of the present invention. In the case of Eg = 1.3 eV (as described above, a normally-off TFT can be realized even if the thickness of the active layer is small as described above), when the light wavelength is obtained from the above photon energy equation, it is about 950 nm. is there. Therefore, the present inventors have defined that the present invention is effective in the above-mentioned light wavelength range of 800 nm ± 150 nm, and set the upper limit of Eg of the present invention to 1.9 eV (corresponding to a light wavelength of 650 nm).

  In other words, the crystalline silicon film of the present invention can be regarded substantially as a single crystal, but its Eg is larger than Eg (= 1.1 eV) of the single crystal silicon film, specifically, 1.3 to 1.9 eV. It can be said that it is different from a single crystal in a certain point. Further, in order to reliably realize normally-off and to minimize the threshold value, it is preferable that the voltage is preferably 1.4 to 1.7 eV.

  Therefore, a silicon film having a structure as shown in the present invention is more effective than a conventional SOI technology in obtaining a silicon film having crystallinity comparable to that of a single crystal on an insulating substrate. It can be said that it greatly contributes.

  In this embodiment, a semiconductor thin film having crystallinity comparable to that of a single crystal is formed by the means shown in Embodiment 1, and a process of forming a thin film transistor using the semiconductor thin film as an active layer will be described with reference to FIGS. In this embodiment, only an example of the formation process is shown, and the structure and numerical values are not limited to this embodiment.

First, an insulating film with a thickness of 200 nm is formed as a base film 502 over a substrate 501 having an insulating property. In this embodiment, a quartz substrate is used as the substrate 501, and silicon oxide (SiO ₂ ), silicon oxynitride (SiO _X N _Y ), silicon nitride (SiN), or the like is used as an insulating film by a plasma CVD method, a low pressure thermal CVD method, or a sputtering method. The film is formed by a method or the like.

  A crystalline silicon film 503 having a region (monodomain region) substantially regarded as a single crystal is formed on the base film 502 according to the means of the first embodiment. Since this forming method has been described in detail in the first embodiment, the description is omitted here. Thus, the state shown in FIG. 5A is obtained.

  Incidentally, what is indicated by 504 is a 50 nm thick thermal oxide film formed by thermal oxidation at 950 ° C. for 30 minutes. Therefore, at this time, the thickness of the silicon film 503 is reduced by the thickness of the thermal oxide film 504 (about 25 nm).

  Next, after removing the thermal oxide film 504, the crystalline silicon film 503 is patterned to form an island-shaped semiconductor layer (not shown) which becomes a prototype of an active layer later. After the island-shaped semiconductor layer is formed, another heat treatment (thermal oxidation step) is performed in an oxidizing atmosphere containing chlorine. This condition is the same as the condition in the first embodiment.

  By this heat treatment, a thermal oxide film 505 having a thickness of 50 nm, which functions as a gate insulating film later, is formed on the surface of the island-shaped semiconductor layer (not shown). At the same time, the active layer 506 is defined. The thickness of the active layer 506 is reduced by the two thermal oxidation steps performed so far, and the final thickness is 50 nm.

  In this embodiment, only this thermal oxide film 505 is used as a gate insulating film. However, another insulating film such as a silicon oxide film or a silicon nitride film is further stacked thereon to form a gate insulating film. It is also possible.

Alternatively, a gate insulating film made of a silicon oxide film or a silicon nitride film may be first formed to cover the active layer 506, and then heat treatment may be performed in an oxidizing atmosphere containing chlorine. In this case, thermal oxidation is performed on the surface of the active layer below the gate insulating film, which is effective in that an extremely good Si / SiO ₂ interface can be formed. Of course, an effect of improving the quality of the gate insulating film can also be expected.

  Next, a conductive film (not shown) is formed to a thickness of 200 to 250 nm. In this embodiment, an aluminum film containing 0.2 wt% of scandium is used. Scandium has the effect of suppressing protrusions such as hillocks and whiskers generated on the aluminum surface during heat treatment or the like.

  In this state, anodization of the aluminum film is performed in an electrolytic solution. As the electrolytic solution, a solution prepared by neutralizing a 3% ethylene glycol solution of tartaric acid with aqueous ammonia to adjust the pH to 6.92 is used. The treatment is performed using platinum as a cathode with a formation current of 5 mA and an ultimate voltage of 10 V.

  The thin and dense anodic oxide film (not shown) formed in this manner has an effect of increasing the adhesion to the photoresist when the aluminum film (not shown) is patterned later. Further, the film thickness can be controlled by controlling the voltage application time.

  Next, an aluminum film (not shown) is patterned to form an aluminum film pattern 507 serving as a prototype of the gate electrode. Thus, the state shown in FIG. 5B is obtained.

  Next, as shown in FIG. 5C, a second anodic oxidation is performed to form a porous anodic oxide film 508. The electrolytic solution is a 3% oxalic acid aqueous solution, and the treatment is performed using platinum as a cathode at a formation current of 2 to 3 mA and a reaching voltage of 8 V. At this time, since a resist mask (not shown) used for patterning exists on the pattern 507, the anodic oxidation proceeds in a direction parallel to the substrate. The length of the porous anodic oxide film 508 can be controlled by controlling the voltage application time.

  Furthermore, after removing the photoresist (not shown) used for patterning the aluminum film with a dedicated stripper, a third anodic oxidation is performed. For this anodic oxidation, a solution prepared by neutralizing a 3% tartaric acid solution of ethylene glycol with aqueous ammonia to adjust the pH to 6.92 is used. Then, the treatment is carried out using platinum as a cathode at a formation current of 5 to 6 mA and an ultimate voltage of 40 to 100 V.

  The anodic oxide film 509 formed at this time is very dense and strong. Therefore, the gate electrode 510 has an effect of protecting the gate electrode 510 from damage and heat generated in a later process such as a doping process. Further, the film thickness becomes 50 to 150 nm. Thus, the state shown in FIG. 5C is obtained.

  Next, an impurity is implanted into the active layer 506 by an ion doping method. For example, if an N-channel TFT is manufactured, P (phosphorus) ions may be implanted as impurities, and if a P-channel TFT is manufactured, B (boron) ions may be implanted as impurities.

  At this time, the ion implantation is performed twice. First, the first ion implantation is performed in a state shown in FIG. In this ion implantation step, the porous anodic oxide film 508 and the like serve as a mask, and regions 511 and 512 which will later become the source / drain are formed in a self-aligned manner.

  Further, the porous anodic oxide film 508 is removed, and the second doping is performed. In this ion implantation step, the gate electrode 510 serves as a mask, and low-concentration impurity regions 513 and 514 having a lower impurity concentration than the source region 511 and the drain region 512 are formed in a self-aligned manner. In addition, since no impurity is implanted immediately below the gate electrode 307, the channel formation region 515 is formed in a self-aligned manner.

  The low-concentration impurity region 514 thus formed is particularly called an LDD region, and has an effect of suppressing formation of a high electric field between the channel region 515 and the drain region 512. Strictly, an offset region is formed between the channel formation region 515 and the low-concentration impurity regions 513 and 514 by the thickness of the dense anodic oxide film 509, but the width is 100 nm or less. Time does not work practically.

Then, irradiation with a KrF excimer laser at an energy density of 200 to 300 mJ / cm ² activates the implanted impurity ions. The activation may be performed by thermal annealing at 300 to 450 ° C. for 2 hours, or laser annealing and thermal annealing may be used in combination.

  Through the implantation and activation of the impurity ions as described above, the state shown in FIG. 5D is obtained. Next, an interlayer insulating film 516 is formed by a plasma CVD method. As the interlayer insulating film 516, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like can be used. Further, the film thickness may be 0.5 to 1.0 μm.

  Alternatively, an organic resin material represented by polyimide can be used for the interlayer insulating film 516. Such an organic resin material is easy to form a film, can easily increase the film thickness, and can reduce unevenness due to device shape to realize an excellent flat surface.

  After forming the first interlayer insulating film 516, contact holes are formed in the source region 511 and the drain region 512, and an aluminum film (not shown) is formed to a thickness of 300 nm. Next, a source electrode 517 and a drain electrode 518 are formed by patterning an aluminum film (not shown).

  Finally, heat treatment is performed at 350 ° C. for about 1 hour in a hydrogen atmosphere, and hydrogen termination of dangling bonds is performed to hydrogenate the semiconductor device. Thus, a semiconductor device having a structure as shown in FIG.

  In the semiconductor device shown in FIG. 5E as shown in the present invention, the active layer is substantially composed of a single crystal silicon film, and the Eg is 1.3 to 1.9 eV or more and the single crystal silicon film has Since it is larger than the bulk Eg, it has a very excellent switching function. Further, since the film thickness is extremely thin, that is, 10 to 85 nm, deterioration such as punch-through and short channel effect can be suppressed.

  FIG. 6 shows electrical characteristics of the semiconductor device shown in FIG. 5E manufactured by the present inventors according to this embodiment. FIG. 6A shows the electric characteristics (Id-Vg characteristics) of an N-channel TFT, and FIG. 6B shows the electric characteristics of a P-channel TFT. Note that VG on the horizontal axis is a gate voltage value, and ID on the vertical axis is a current value flowing between the source and the drain. Further, the Id-Vg curves 601 and 603 show the characteristics when the drain voltage VD = 1V, and the Id-Vg curves 602 and 604 show the characteristics when the drain voltage VD = 5V.

  First, it should be noted that the threshold value shift is extremely small. The regions indicated by 605 and 606 are the rising portions of the current value ID. In the N-channel TFT, both the curves 601 and 602 rise at VG = about -0.5V. This indicates that almost no current flows when the gate voltage VG = 0 V, and the device is in a normally-off state.

  Similarly, in the region indicated by 606, in the P-channel type TFT, both curves 603 and 604 rise at VG = 0 to -0.5V. That is, it is clear that the device is in the normally-off state.

Here, Table 1 shows typical characteristic parameters of the thin film transistor obtained from the electric characteristics shown in FIGS. 6A and 6B. Note that the parameter value is represented by an average value of the 40-point measurement, and the variation is shown using the standard deviation σ. In Table 1, L / W = 8/8 μm indicates the channel length L and channel width W, and T _OX = 56 nm indicates that the thickness of the active layer is 56 nm.

  The data shown in Table 1 is measured data when VD = 1 V, and the off-state current (Ioff) is extremely small at 0.03 pA for N-type and 1.65 pA for P-type. A small off-state current suggests that the function as a switching element is excellent and that power consumption is small. Further, the threshold value (Vth) is as small as -0.25 V for the N type and -1.36 V for the P type, and it can be seen that it is normally off without any problem.

Further, it has been clarified that the semiconductor device according to the present invention has an active layer substantially composed of a single crystal in terms of a subthreshold value (S value) and a field effect mobility (μFE). The S value is 80 mV / dec for both N-type and P-type, and μFE is 200 cm ² / Vs for N-type and 160 cm ² / Vs for P-type. These values are evidence that the thin film transistor according to the present invention has extremely excellent characteristics, and it can be said that the effect of the present invention is remarkably exhibited.

  Actually, there is a TFT having a characteristic that is almost the same as that of single crystal silicon having an S value of about 60 mV / dec. Having an extremely excellent S value is also one of the characteristics of the semiconductor thin film having the structure of the present invention, and it can be said that the semiconductor thin film has a characteristic that the S value is 85 mV / dec or less, preferably 75 mV / dec or less.

  The present inventors have realized a highly accurate measurement by changing the gate voltage VG in the range of -3 V to 3 V when measuring the Id-Vg curve, and reducing the step width of changing the gate voltage. ing. This will be described using the aforementioned S value as an example.

  FIGS. 16A to 16D show the case where the step width of the gate voltage VG is varied by four conditions for the N-channel TFT and FIGS. 16E to 16H for the P-channel TFT. 5 is an Id-Vg curve (electrical characteristics) of the sample.

  Referring to FIG. 16A, the step width was 0.5 V, and the S value obtained by the calculation at that time was 139 mV / dec. At this time, the Id-Vg curve has a linear shape because the step width is rough. When the VG step width is reduced to 0.25 V (FIG. 16B), 0.1 V (FIG. 16C), and 0.05 V (FIG. 16D), Id−Vg The curve also becomes smooth, and the S value tends to decrease. Finally, as shown in FIG. 16D, when the step width is 0.05 V, the S value is reduced to 83 mV.

  The same applies to the P-channel type TFT, and the S value becomes 162 mV / dec and 84 mV by reducing the step width in FIGS. 16 (E), (F), (G) and (H). / Dec, 76 mV / dec, and 74 mV / dec.

  As described above, accurate measurement can be performed by reducing the VG step width, and the electrical characteristics in this specification are shown by experimental results obtained by such a highly accurate measurement method. .

  One of the features of the present invention is that the S value obtained by the above-described highly accurate measurement is 85 mV / dec or less. This value is very close to the value normally obtained when a single crystal silicon film is used (about 60 mV / dec), and it can be seen that the crystallinity of the silicon film having the structure shown in the present invention is extremely good.

  The reason for this will be described below. Note that this consideration is an attempt to explain the above-mentioned reason by using a formula obtained by analyzing a semiconductor property of a single crystal silicon film assuming that the silicon film shown in the present invention is a single crystal. Therefore, it is considered that the logic development described below cannot be applied to ordinary polysilicon or amorphous silicon.

First, the intrinsic carrier density ni in the channel formation region becomes ni = (NcNv) ^1/2 e- ^{Eg /} 2kT according to the law of mass action. Nc is the effective state density of the conduction band, Nv is the effective state density of the valence band, Eg is the energy band gap, k is the Boltzmann constant, and T is the absolute temperature.

  From this equation, it can be seen that the intrinsic carrier density ni decreases as Eg increases. Since the silicon film having the structure of the present invention has a characteristic of Eg of 1.3 to 1.9 eV while being substantially single crystal, the intrinsic carrier density ni tends to be smaller than that of the single crystal. Can be

The width Xd of the depletion layer formed upon applying a gate _{voltage, Xd = (2ε S ε 0} φ S / qni) represented by ^1/2. ε _S is the relative dielectric constant of silicon, ε ₀ is the dielectric constant of vacuum, φ _S is the surface potential of silicon, and q is the charge of the carrier. When φ _S reaches a certain value, the width of the depletion layer does not increase any more. Considering this point, it is understood from the above equation that the width Xd of the depletion layer increases as the intrinsic carrier density ni decreases.

This means that the capacitance Cd of the depletion layer is reduced, which is apparent from the fact that the capacitance Cd of the depletion layer is obtained by Cd = ε _S ε ₀ / Xd. It has been found that the depletion layer capacitance Cd is one of the parameters that greatly affects the S value.

In general, the S value is defined by the amount of change in Vg required to change Id by one digit in the aforementioned Id-Vg curve. Then, the value is represented by ln10 · kT / q [1+ (Cd + Cit) / C _0X ]. Here, Cit is the equivalent capacitance of the interface state, and C _0X is the gate capacitance. Note that the semiconductor device of this embodiment realizes a Si / SiO ₂ interface with extremely good matching by using a thermal oxide film as a gate insulating film (the interface state is extremely small). Can be ignored.

From this equation, it is understood that assuming that C _0x = constant, the S value decreases as the depletion layer capacitance Cd decreases. Therefore, in a state where the depletion layer capacitance Cd is reduced to a negligible level, that is, in a state where Cd = 0 can be considered, the S value takes a minimum value, and this state is an S value in an ideal state of single crystal silicon (ideal S value). Is believed to be.

  Actually, it is said that the ideal S value of single crystal silicon is about 60 mV / dec. Although the S value of the semiconductor device shown in this embodiment falls within a range of approximately 60 to 85 mV / dec, sometimes it becomes 60 mV / dec or less. This phenomenon is a fact that has been frequently reported even when SOI technology is used.

  With respect to this fact, the present inventors considered as follows. According to the above theoretical development, it is considered that the S value decreases as the energy band gap Eg increases (provided that it can be regarded as a single crystal). However, actually, the value of the semiconductor device shown in this embodiment is larger than the ideal S value.

  This is considered to be due to the fact that the thickness of the active layer of the semiconductor device of this example is as thin as 50 nm. This is because the width Xd of the depletion layer increases as the gate voltage is applied, but when the width exceeds 50 nm, the thickness is limited and the depletion layer does not further expand. That is, since the depletion layer capacitance Cd cannot be reduced any further, the S value is also limited there.

  As presumed as described above, one explanation may be given as to why the thin film transistor having extremely excellent electric characteristics as shown in FIG. 6 and Table 1 could be manufactured in the structure shown in the present invention. become.

In the above theoretical development, the gate capacitance C _0X = constant and the depletion layer capacitance Cd is associated with the S value. However, the gate capacitance C _0X actually varies depending on the thickness T _0X of the gate insulating film. Then, the present inventors simulated the relationship between the depletion layer capacitance Cd and the S value under the three conditions of the thickness T _0X of the gate insulating film of 10, 25, and 50 nm.

In the calculation equation of the above S-value, considering that Cit = 0, a S = ln10 · kT / q ( 1 + Cd / C 0X), Cd = because it is ln10 · kT / q = 0.06 at room temperature 300K ( the S / 0.06-1) C _0X.

Here, when the gate capacitance C _0X is calculated under three conditions where the thickness T _0X of the gate insulating film is 10, 25, and 50 nm, ε _r = 3.8 at C _0X = ε _r ε ₀ S / T _0X . , Ε ₀ = 8.85 × 10 ⁻¹⁴ (F / cm), S = 6.4 × 10 ⁻⁷ (cm ² ) (calculated assuming that the area of the channel region is L / W = 8/8 μm). Is obtained.
When T _0X = 10 nm: C _0X = 3.36 × 10 ⁻⁷ (F / cm ² )
When T _0X = 25 nm: C _0X = 1.35 × 10 ⁻⁷ (F / cm ² )
When T _0X = 50 nm: C _0X = 6.73 × 10 ⁻⁸ (F / cm ² )

Here in the previous formula Cd = (S / 0.06-1) C 0X, when the Cd when the T _0X = 10 nm and Cd, _10, S Substituting C _0X as S _10,
Cd, ₁₀ = 5.60 × 10 ⁻⁶ · S ₁₀ −3.36 × 10 ⁻⁷ (F / cm ² )
Is obtained. Similarly, depletion layer capacitance Cd, _25, Cd, ₅₀ when the T _0X = 25,50nm is
Cd, ₂₅ = 2.25 × 10 ^-6 · S ₂₅ -1.35 × 10 ^-7 (F / cm ² )
Cd, ₅₀ = 1.12 × 10 ⁻⁶ .S ₅₀ −6.73 × 10 ⁻⁸ (F / cm ² )
It is calculated by the following equation.

  Based on these equations, the horizontal axis represents the S value and the vertical axis represents the depletion layer capacitance Cd, and FIG. 17 shows the result of simulating the value of Cd for an arbitrary S value. It can be seen that when the depletion layer capacitance Cd = 0, the S value is an ideal S value (= 0.06 V / dec).

Also, from FIG. 17, it can be confirmed that the depletion layer capacitance Cd tends to increase as the thickness T _0X of the gate insulating film _decreases . It is also assumed that the film having a _larger T _0X has a smaller slope of the straight line, that is, is more sensitive to a change in Cd. Therefore, in the present invention, it is presumed that the S value is improved by suppressing Cd to be small. Therefore, it is preferable that the thickness of the gate insulating film be at least 50 nm or more.

  As described in the second embodiment, the semiconductor device according to the present invention has a small S value and a high mobility, and thus is very effective in forming a circuit requiring high-speed operation. For example, in an active matrix display device including a pixel matrix circuit and a peripheral driving circuit on the same substrate, a shift register or the like provided in the peripheral driving circuit requires high-speed operation.

  Such a drive circuit is usually constituted by a CMOS circuit in which an N-channel TFT and a P-channel TFT are complementarily combined. Therefore, this embodiment shows an example in which a CMOS structure is formed using the TFT shown in the second embodiment. 7 to 9 show a manufacturing process of this embodiment. The application range of the crystalline silicon film formed according to the present invention is wide, and the method of forming the CMOS structure is not limited to this embodiment.

  First, a silicon oxide film 702 is formed on a glass substrate 701 according to the structure shown in Embodiment 1, and a crystalline silicon film having a monodomain region is obtained thereon. By patterning them, an active layer 703 of an N-channel TFT and an active layer 704 of a P-channel TFT composed of only a monodomain region are obtained.

  After the formation of the active layers 703 and 704, a thermal oxidation process is performed as described in the second embodiment to form a thermal oxide film 705 functioning as a gate insulating film. Although the thickness can be controlled by the processing temperature and the processing time of the thermal oxidation step, in this embodiment, it is set to 50 nm as in the first and second embodiments.

  Thus, the state shown in FIG. 7A is obtained. After the state shown in FIG. 7A is obtained, an aluminum film 706 that will form a gate electrode later is formed as shown in FIG. 7B. This aluminum film contains scandium at 0.2 wt% in order to suppress generation of hillocks and whiskers. The aluminum film is formed by a sputtering method or an electron beam evaporation method.

  Hillocks and whiskers are bar-like or needle-like protrusions caused by abnormal growth of aluminum. The presence of hillocks or whiskers causes a short circuit or crosstalk between adjacent wirings or between wirings separated vertically.

  Anodizable metals such as tantalum and molybdenum can be used as materials other than the aluminum film. Further, instead of the aluminum film, a silicon film provided with conductivity can be used.

  After the formation of the aluminum film 706, anodic oxidation is performed in an electrolytic solution using the aluminum film 706 as an anode to form a thin and dense anodic oxide film 707. The conditions for forming this anodic oxidation may be according to the second embodiment. (FIG. 7 (B))

  Next, resist masks 708 and 709 are formed. The aluminum film 706 is patterned by using the resist masks 708 and 709 to form aluminum film patterns 710 and 711 serving as gate electrode prototypes. Thus, the state shown in FIG. 7C is obtained.

  Next, porous anodic oxide films 712 and 713 are formed on the side surfaces of the aluminum film patterns 710 and 711 under the same conditions as in the second embodiment. In this embodiment, the thickness of the porous anodic oxide films 712 and 713 is set to 0.7 μm. Thus, the state shown in FIG. 7D is obtained.

  Next, dense and strong anodic oxide films 714 and 715 are formed under the same conditions as in the second embodiment. However, in this embodiment, the attained voltage is adjusted so that the film thickness becomes 70 nm. In addition, gate electrodes 71 and 72 are defined by this process. The structure is as shown in FIG.

Next, in the state shown in FIG. 7E, P (phosphorus) ions are doped over the entire surface as an impurity imparting N-type. This doping is performed at a high dose of 0.2 to 5 × 10 ¹⁵ / cm ² , preferably 1 to 2 × 10 ¹⁵ / cm ² . As a doping method, a plasma doping method or an ion doping method is used.

  As a result of the step shown in FIG. 7E, regions 716 to 719 in which P ions are implanted at a high concentration are formed. These regions will later function as source / drain regions. (FIG. 7E)

  Next, the porous anodic oxide films 712 and 713 are removed using a mixed acid solution in which acetic acid, nitric acid, and phosphoric acid are mixed. At this time, the active layer region located immediately below the anodic oxide films 712 and 713 is substantially intrinsic since no ions are implanted.

Next, a resist mask 720 is formed so as to cover an element forming a P-channel thin film transistor on the right side. Thus, the state shown in FIG. When the state shown in FIG. 8A is obtained, P ions are implanted again as shown in FIG. The dose of this P ion is set to a low value of 0.1 to 5 × 10 ¹⁴ / cm ² , preferably 0.3 to 1 × 10 ¹⁴ / cm ² .

  That is, the dose of the P ions implanted in the step shown in FIG. 8B is lower than that in the step shown in FIG. Then, as a result of this step, the regions 722 and 724 become lightly doped low concentration impurity regions. The regions 721 and 725 are high-concentration impurity regions into which P ions are implanted at a higher concentration.

  In this step, the region 721 becomes a source region of the N-channel thin film transistor. 722 and 724 are low concentration impurity regions, and 725 is a drain region. The region denoted by 723 is a substantially intrinsic channel forming region. The region indicated by 724 is a region generally called an LDD (lightly doped drain) region.

  Although not particularly shown, a region whose ion implantation is blocked by the anodic oxide film 714 exists between the channel formation region 723 and the low-concentration impurity regions 722 and 724. This region is called an offset gate region and has a distance corresponding to the thickness of the anodic oxide film 714.

  Although the offset gate region is substantially intrinsic without being ion-implanted, it does not form a channel because no gate voltage is applied, and functions as a resistance component that relaxes electric field intensity and suppresses deterioration. However, if the distance (offset width) is short, it does not function as an effective offset area. In this embodiment, since the width is 70 nm, it does not function as an offset region.

Next, the resist mask 720 is removed, and a resist mask 726 covering the left N-channel thin film transistor is formed as illustrated in FIG. Then, in the state shown in FIG. 8C, B (boron) ions are implanted as impurities imparting P-type. Here, the dose of B ions is set to 0.2 to 10 × 10 ¹⁵ / cm ² , preferably, to about 1 to 2 × 10 ¹⁵ / cm ² . This dose can be approximately the same as the dose in the step shown in FIG.

  By this step, the high-concentration impurity regions 718 and 719 are inverted from N-type to P-type to form a source region 727 and a drain region 728 of the P-channel TFT. Further, a channel formation region 729 is formed immediately below the gate electrode 72.

  Next, after the step illustrated in FIG. 8C is completed, the resist mask 726 is removed to obtain a state illustrated in FIG. In this state, laser light irradiation is performed to activate the implanted impurities and anneal the region into which the impurity ions have been implanted.

  When the state shown in FIG. 8D is obtained, an interlayer insulating film 730 is formed to a thickness of 400 nm as shown in FIG. The interlayer insulating film 730 may be any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, and may have a multilayer structure. As a method for forming these silicide films, a plasma CVD method or a thermal CVD method may be used.

  Next, a contact hole is formed, and a source electrode 731 of an N-channel thin film transistor (NTFT) and a source electrode 732 of a P-channel thin film transistor (PTFT) are formed. Further, a CMOS structure is realized by using a configuration in which the drain electrode 733 is shared by the N-channel TFT and the P-channel TFT. (FIG. 8 (B))

  Through the above process, a CMOS circuit having the structure illustrated in FIG. 8B can be manufactured. A closed circuit formed by connecting an odd number of CMOS circuits in series is called a ring oscillator, and is used when evaluating the operation speed of a semiconductor device.

  Here, FIG. 10 shows the result of configuring a ring oscillator with a CMOS circuit manufactured according to the present embodiment and examining the oscillation frequency of the ring oscillator. The measurement was performed using a ring oscillator to which 9, 19, and 51 sets (stages) of CMOS circuits were connected, and the relationship between the power supply voltage and the oscillation frequency was obtained.

  According to FIG. 10, for example, a power supply voltage of 10 (V), a 19-stage ring oscillator realizes an oscillation frequency of 62.6 MHz, and it can be seen that the operation speed is extremely high. FIG. 11 shows the measurement results of the ring oscillator formed of the CMOS circuit manufactured in Example 3 without including the thermal oxidation step (single crystallization step). However, the operation was not confirmed when the power supply voltage was lower than 6 (V), so the description was omitted.

  In FIG. 11, for example, a power supply voltage of 10 (V), a 19-stage ring oscillator has an oscillation frequency of 6.5 MHz, and a CMOS circuit having the configuration of the present invention is compared with a low-temperature polysilicon TFT manufactured under general conditions. It has been found that the operating speed is about 10 times.

  It is certain that such a result is one of the major factors because the S value is extremely small as described in the third embodiment. Therefore, when configuring a circuit capable of high-speed operation as described in the present embodiment, the S value of the circuit TFT needs to be 85 mV / dec or less, preferably 75 mV / dec or less.

  The anodic oxidation process described in Examples 1 to 3 is a liquid phase treatment in which a substrate (anode) on which wiring is formed and a platinum electrode (cathode) are immersed in an electrolytic solution. The outline of the apparatus is as shown in FIG.

  In FIG. 12A, the inside of a thermostat 1201 is filled with an electrolytic solution 1202. As the electrolytic solution 1202, a 3% oxalic acid aqueous solution is used to form a porous anodic oxide, and a 3% tartaric acid ethylene glycol solution is used to form a dense anodic oxide.

  Then, a substrate to be processed 1203 serving as an anode and a platinum electrode 1204 serving as a cathode are immersed in the electrolytic solution 1202, and connection wires drawn from respective terminals are connected to a potentiometer 1205. The potentiometer 1205 is a control device for keeping current and voltage constant.

  When an electrochemical circuit is formed in a state as shown in FIG. 12A, first, a constant current process is performed, and between the substrate 1203 and the platinum electrode 1204 (more precisely, the wiring on the substrate 1203, the electrolytic solution, When the voltage of (2) reaches the attained voltage, constant voltage processing is performed while maintaining the voltage as it is. At this time, a current flows in a direction indicated by an arrow in the drawing, and the wiring on the substrate is supplied with the current and anodized.

  As another oxide formation method, a plasma oxidation method is known. However, the plasma oxidation method has no problem in forming an oxide near the surface of the wiring to be processed, but is not suitable for the purpose of transforming the wiring itself into an oxide as in the present invention. However, when an oxide is formed on the surface of the wiring for the purpose of protecting the wiring, the same effect as the above-described anodic oxidation can be obtained. FIG. 12B illustrates an example of a device configuration in the case where a plasma oxidation method is used.

  In FIG. 12B, a first electrode 1207 and a second electrode 1208 facing each other are provided in a grounded processing chamber 1206. The substrate 1209 is held by a first electrode 1207, and the first electrode 1207 is grounded. The second electrode 1208 is connected to an AC power supply 1211 via a blocking capacitor 1210, so that an AC voltage is applied.

  Reference numeral 1212 denotes an inlet for the plasma excitation gas, and reference numeral 1213 denotes an outlet for discharging the excitation gas out of the processing chamber 1206, which is connected to a vacuum pump (not shown). It is to be noted that a so-called ECR mode plasma device can be formed by providing a magnet or the like in the present device to form a magnetic field.

  In the plasma device illustrated in FIG. 12B, a gas containing oxygen as a plasma excitation gas is introduced into the treatment chamber 1206 from the introduction port 1212, and an AC voltage is applied to the second electrode 1208. Then, plasma 1214 is generated between the first electrode 1207 and the second electrode 1208. Then, the wiring formed on the substrate 1209 is oxidized by oxygen plasma, and an oxide containing the same substance as the wiring material in its composition is formed on the surface thereof.

  As described above, the oxide formed for the purpose of protecting the wiring can be obtained not only by the liquid phase anodic oxidation method but also by the plasma oxidation method.

  Embodiments 1 to 3 show an example in which a planar type TFT is formed as a thin film transistor to which the present invention is applied. However, in some cases, another type of TFT, for example, an inverted staggered type having a structure as shown in FIG. The present invention can be implemented using a TFT.

  The details of the manufacturing process of the inverted staggered TFT are described in JP-A-5-275452 and the like, and may be manufactured by a known technique. Therefore, in this embodiment, a detailed description is omitted, only the structure is shown in FIG. 13, and only the configuration of the active layer 1301 is mentioned.

  In the case where it is necessary to perform the heat treatment in the temperature range of 700 to 1000 ° C., typically 950 ° C. as described in Embodiment 2, an inverted staggered TFT in which a gate electrode 1302 is formed before the formation of the active layer 1301 Application to is impossible.

  Therefore, when applied to an inverted staggered TFT as in this embodiment, the active layer 1301 may be formed using a crystalline silicon film crystallized by the technique described in Japanese Patent Application Laid-Open No. 6-64834. According to the technique described in the publication, it is possible to form a silicon film having a monodomain region at a temperature lower than the heat resistance of the gate electrode 1301.

  In this embodiment, an example in which an electro-optical device is formed using a semiconductor device having the structure of the present invention will be described. Examples of the electro-optical device include a liquid crystal display device, an EL (electroluminescence) display device, and an EC (electrochromics) display device.

  For example, an active matrix liquid crystal display device having a structure in which a pixel matrix circuit and a peripheral driver circuit are integrated on the same substrate can have a structure as shown in FIG. Note that the integrated circuit illustrated in FIG. 14 is an SOG (system-on-glass) type display device including a control circuit such as a memory circuit or a CPU circuit in addition to the pixel matrix circuit and the peripheral driver circuit.

  In FIG. 14, reference numeral 1401 denotes a pixel matrix circuit in which hundreds of hundreds of thousands of TFTs are usually arranged in a matrix to control the voltage applied to the liquid crystal. Reference numeral 1402 denotes a vertical scanning driving circuit, and 1403 denotes a horizontal scanning driving circuit. These drive circuits include a shift register circuit, a buffer circuit, a sampling circuit, and the like, and control a gate signal and a video signal. Reference numeral 1404 denotes a control circuit, which includes a CPU circuit, a memory circuit, and the like.

  The most characteristic of the semiconductor device having the structure of the present invention is that the semiconductor device is extremely excellent in high-speed operation. It can be said that it is most preferable to dispose it at a place where high-speed operation is required.

  Further, as an applied product of an active type display device such as a liquid crystal display device as shown in FIG. 14 and other EL display devices and EC display devices, TV cameras, personal computers, car navigation systems, and TV projectors ( TV), a video camera and the like. A brief description of these applications will be given with reference to FIG.

  FIG. 15A illustrates a TV camera, which includes a main body 2001, a camera unit 2002, a display device 2003, and operation switches 2004. The display device 2003 is used as a viewfinder.

  FIG. 15B illustrates a personal computer, which includes a main body 2101, a cover portion 2102, a keyboard 2103, and a display device 2104. The display device 2104 is used as a monitor, and requires a size as large as ten and several inches diagonal.

  FIG. 15C illustrates a car navigation system, which includes a main body 2201, a display device 2202, operation switches 2203, and an antenna 2204. Although the display device 2202 is used as a monitor, it can be said that the allowable range of resolution is relatively wide because the main purpose is to display a map.

  FIG. 15D illustrates a TV projector, which includes a main body 2301, a light source 2302, a display device 2303, mirrors 2304 and 2305, and a screen 2306. Since the image projected on the display device 2303 is projected on the screen 2306, the display device 2303 requires a high resolution.

  FIG. 15E illustrates a video camera, which includes a main body 2401, a display device 2402, an eyepiece 2403, operation switches 2404, and a tape holder 2405. Since a captured image projected on the display device 2402 can be viewed in real time through the eyepiece 2403, the user can capture an image while viewing the image.

  As described above, the application range of the present invention is extremely wide, and the present invention can be applied to various manufactured products having a semiconductor circuit.

FIG. 3 is a diagram illustrating a configuration of the present invention. FIG. 4 is a diagram illustrating a band state of a conventional active layer. The figure which shows the formation process of a semiconductor thin film. The figure which shows the result of a transmittance measurement. 4A to 4C illustrate a manufacturing process of a thin film transistor. FIG. 4 illustrates electric characteristics of a thin film transistor. 4A to 4C illustrate a manufacturing process of a thin film transistor. 4A to 4C illustrate a manufacturing process of a thin film transistor. 4A to 4C illustrate a manufacturing process of a thin film transistor. The figure which shows the measurement result of a ring oscillator. The figure which shows the measurement result of a ring oscillator. The figure which shows the structure of an anodic oxidation apparatus and a plasma oxidation apparatus. FIG. 3 is a diagram showing a structure of an inverted staggered TFT. FIG. 3 illustrates a structure of an active matrix liquid crystal display device. FIG. 9 illustrates an application example of an electro-optical device. FIG. 4 illustrates electric characteristics of a thin film transistor. The figure which shows the relationship between depletion layer capacity and S value.

Claims (23)

A thin film transistor including a crystalline silicon film having a thickness of 10 to 85 nm, an oxide film over the crystalline silicon film, and a gate electrode over the oxide film;
The semiconductor device according to claim 1, wherein an S value of the thin film transistor is 60 to 85 mV / dec or less. A crystalline silicon film having a thickness of 10 to 85 nm, an oxide film on the crystalline silicon film, a silicon oxide film or a silicon nitride film on the oxide film, and a gate electrode on the silicon oxide film or the silicon nitride film And a thin film transistor having
The semiconductor device according to claim 1, wherein an S value of the thin film transistor is 60 to 85 mV / dec or less. A thin film transistor including a crystalline silicon film having a thickness of 10 to 85 nm, a thermal oxide film on the crystalline silicon film, and a gate electrode on the thermal oxide film;
The semiconductor device according to claim 1, wherein an S value of the thin film transistor is 60 to 85 mV / dec or less. A crystalline silicon film having a thickness of 10 to 85 nm, a thermal oxide film on the crystalline silicon film, a silicon oxide film or a silicon nitride film on the thermal oxide film, and a film on the silicon oxide film or the silicon nitride film. A thin film transistor having a gate electrode;
The semiconductor device according to claim 1, wherein an S value of the thin film transistor is 60 to 85 mV / dec or less. An N-channel thin film transistor and a P-channel thin film transistor each including a crystalline silicon film having a thickness of 10 to 85 nm, an oxide film over the crystalline silicon film, and a gate electrode over the oxide film;
A semiconductor device, wherein the S value of the N-channel thin film transistor and the P-channel thin film transistor is 60 to 85 mV / dec or less. An N-channel thin film transistor and a P-channel thin film transistor each including a crystalline silicon film having a thickness of 10 to 85 nm, a thermal oxide film on the crystalline silicon film, and a gate electrode on the thermal oxide film ,
A semiconductor device, wherein the S value of the N-channel thin film transistor and the P-channel thin film transistor is 60 to 85 mV / dec or less.     7. The semiconductor device according to claim 5, wherein the gate electrode is made of aluminum, tantalum, molybdenum, or a silicon film having conductivity.     7. The semiconductor device according to claim 1, wherein the crystalline silicon film has a region that can be substantially regarded as a single crystal.     The semiconductor device according to claim 1, wherein the crystalline silicon film has a monodomain region.     A liquid crystal display device using the semiconductor device according to claim 1.     An electroluminescent display device using the semiconductor device according to claim 1.     An electrochromic display device using the semiconductor device according to claim 1.     A TV using the semiconductor device according to claim 1.     A personal computer using the semiconductor device according to claim 1.     A car navigation system using the semiconductor device according to claim 1.     A camera using the semiconductor device according to claim 1.     A video camera using the semiconductor device according to claim 1. Introducing a metal element that promotes crystallization of silicon into the amorphous silicon film,
Performing a first heat treatment to crystallize the amorphous silicon film to form a crystalline silicon film;
A method for manufacturing a semiconductor device, comprising: performing a second heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on a surface of the crystalline silicon film. Introducing a metal element that promotes crystallization of silicon into the amorphous silicon film,
Performing a first heat treatment to crystallize the amorphous silicon film to form a crystalline silicon film;
Performing a second heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on the surface of the crystalline silicon film;
Removing the thermal oxide film,
A method for manufacturing a semiconductor device, comprising forming an island-shaped crystalline silicon film by patterning the crystalline silicon film. Introducing a metal element that promotes crystallization of silicon into the amorphous silicon film,
Performing a first heat treatment to crystallize the amorphous silicon film to form a crystalline silicon film;
Performing a second heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on the surface of the crystalline silicon film;
Removing the thermal oxide film,
Patterning the crystalline silicon film to form an island-shaped crystalline silicon film;
A method for manufacturing a semiconductor device, comprising: performing a third heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on a surface of the island-shaped crystalline silicon film. Introducing a metal element that promotes crystallization of silicon into the amorphous silicon film,
Performing a first heat treatment to crystallize the amorphous silicon film to form a crystalline silicon film;
Performing a second heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on the surface of the crystalline silicon film;
Removing the thermal oxide film,
Patterning the crystalline silicon film to form an island-shaped crystalline silicon film;
Performing a third heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on the surface of the island-shaped crystalline silicon film;
A method for manufacturing a semiconductor device, comprising forming a silicon oxide film or a silicon nitride film on the thermal oxide film. Introducing a metal element that promotes crystallization of silicon into the amorphous silicon film,
Performing a first heat treatment to crystallize the amorphous silicon film to form a crystalline silicon film;
Performing a second heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on the surface of the crystalline silicon film;
Removing the thermal oxide film,
Patterning the crystalline silicon film to form an island-shaped crystalline silicon film;
Forming a silicon oxide film or a silicon nitride film on the island-shaped crystalline silicon film;
A method for manufacturing a semiconductor device, wherein a third heat treatment is performed in an oxidizing atmosphere containing chlorine to form a thermal oxide film. Introducing a metal element that promotes crystallization of silicon into the amorphous silicon film,
Performing a first heat treatment to crystallize the amorphous silicon film to form a crystalline silicon film;
Performing a second heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on the surface of the crystalline silicon film;
Removing the thermal oxide film,
Patterning the crystalline silicon film to form a first island-like crystalline silicon film and a second island-like crystalline silicon film;
Performing a third heat treatment in an oxidizing atmosphere containing chlorine to form a thermal oxide film on the surface of the first island-shaped crystalline silicon film and the surface of the second island-shaped crystalline silicon film; ,
Forming a gate electrode made of aluminum, tantalum, molybdenum or a silicon film having conductivity on the thermal oxide film;
The first island-shaped crystalline silicon film is used for an active layer of an N-channel thin film transistor,
The method for manufacturing a semiconductor device, wherein the second island-shaped crystalline silicon film is used for an active layer of a P-channel thin film transistor.