JP3923141B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
[Technical field to which the invention belongs]
The invention disclosed in this specification includes a semiconductor device including a crystalline semiconductor (including a single crystal and a non-single crystal) formed over an insulating substrate such as a glass substrate, a quartz substrate, or a silicon wafer, and It relates to a manufacturing method thereof. In particular, the present invention relates to an example of configuring a CMOS circuit in which an N-channel type semiconductor device and a P-channel type semiconductor device are complementarily combined.
[0002]
[Prior art]
In recent years, a technique for manufacturing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. This is because the demand for active matrix display devices has increased. In an active matrix display device, a TFT (pixel TFT) is arranged in each pixel arranged in a matrix, and a data signal is controlled by a switching function of each pixel TFT.
[0003]
The pixel TFTs arranged in a matrix form are controlled to transmit gate signals and data signals by a peripheral drive circuit formed on the same substrate. In constructing such a control circuit, a technique for constructing a CMOS circuit in which an N-channel TFT and a P-channel TFT are complementarily combined is generally widespread.
[0004]
In addition, since a circuit TFT for constituting such a peripheral drive circuit is required to have high-speed operation, a crystalline silicon film is mainly used as an active layer. Since a crystalline silicon film moves carriers faster than an amorphous silicon film, a thin film transistor having high electrical characteristics can be formed.
[0005]
Here, FIG. 1A shows an example of a cross-sectional view in the case where a CMOS circuit is configured with top gate type TFTs. Reference numeral 101 denotes a glass or quartz substrate, on which a base film 102 is formed. Reference numeral 103 denotes a crystalline silicon film that becomes an active layer of an N-channel TFT, and reference numeral 104 denotes a crystalline silicon film that becomes an active layer of a P-channel TFT.
[0006]
These active layers are covered with a gate insulating film 105, and gate electrodes 106 and 107 are formed. The gate electrodes 106 and 107 are covered with an interlayer insulating film 108 that electrically insulates the extraction wiring and the gate electrode.
[0007]
The interlayer insulating film 108 is provided with source electrodes 109 and 110 and a drain electrode 111 that are electrically connected to the active layers 103 and 104 through contact holes. In this case, since it is a CMOS circuit, the drain electrode 111 is common to the N-channel TFT and the P-channel TFT. Finally, the source and drain electrodes 109 to 111 are covered with a protective film 112, and a CMOS circuit as shown in FIG.
[0008]
The structure shown in FIG. 1A is the simplest configuration of a CMOS circuit, and is an inverter circuit that functions as a circuit that inverts the polarity of a signal. Further, by combining such CMOS circuits, more complex logic circuits such as NAND circuits and NOR circuits can be configured, and various electric circuits can be designed.
[0009]
However, as described in Japanese Patent Application Laid-Open Nos. 4-206971 and 4-286339, CMOS circuits that are conventionally made using a crystalline silicon film have a depletion in terms of electrical characteristics of N-channel TFTs. It has been a problem that the P-channel TFT shifts in the enhancement direction.
[0010]
The electrical characteristics (Id-Vg characteristics) of the TFT in that case are shown in FIG. In FIG. 1B, the horizontal axis (Vg) is the gate voltage, and the vertical axis (Id) is the drain current. A curve indicated by 103 indicates the Id-Vg characteristic of the N-channel TFT, and a curve indicated by 104 indicates the Id-Vg characteristic of the P-channel TFT.
[0011]
  Id-Vg characteristics of N-channel TFT113Shifts in the depletion direction and the Id-Vg characteristics of P-channel TFTs114Shifting in the enhancement direction means that both are biased to the negative side with respect to the gate voltage Vg as shown in FIG.
[0012]
Accordingly, the N-channel type and P-channel type Id-Vg characteristics 113 and 114 are asymmetrical with respect to the gate voltage of 0 V, and the threshold voltage of the N-channel type and P-channel type TFTs. Absolute values are very different.
[0013]
However, as described in Japanese Patent Laid-Open No. 4-206971, if the output voltage is biased due to the difference in threshold voltage (drive voltage) between the N-channel TFT and the P-channel TFT, the CMOS circuit This may cause a decrease in operating speed and a malfunction.
[0014]
In order to solve the above problem, these publications disclose a method of adding an impurity element imparting one conductivity to a channel formation region of a TFT and controlling a threshold voltage.
[0015]
[Problems to be solved by the invention]
However, these techniques (hereinafter referred to as channel dope) have a problem that they are difficult to control when the addition amount is small. In our experimental experience, 1 × 10¹⁸/cm^ThreeTo the extent, no change in the threshold was observed, but beyond that, the change in the threshold was confirmed abruptly with a slight change in concentration.
[0016]
For example, when the shift amount of the threshold voltage to be controlled is 1 V or less, a very small amount of addition is required to shift the threshold voltage of the comma number V.
Therefore, in order to control the threshold voltage with high accuracy, delicate control of the impurity element concentration to be added is indispensable. However, the subtle addition of impurity elements has been extremely difficult technically. For example, the applicant's experimental experience is 1 × 10¹⁸/cm^ThreeTo the extent, no change in the threshold was observed, but beyond that, the change in the threshold was confirmed abruptly with a slight change in concentration.
[0017]
The invention disclosed in this specification has been made in view of the above problems, and it is an object to provide a technique for finely controlling the threshold voltage by finely controlling the addition concentration of the impurity element. And
[0018]
[Means for Solving the Problems]
The configuration of the invention disclosed in this specification is as follows.
An active layer made of a crystalline silicon film disposed on a substrate having an insulating surface;
A gate insulating film obtained by subjecting the active layer to a thermal oxidation treatment;
A gate electrode disposed on the gate insulating film;
In a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined,
An impurity element imparting P-type is intentionally added only in the active layer of the P-channel semiconductor device,
The concentration distribution of the impurity element is discontinuous at the interface between the active layer and the gate insulating film, and tends to continuously decrease toward the interface in the vicinity of the interface on the active layer side,
The impurity element remaining in the vicinity of the interface on the active layer side is used for controlling a threshold voltage.
[0019]
Further, the configuration of the other invention is as follows:
An active layer made of a crystalline silicon film disposed on a substrate having an insulating surface;
A gate insulating film obtained by subjecting the active layer to a thermal oxidation treatment;
A gate electrode disposed on the gate insulating film;
In a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined,
An impurity element imparting P-type is intentionally added to the active layer of the N-channel semiconductor device and the P-channel semiconductor device,
The impurity element concentration distribution is discontinuous at the interface between the active layer and the gate insulating film, and continuously decreases toward the interface near the interface on the active layer side,
The impurity element remaining in the vicinity of the interface on the active layer side is used for controlling a threshold voltage.
[0020]
Specifically, the impurity element is added to a region including at least an edge portion in the active layer of the N-channel semiconductor device,
The impurity element is added to an active layer of the P-channel semiconductor device at least in a region not including an edge portion in a channel formation region.
[0021]
The concentration of the impurity element in the gate insulating film is 1 × 10¹⁷~ 1 × 10²⁰/cm^ThreeIt is characterized by being.
In the present invention, the surface of the active layer (an inversion layer is formed) by incorporating an impurity element (typically B (boron)) imparting P-type contained in the active layer into the thermal oxide film (gate insulating film). The B ion concentration in the surface to be reduced is reduced. That is, when the thermal oxide film is used as a gate insulating film, the incorporated B ions exist in the inside, and the concentration is 1 × 10 5.¹⁷~ 1 × 10²⁰/cm^ThreeIt is.
[0022]
When a crystalline silicon film is obtained by crystallizing an amorphous silicon film, if a catalytic element (metal element) that promotes crystallization is used, the resulting crystalline silicon film contains 5 × Ten¹⁸/cm^ThreeContains at the following concentrations. This value is an example when the thermal oxidation treatment is performed in an atmosphere containing a halogen element. In such a case, the gate insulating film also contains metal elements and halogen elements. In particular, halogen elements are 1 × 10¹⁶~ 1 × 10²⁰/cm^ThreeContained in the gate insulating film at a concentration of.
[0023]
  The metal element is one or more elements selected from Ni (nickel), Co (cobalt), Pt (platinum), Cu (copper), and Fe (iron). Used. The thermal oxidation treatment is performed in a relatively high temperature range of 700 to 1100 ° C., and the halogen elementageIn general, Cl (chlorine) or F (fluorine) is generally used. In the case of introducing a halogen element into the processing atmosphere during the thermal oxidation treatment, HCl gas, NF containing a halogen element in its composition_ThreeGas, ClF_ThreeGas may be used.
[0024]
In the present invention, the crystalline silicon film has an energy band gap of 1.3 to 1.9 eV.
In addition, the energy band gap is obtained by measuring the optical absorption spectrum to determine the optical wavelength dependence of the effective transmittance of the crystalline silicon film,
It is defined by a value calculated by converting the value of the light wavelength at the absorption edge where the effective transmittance starts to decrease into an energy value using an equation represented by E = hc / λ.
[0025]
In the present invention, the N-channel semiconductor device and the P-channel semiconductor device have a subthreshold value of 85 mV / dec or less.
The threshold voltage of the N-channel semiconductor device is -0.2 to 0.5V,
The threshold voltage of the P-channel type semiconductor device is -0.5 to 0.2V,
The window width of the N-channel type semiconductor device and the P-channel type semiconductor device is 1 V or less.
[0026]
In addition, the configuration of other inventions is as follows:
Forming a first active layer and a second active layer made of a crystalline silicon film on an insulating substrate;
Including an impurity element imparting P-type only to the first active layer;
Incorporating the impurity element into a thermal oxide film formed on the surface of the first active layer by applying a thermal oxidation process to the first and second active layers;
A method for manufacturing a semiconductor device having at least
The impurity element concentration distribution is discontinuous at the interface between the active layer and the gate insulating film, and continuously decreases toward the interface near the interface on the active layer side,
The threshold voltage is controlled by using the impurity element remaining in the vicinity of the interface on the active layer side.
[0027]
The first active layer is an active layer of a P-channel type semiconductor device,
The second active layer is an active layer of an N-channel semiconductor device;
The P channel semiconductor device and the N channel semiconductor device are complementarily combined to form a CMOS structure.
[0028]
In addition, the configuration of other inventions is as follows:
Forming a first active layer made of a crystalline silicon film containing an impurity element imparting P-type on a substrate having an insulating surface and a second active layer containing no impurity element;
Performing a thermal oxidation process on the first and second active layers to form a gate insulating film;
A method of manufacturing a CMOS type semiconductor device which is a combination of an N channel type semiconductor device and a P channel type semiconductor device in a complementary manner,
The first active layer constitutes the P-channel type semiconductor device, the second semiconductor device constitutes the N-channel type semiconductor device,
The impurity element contained in the first active layer by the thermal oxidation treatment is taken into the gate insulating film,
Reducing the concentration of the impurity element on the active layer surface on the side in contact with the gate insulating film;
The threshold voltage is controlled using the impurity element remaining on the surface of the active layer in contact with the gate insulating film.
[0029]
In addition, the configuration of other inventions is as follows:
Forming a first active layer and a second active layer made of a crystalline silicon film containing an impurity element imparting P-type on a substrate having an insulating surface;
Performing a thermal oxidation process on the first and second active layers to form a gate insulating film;
A method of manufacturing a CMOS type semiconductor device which is a combination of an N channel type semiconductor device and a P channel type semiconductor device in a complementary manner,
The first active layer constitutes the P-channel type semiconductor device, the second semiconductor device constitutes the N-channel type semiconductor device,
The impurity element contained in the first active layer by the thermal oxidation treatment is taken into the gate insulating film,
Reducing the concentration of the impurity element on the active layer surface on the side in contact with the gate insulating film;
The threshold voltage is controlled using the impurity element remaining on the surface of the active layer in contact with the gate insulating film.
[0030]
Further, the impurity element is added to the active layer of the N-channel semiconductor device at least in a region including an edge portion,
The impurity element is added to an active layer of the P-channel semiconductor device at least in a region not including an edge portion in a channel formation region.
[0031]
The crystalline silicon film is formed using a metal element that promotes crystallization,
The thermal oxidation treatment is performed at a temperature of 700 to 1100 ° C. in an atmosphere containing a halogen element.
[0032]
The metal element is one or more elements selected from Ni, Co, Pt, Cu, and Fe,
The thermal oxidation treatment is performed in a temperature range of 700 to 1100 ° C,
The halogen element is Cl or F.
[0033]
Further, the metal element is Ni, and the heat treatment includes Cl and / or F in its composition, HCl gas, NF_Three Gas, ClF_Three It is performed in an atmosphere containing at least a gas.
[0034]
An object of the present invention is to manufacture a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined using the manufacturing method having the above-described configuration. Note that in the above structure, the first active layer is a P-channel semiconductor device, and the second active layer is an N-channel semiconductor device.
[0035]
  By implementing the invention configured as described above, the conventional channel doping technique can be performed more precisely. This is achieved in the configuration in which B ions are added to the P-channel type semiconductor device, and in the channel formation region, Si / SiO₂Physics to reduce the B ion concentration near the interface (active layer side)phenomenonIs a technology that uses
[0036]
【Example】
[Example 1]
An example of manufacturing a CMOS circuit in which an N-channel TFT and a P-channel TFT are complementarily combined using the present invention will be described. The CMOS circuit manufactured in this embodiment is an inverter circuit having the simplest configuration as shown in FIG. Further, an example in which B (boron) ions are added only to a P-channel TFT to control the threshold voltage. 2 and 3 are used for the description.
[0037]
In FIG. 2A, 201 is a substrate. As the substrate 201, a glass substrate, a quartz substrate, a silicon substrate (wafer), or the like can be used. The substrate is determined in consideration of the heat resistance in the subsequent thermal oxidation process. In this embodiment, a quartz substrate is used as the substrate 201, and a silicon oxide film is formed as a base film 202 on the surface thereof.
[0038]
  Next, a crystalline silicon film to be an active layer of the TFT later is formed. There are various methods for obtaining the crystalline silicon film. In this embodiment, the low pressure thermal CVD method or the plasma CVD method is used.10-300nm,Preferably10-100nm, Typically20-50nmA crystalline silicon film is obtained by crystallizing an amorphous silicon film formed to a thickness of 1 nm by annealing with an excimer laser. As the excimer laser, ultraviolet light using an excitation gas such as KrF or XeCl may be used.
[0039]
In addition, the amorphous silicon film can be crystallized by heat treatment or by means of a combination of heat treatment and laser annealing. For example, a method of solid-phase growing an amorphous silicon film by performing a heat treatment at a temperature of about 600 ° C., and then improving the crystallinity by laser annealing is effective.
[0040]
When the crystalline silicon film 203 is obtained by using the above technique, patterning is performed to form an island-shaped semiconductor layer 204 that will later form an active layer of an N-channel TFT, and an island-shaped structure that will later configure an active layer of a P-channel TFT. A semiconductor layer 205 is formed.
[0041]
Next, a resist mask (not shown) for patterning the island-shaped semiconductor layers 204 and 205 is removed with a dedicated stripping solution, and then the island-shaped semiconductor layer 204 serving as an active layer of the N-channel TFT is covered again. Then, a resist mask 206 is formed. In this state, B ions that are impurity elements imparting P-type are added only to the island-shaped semiconductor layer 205 (channel doping step).
[0042]
In this example, B ions are added by mass separation of B ions 1 × 10¹⁶~ 1 × 10¹⁹/cm^Three Implantation is carried out by an ion implantation method at a concentration of This method has an advantage that the addition amount (addition concentration) can be easily controlled because only B ions can be selectively added. As a means for performing ion implantation without mass separation, there is a plasma doping method in addition to the ion implantation method. In the case of using these means, since B ions are added in clusters (lumps) together with other atoms and molecules, it is necessary to provide a diffusion step later.
[0043]
Further, since the amount of B ions added (added concentration) varies depending on how much Vth is changed, the optimum value must be obtained experimentally. In the configuration of the present invention, the actual channel forming region Si / SiO₂ The B ion concentration in the vicinity of the interface is determined after the subsequent thermal oxidation step. Therefore, it is necessary to adjust the addition concentration based on this.
[0044]
Note that although an example in which B ions are added by an ion implantation method is described in this embodiment, a gas containing a composition containing B ions (such as diborane) is included in the deposition gas when the amorphous silicon film is formed. Therefore, a means for adding B ions can be taken. However, in this case, care must be taken because the threshold voltage of the N-channel TFT is also shifted in the positive direction.
[0045]
When the B ion addition step is completed, the island-like semiconductor layers 204 and 205 are subjected to thermal oxidation treatment here. As a thermal oxidation method, dry O₂ Oxidation, wet O₂ A known oxidation technique such as oxidation or pyrogenic oxidation may be used. In addition, NF as the atmosphere gas_Three Since the oxidation method using gas can form a thermal oxide film even at a relatively low temperature of about 500 to 700 ° C., it can be applied to a glass substrate.
[0046]
This thermal oxidation process in the present embodiment is performed by Si / SiO by incorporating B ions into the thermal oxide film.₂ The purpose is to reduce (or control) the B ion concentration at the interface. FIG. 4 is a graph showing the relationship between the diffusion coefficient (Diffudion Coeffcient) and temperature (Temperature) of silicon and boron.
[0047]
As is clear from FIG. 4, the difference in diffusion coefficient between boron and silicon in silicon is not large (meaning that compared with a metal element), and it can be seen that boron is a substance that is difficult to diffuse. For example, if the thermal oxidation process is performed at 950 ° C, the diffusion coefficient of boron is about 4 × 10^-14cm²/ S and very small. This means that when a redistribution of B ions later occurs at the interface between the silicon film and its thermal oxide film, a clear concentration gradient appears.
[0048]
Here, Si / SiO is obtained by the thermal oxidation process described above.₂ FIG. 5 shows the distribution of the B ion concentration in the vicinity of the interface. FIG. 5 also shows the case of P ions for comparison.
[0049]
As shown in FIG. 5, the added ions (B, P) present in Si are redistributed when an oxide film is formed. This is in Si and SiO₂This phenomenon occurs because the solubility and diffusion rate of added ions are different. The solubility of added ions in Si [C]_SiAnd SiO₂Solubility in [C]_SiO2The equilibrium segregation coefficient m is defined by the following equation.
m = [C]_Si/ [C]_SiO2
[0050]
At this time, Si / SiO₂ The segregation of added ions near the interface is governed by the value of m. In general, assuming that the diffusion coefficient of the added ions in Si is sufficiently large, if m <1, the added ions in Si are SiO₂It is taken in (FIG. 5A). When m> 1, SiO₂Eliminates the added ions, resulting in Si / SiO₂ The concentration of added ions in the vicinity of the interface increases (FIG. 5B).
[0051]
According to literature values, the value of m for B ions is about 0.3 and the value of m for P ions is about 10. Therefore, the concentration distribution of B ions after the thermal oxidation process in this embodiment is as shown in FIG. 5A. B ions are taken into the thermal oxide films 207 and 208, and Si / SiO of the island-like semiconductor layer 205 is obtained.₂ The B ion concentration in the vicinity of the interface is extremely small.
[0052]
  That is, when the island-like semiconductor layer 205 later functions as the active layer of the TFT, the B ion concentration in the vicinity of the active layer main surface (on the side where the inversion layer is actually formed) of the channel formation regionTheSince it can be extremely reduced, a delicate limit of the threshold voltage can be realized by adjusting this concentration. Therefore, the concentration of B ions in the active layer 205 is characterized by decreasing as it approaches the interface with the gate insulating film 208.
[0053]
When P ions are used as added ions, on the contrary, as shown in FIG.₂ Since the P ion concentration in the vicinity of the interface is increased, subtle threshold voltage control cannot be performed.
[0054]
In addition, this thermal oxidation process has an effect of making the concentration of added ions (B ions) uniform on the main surface of the active layer. This effect has the following advantages.
[0055]
  For example, as shown in FIG. 8A, the concentration profile 801 of B ions added by ion implantation or plasma doping is in a non-uniform distribution state in the depth direction in the active layer. In particular, the plasma doping method is effective for forming a shallow doped region.,ThatdistributionIt is difficult to ensure uniformity. 8A and 8B show the concentration distribution in the in-plane direction with attention paid to an arbitrary depth.
[0056]
In other words, density concentration occurs in the in-plane direction (of course, also in the depth direction) in the vicinity of the main surface of the active layer, and this density is reflected in the band state of the channel formation region, and thus the semiconductor device. It affects the variation of the threshold voltage.
[0057]
However, after the thermal oxidation process is performed as in this embodiment, since the B ions are redistributed with some diffusion, the overall difference in density is reduced. That is, as shown in FIG. 8B, B ions in a high concentration region are preferentially taken into the thermal oxide film and sufficiently reduced. Further, the B ions in the low concentration region are increased in concentration by diffusion, and are taken into the thermal oxide film when the concentration exceeds a certain level.
[0058]
  Therefore, the concentration profile 802 of B ions remaining on the main surface of the active layer is substantially uniform in the concentration distribution state.WhenBecome. As described above, the B ion extraction effect by thermal oxidation is also effective in improving the uniformity of concentration distribution.soThis is one of the effects that greatly contribute to the delicate control of the threshold voltage.
[0059]
  Further, in this example, it was formed by this thermal oxidation process.50nmThe thermal oxide film is used as a gate insulating film. When a thermal oxide film is used as a gate insulating film, Si / SiO₂Near the interfaceInSince the interface state and the like can be reduced, a TFT having extremely excellent electrical characteristics can be obtained. The film thickness can be adjusted by changing the temperature, time, and atmosphere of the thermal oxidation process.
[0060]
Furthermore, in the case of the present embodiment, since this thermal oxidation process is performed at a relatively high temperature of 950 ° C., an effect of greatly improving the crystallinity of the island-like semiconductor layers 204 and 205 can be expected.
[0061]
When the state shown in FIG. 2C is obtained after the thermal oxidation process, an aluminum film (not shown) which will later constitute a gate electrode is formed. This aluminum film contains scandium in an amount of 0.2 wt% in order to suppress generation of hillocks and whiskers. The aluminum film is formed by sputtering or electron beam evaporation.
[0062]
Hillocks and whiskers are stab-like or needle-like protrusions resulting from abnormal growth of aluminum. The presence of hillocks and whiskers causes a short circuit and crosstalk between adjacent wirings and between wirings separated between upper limits.
[0063]
As materials other than the aluminum film, anodizable metals such as tantalum and molybdenum can be used. It is also possible to use a silicon film provided with conductivity instead of the aluminum film.
[0064]
When the aluminum film is formed, anodization is performed in the electrolytic solution using the aluminum film as an anode to form a thin and dense anodic oxide film on the surface of the aluminum film. This anodic oxide film plays a role of improving the adhesion between the resist mask and the aluminum film during patterning.
[0065]
Next, resist masks 209 and 210 are formed. Then, using the resist masks 209 and 210, an aluminum film (not shown) is patterned to form aluminum film patterns 211 and 212 which serve as a prototype of the gate electrode. In this way, the state shown in FIG.
[0066]
Next, porous anodic oxide films 213 and 214 are formed on the side surfaces of the aluminum film patterns 211 and 212 in accordance with the conditions described in JP-A-7-169974. In this embodiment, the thickness of the porous anodic oxide films 212 and 214 is 0.7 μm. In this way, the state shown in FIG.
[0067]
  Further, after removing the resist masks 209 and 210, dense and strong anodic oxide films 215 and 216 are formed according to the conditions described in Japanese Patent Laid-Open No. 7-169974. However, in this example, this film thickness is70nmAdjust the ultimate voltage so that In addition, the gate electrodes 21 and 22 are defined by this process. The structure is as shown in FIG.
[0068]
Next, P ions are added to the entire surface as an impurity imparting N-type in the state shown in FIG. This P ion addition is 0.2 to 5 × 10.¹⁵/ Cm² , Preferably 1-2 × 10¹⁵/ Cm² This is done with a high dose. As a doping method, a plasma doping method or an ion doping method is used.
[0069]
As a result of the process shown in FIG. 3A, regions 217 to 220 into which P ions are implanted at a high concentration are formed. These regions later function as source / drain regions. (Fig. 3 (A))
[0070]
Next, after removing the porous anodic oxide films 213 and 214 using a mixed acid solution in which acetic acid, nitric acid and phosphoric acid are mixed, the resist mask 221 covers the elements constituting the right P-channel TFT. Form. In this state, P ions are implanted again. This implantation of P ions has a dosage of 0.1 to 5 × 10 6.¹⁴/ Cm² , Preferably 0.3 to 1 × 10¹⁴/ Cm² A low value of (Fig. 3 (B))
[0071]
That is, the implantation amount of P ions performed in the process shown in FIG. 3B is lower than that in the process shown in FIG. Then, as a result of this step, the regions 223 and 225 become lightly doped low concentration impurity regions. The regions 222 and 226 are high concentration impurity regions into which P ions are implanted at a higher concentration.
[0072]
  In this step, the region 222 becomes the source region of the N-channel TFT. Then, 223 and 225 are low concentration impurity regions, and 226 is a drain region. Also,224The region indicated by is a substantially intrinsic channel formation region. Note that a region indicated by 225 is a region generally called an LDD (lightly doped drain) region.
[0073]
Although not particularly illustrated, a region where ion implantation is blocked by the anodic oxide film 215 exists between the channel formation region 224 and the low-concentration impurity regions 223 and 225. This region is called an offset region and has a distance corresponding to the thickness of the anodic oxide film 215.
[0074]
  The offset gate region is substantially intrinsic without being ion-implanted, but does not form a channel because a gate voltage is not applied, and functions as a resistance component that relaxes electric field strength and suppresses deterioration. However, when the distance (offset width) is short, it does not function as an effective offset region. In this example, the width is70nmTherefore, it does not function as an offset area.
[0075]
Next, the resist mask 221 is removed, and a resist mask 227 covering the left N-channel TFT is formed as shown in FIG. Then, B (boron) ions are implanted as an impurity imparting P-type in the state shown in FIG. Here, the dose amount of B ions is 0.2 to 10 × 10.¹⁵/ Cm² , Preferably 1-2 × 10¹⁵/ Cm² To the extent. This dose amount can be approximately the same as the dose amount in the step shown in FIG.
[0076]
By this step, the high concentration impurity regions 219 and 220 are inverted from the N-type to the P-type, and the source region 228 and the drain region 229 of the P-channel TFT are formed. A channel formation region 230 is formed immediately below the gate electrode 22. This channel formation region 230 is doped with B ions by a channel doping process, but Si / SiO₂ The B ion concentration in the vicinity of the interface decreases as it approaches the interface.
[0077]
Next, after the process shown in FIG. 3C is completed, the resist mask 227 is removed to activate the added impurity elements (P and B ions) and to recover the damage received on the island-shaped semiconductor layer. Excimer laser light is irradiated. Irradiation energy is 200-250mJ / cm² And
[0078]
  When the excimer laser light irradiation is completed, an interlayer insulating film 231 is formed as shown in FIG.400nmThe film is formed to a thickness of The interlayer insulating film 231 may be any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, and may have a multilayer structure. As a method for forming these silicide films, a plasma CVD method or a thermal CVD method may be used. Alternatively, a permeable organic resin film (eg, polyimide) can be used.
[0079]
Next, contact holes are formed, and a source electrode 232 of an N-channel TFT and a source electrode 233 of a P-channel TFT are formed. The drain electrode 234 is configured to be shared between the N-channel TFT and the P-channel TFT, thereby realizing a CMOS structure. (Fig. 3 (D))
[0080]
In this embodiment, an example in which a TFT is formed on a quartz substrate to constitute a CMOS circuit is shown. However, the present invention can be easily applied to a MOSFET formed on a silicon wafer. That is, IC technology is an application field of the present invention.
[0081]
Here, the electrical characteristics (Id-Vg characteristics) of the TFT shown in FIG. 3D manufactured according to the present example are as shown in FIG. In FIG. 6, curves (solid lines) indicated by reference numerals 601 and 602 indicate the Id-Vg characteristics of the N-channel TFT and the P-channel TFT, respectively. A curve (broken line) indicated by 603 is an Id-Vg characteristic of a P-channel TFT when the configuration of the present invention is not used. The horizontal axis represents the gate voltage (Vg) of the TFT, and the vertical axis represents the drain current (Id).
[0082]
In this example, the threshold voltage Vth, n obtained by calculation from the Id-Vg characteristic 601 of the manufactured N-channel TFT was within the range of 0.1 to 0.5V. Further, the threshold voltage Vth, p obtained by calculation from the Id-Vg characteristic 602 of the P-channel TFT was within the range of -0.5 to -0.1V.
[0083]
Further, when compared with the conventional Id-Vg characteristic 603, it can be clearly seen that the Id-Vg characteristic 602 using the present invention is shifted to the positive direction (arrow direction). It should be noted that the threshold voltage obtained from the Id-Vg characteristic 603 indicated by the broken line is within the range of about -1.5 to -1.0V. Therefore, it can be understood that this shift amount is as small as a comma number V, and is so precise that it cannot be controlled by the conventional channel doping technique.
[0084]
This remarkably shows that the channel doping can be performed very precisely by the present invention. The present invention is particularly effective for a TFT having a sufficiently low threshold voltage without channel doping as in this embodiment.
[0085]
Further, as in the configuration of the present invention, it is significant to add B ions only to the P-channel TFT. This will be explained below.
[0086]
Usually, the opening (difference) between the threshold voltage (Vth, n) of the N-channel TFT and the threshold voltage (Vth, p) of the P-channel TFT is called a window. Further, as described in Japanese Patent Laid-Open No. 4-206971, if the window is not symmetrical with respect to the gate voltage 0 V, that is, if the absolute values of Vth, n, Vth, p are biased, the CMOS It is known that the operation speed of the circuit is reduced and malfunction occurs.
[0087]
When a crystalline silicon film is used as the active layer, it often shifts in the negative direction with respect to the gate voltage. Therefore, in general, threshold value control is performed by adding an impurity element imparting P-type to an N-channel TFT, but in this method, the window width becomes large, and the voltage that must be applied to the gate electrode The width will increase.
[0088]
That is, the drive voltage of the gate voltage is increased, resulting in an increase in power consumption. Further, in order to operate a CMOS circuit that operates at a high speed with a high driving voltage, it is necessary to realize high reliability excellent in deterioration resistance, and therefore, a higher performance TFT must be manufactured.
[0089]
However, the window width can be reduced by controlling the threshold value of only the P-channel TFT as shown in this embodiment, so that the power consumption can be reduced. In particular, according to the manufacturing process of this embodiment, the window width can be within a range of 0.2 to 1 V, so that not only the power consumption is reduced but also a highly reliable CMOS circuit can be manufactured.
[0090]
As described above, in this embodiment, since only the threshold voltage of the P-channel TFT is controlled by channel doping, the window width is narrow and the Id-Vg characteristic balance is good. In particular, redistribution of added ions after channel doping and Si / SiO in the channel formation region₂ The greatest feature of the present invention is that the concentration of added ions in the vicinity of the interface is reduced.
[0091]
As a result, it becomes possible to control the threshold voltage delicately, which is very effective in the case where the threshold voltage is small and the channel doping is required to be performed with extremely delicate accuracy as described in the present embodiment. It can be used as a means.
[0092]
[Example 2]
In Example 1, although the example which performs a channel dope process immediately after formation of an island-like semiconductor layer was shown, you may perform a channel dope process between another processes. For example, it may be added to the amorphous silicon film before crystallization, or it may be added to the crystalline silicon film before the island-shaped semiconductor layer (before patterning). In particular, when added to an amorphous silicon film, even when an ion implantation method without mass separation (added ions are implanted in a cluster) is used, it can be uniformly diffused in the film during crystallization. Because it can, it can be implemented without problems.
[0093]
Further, for example, a method of performing a thermal oxidation step after adding ions into the crystalline silicon film before patterning or the crystalline silicon film after patterning and then diffusing the added ions by thermal diffusion or laser annealing may be used.
[0094]
As described above, the position of the channel doping step in the present invention can be changed as appropriate in consideration of other steps. Basically, the final additive ion concentration is finely adjusted in the thermal oxidation step, so that it is sufficient that a necessary amount of additive ions is contained in the island-like semiconductor layer so far.
[0095]
Example 3
In Example 1, the diagrams shown in FIGS. 5A and 5B show a redistribution tendency for a substance having a low diffusion rate. The diffusion rates of P and B ions are almost the same, and are sufficiently small as described with reference to FIG. However, when the diffusion rate of the added ions becomes sufficiently large, the behavior during redistribution changes.
[0096]
For example, when the diffusion rate of B ions increases, a distribution state different from that shown in FIG. In fact, it has been reported that the diffusion rate of B ions increases when the thermal oxidation process is performed in an atmosphere containing hydrogen.
[0097]
In that case, Si / SiO₂ The concentration distribution of B ions at the interface shows a tendency as shown in FIG. That is, as shown in FIG.₂ The concentration of B ions at the interface is lower than that shown in FIG. SiO₂The B ion concentration in the medium is also clearly reduced.
[0098]
Therefore, if this is utilized, the B ion concentration on the main surface of the active layer can be more effectively reduced, and the threshold voltage can be more precisely controlled. In an atmosphere containing hydrogen, since hydrogen ions compensate for dangling bonds (unbonded hands) and defects in the crystalline silicon film constituting the active layer, an effect of improving crystallinity can be added.
[0099]
Example 4
In this embodiment, an example in which a crystalline silicon film having conductivity is used as the gate electrode is shown in FIG. Although an example in which a CMOS circuit is formed on a quartz substrate is shown here, it may be formed on a glass substrate or a silicon substrate (including a wafer). An IC circuit using a conventional MOSFET can be formed on a silicon substrate, or a so-called SOI structure can be used.
[0100]
In FIG. 9, reference numeral 901 denotes a quartz substrate, and reference numeral 902 denotes a silicon oxide film serving as a base film. Reference numerals 903 and 904 denote active layers having LDD regions. 903 is an N-channel TFT and 904 is a P-channel TFT. The active layers 903 and 904 are formed as follows.
[0101]
First, a crystalline silicon film is obtained over the silicon oxide film 902. The forming method may be in accordance with Example 1, or SiH as a film forming gas by a low pressure thermal CVD method._Four, Si₂H₆ , SiH₂Cl₂ Alternatively, a crystalline silicon film may be directly formed using a silane-based gas such as. In this embodiment, a non-doped crystalline silicon film is used. Next, when a crystalline silicon film is obtained, it is patterned into an island shape to form an active layer prototype, and channel doping is performed. In channel doping, B ions are added only to P-channel TFTs as in the first embodiment.
[0102]
Next, a thermal oxidation process is performed to form gate insulating films 905 and 906, and Si / SiO.₂ B ion concentration in the vicinity of the interface is reduced. Note that the heat treatment is performed under optimum conditions in consideration of the film quality of the thermal oxide film, the film thickness, the B ion concentration for threshold value control, and the like. Of course, the formed thermal oxide film is removed, for example, TEOS / O₂ Gas and SiH_Four/ N₂It is also possible to form a silicon oxide film by a plasma CVD method using an O-based gas to form a gate insulating film.
[0103]
Next, later gate electrodes 907 and 908 are formed, and impurity ions are implanted using the gate electrodes as a mask. This impurity implantation process is a process for forming source / drain regions, low-concentration impurity regions (LDD regions), and channel formation regions in the active layers 903 and 904.
[0104]
Note that the low-concentration impurity region is disposed for the purpose of improving the deterioration resistance, and thus may not be provided in a P-channel TFT having a small deterioration problem. In order to form a CMOS circuit on the same substrate, impurity implantation is selectively performed, so that the process becomes somewhat complicated. Therefore, the process is simplified if not arranged. In this embodiment, the LDD regions are arranged in both the N channel type and the P channel type.
[0105]
First, the first impurity implantation (P ions and B ions) is performed. When the first impurity implantation is completed, a silicon nitride film is formed, and sidewalls 909 and 910 are formed using anisotropic etching. . Then, second impurity implantation (P ions and B ions) is performed to form source / drain regions of the N-channel TFT and the P-channel TFT. Note that a portion immediately below the sidewalls 909 and 910 is a low concentration impurity region (LDD region). Further, a channel formation region is directly below the gate electrodes 907 and 908.
[0106]
When the active layers 903 and 904 are completed, a Ti (titanium) film or a Co (cobalt) film is formed on the entire surface by sputtering, and reacted with the silicon film exposed on the source / drain regions and the gate electrodes 907 and 908. . The reaction may be performed by heat treatment, but it is preferable to use the RTA method because the treatment atmosphere is easily controlled and the throughput is high. This technology is known as salicide technology.
[0107]
Thus, part of the source / drain regions and the gate electrodes 907 and 908 are salicided (in this embodiment, titanium silicide or cobalt silicide) to become a low resistance region. After that, an interlayer insulating film 911 is formed, contact holes are formed, wirings 912 to 914 are formed, and a CMOS circuit having a structure as shown in FIG. 9 can be formed.
[0108]
Example 5
The present invention can be applied to various semiconductor integrated circuits. In the present embodiment, an example of application to SRAM (Static Rondom Access Memory) is shown as an example. The description will be given with reference to FIG.
[0109]
The SRAM is a memory using a bistable circuit such as a flip-flop as a storage element, and stores a binary information value (0 or 1) corresponding to the bi-stable state of ON-OFF or OFF-ON of the bistable circuit. To do. This is advantageous in that the memory is retained as long as power is supplied. The memory circuit is composed of an NMOS circuit or a CMOS circuit. The SRAM circuit shown in FIG. 10A is a circuit using a high resistance as a passive load element.
[0110]
Reference numeral 1001 denotes a word line, and reference numeral 1002 denotes a bit line. Reference numeral 1003 denotes a load element having a high resistance, and an SRAM is constituted by two sets of driver transistors as indicated by 1004 and two sets of access transistors as indicated by 1005. The characteristics of the SRAM configured as described above are that it can operate at high speed, is highly reliable, and can be easily incorporated into a system.
[0111]
Example 6
In this embodiment, in addition to the present invention, the technique described in JP-A-7-76753 is implemented. For example, B ions are added not only to a P-channel TFT but also to an N-channel TFT. An example of application will be described.
[0112]
Specifically, when channel doping is performed on a P-channel TFT, B ions imparting a reverse conductivity type are added to a part of the active layer of the N-channel TFT. This is to prevent the occurrence of a leak current (short channel leak) by forming a basin with a high energy barrier in a portion that tends to be a current path, such as an edge portion of the active layer. Japanese Patent Laid-Open No. 7-176753 describes that the above effect can be achieved with various impurities, but this embodiment is a part of the structure (impurities imparting a conductivity type opposite to that of the active layer). Use example).
[0113]
In Example 1, as shown in FIG. 2, a channel mask was selectively doped into the active layer 205 of the P-channel TFT by providing a resist mask 206 for the N-channel TFT during the channel doping process. However, this embodiment is characterized in that an opening is formed in a part of the resist mask 206 and B ions are selectively added to a part of the active layer 204 of the N-channel TFT.
[0114]
In which region of the active layer 204 of the N-channel TFT the B ion is added can be arbitrarily set. In the present embodiment, several application examples will be described.
[0115]
In FIG. 11A, reference numeral 1101 denotes an active layer of an N-channel TFT, and reference numeral 1102 denotes an active layer of a P-channel TFT. Reference numeral 1103 denotes a gate electrode made of a crystalline silicon film, and 1104 denotes a wiring (source or drain electrode) made of a conductive material. Accordingly, FIG. 11A shows a top view of the CMOS circuit.
[0116]
In the active layers 1101 and 1102, the hatched regions are regions where B ions are added during channel doping. In this embodiment, a region where B ions are not added is a substantially intrinsic I layer, and a region where B ions are added in the channel doping process is defined as P.^-I will treat it as a layer. However, the purpose of channel doping is generally N^-The active layer that behaves as a layer is mainly made closer to the properties of the I layer by adding B ions imparting P-type. Therefore, the N layer (N^-Layer) and P^-A layer is a substantially intrinsic I layer.
[0117]
In FIG. 11A, B ions are added only to the edge portion of the active layer 1101 of the N-channel TFT, and this portion is converted to P having the opposite conductivity type.^-It is as a layer. Since the edge portion of the active layer is easily damaged by plasma damage or the like, it is easy to form a current path.^-By providing the layer, the energy barrier is increased to prevent leakage current.
[0118]
Further, FIG. 11B is a cross-sectional view of the N-channel TFT of this CMOS circuit cut along A-A ′. As is apparent from the figure, B ions are added to the edge portions 1105 and 1106 of the active layer, and P^-A layer is formed, and the I layer is left immediately below the gate electrode (region indicated by 1106). On the other hand, FIG. 11C is a cross-sectional view of the P-channel TFT cut along B-B ′. In this case, as is apparent from the figure, B ions are also added under the gate electrode (region shown by 1107), and P as shown by the oblique lines is shown.^-A layer is formed.
[0119]
Further, FIG. 11D is a cross-sectional view of the CMOS circuit cut in the horizontal direction along C-C ′. Even in this case, the structure of the active layer differs between the N-channel TFT and the P-channel TFT. In the case of an N-channel TFT, a strong N-type layer (N⁺⁺The channel formation region 1110 remains as the I layer.
[0120]
In the case of a P-channel TFT, the source region 1111 and the drain region 1112 are doped with B ions at a high concentration to form a strong P-type layer (P⁺⁺And the channel formation region 1113 is formed of P to which a small amount of B ions are added.^-It is a layer.
[0121]
Note that FIGS. 11E, 11F, 11G, and 11H show another example in which B ions are added to the active layer of an N-channel TFT. (E), (F) are locally P on the edge part.^-(G) is a narrow P in the channel formation region.^-In this example, a layer is provided to reduce the leakage current between the source and drain. Further, (H) shows that the edge portion is P so that the damage of the edge portion of the active layer is not deteriorated in the channel doping process.^-This is an example surrounded by layers.
[0122]
As described above, it is possible to use a technique for effectively suppressing leakage current by adding B ions to an N-channel TFT simultaneously with channel doping. Note that the addition of ions to the N-channel TFT only needs to be provided in the resist mask with an opening only in a desired region. Therefore, the present invention can be widely applied without being limited to the example shown in this embodiment.
[0123]
By the way, when B ions are added to the P-channel TFT during channel doping, if the ions are not added only to the edge portion of the active layer, that region remains as a region having the opposite conductivity type. The function of effectively suppressing leakage current is revealed. An example of this will be described with reference to FIG. Since the structure of the CMOS circuit is the same as that in FIG. 11, the same reference numerals are used together.
[0124]
In FIG. 12A, an N-channel TFT denoted by reference numeral 1101 is doped with B ions at the edge portion.^-A layer is formed. Since details have already been described, only an example in which B ions are added to the region shown in FIG. What is different from the above FIG. 11A is the structure of the active layer 1201 of the P-channel TFT.
[0125]
The cross-sectional view (FIG. 12B) obtained by cutting the N-channel TFT in FIG. 12A along AA ′ is not particularly changed, but the cross-section obtained by cutting the P-channel TFT along BB ′ in FIG. In C), the edge portion 1202 is the I layer. Of course, since the region 1203 other than the edge portion is channel-doped, P^-It is a layer.
[0126]
As mentioned above, the I layer is substantially N^-Layer and P^-The layer has the property of being substantially regarded as the I layer. Therefore, the I layer (substantially N^-The layer) behaves as a reverse conductivity type region for the P-channel TFT. That is, since the P-type region and the N-type region are configured, there is a high energy barrier between them, and carrier movement is effectively suppressed.
[0127]
In FIG. 12D, the source region 1204 and the drain region 1205 of the P-channel TFT are strong P-type Ps.⁺⁺The channel formation region 1206 is P^-It is a layer. That is, as shown in FIG. 12C, an I layer that substantially imparts a reverse conductivity type (N type) is finally formed at least at the edge portion of the channel formation region. Thus, the effect of reducing the leakage current can be obtained. As an example of such a configuration, the I layer may be left in the regions shown in FIGS.
[0128]
Example 7
The CMOS circuit manufactured in Embodiment 1 can be applied to an active display device in which a pixel region and a peripheral driver circuit are integrated on the same substrate. As an active display device, an active matrix liquid crystal display device is generally known. The configuration is shown in FIG.
[0129]
The configuration shown in FIG. 13 is an SOG (system on glass) type display device in which a pixel region and a peripheral drive circuit are formed on the same substrate, and further provided with a control circuit such as a memory circuit and a CPU circuit.
[0130]
In FIG. 13, reference numeral 1301 denotes a pixel region, and usually hundreds of thousands of TFTs are arranged in a matrix to control the voltage applied to the liquid crystal. Reference numeral 1302 denotes a vertical scanning drive circuit, and 1303 denotes a horizontal scanning drive circuit. These drive circuits are composed of a shift register circuit, a buffer circuit, a sampling circuit, and the like, and control gate signals and video signals. Reference numeral 1304 denotes a control circuit, which includes a CPU circuit and a memory circuit.
[0131]
A semiconductor device having a CMOS structure is used for horizontal / vertical scanning driving circuits 1302 and 1303, a control circuit 1304, and the like in FIG. These drive circuits and the like are required to have high reliability. However, the semiconductor device having the CMOS structure manufactured in Embodiment 1 can be designed with a sufficient withstand voltage because the drive voltage is small.
[0132]
The electro-optical device to which the present invention can be applied includes not only an active matrix liquid crystal display device as shown in FIG. 13 but also other active flat panel displays, such as an EL display device, It can also be used for a CL display device. Further, it can be applied not only to a direct view type display but also to a projection type display device.
[0133]
In the active display device, the peripheral driving circuit is required to operate at high speed in order to speed up the response of the display screen and suppress flickering and flickering. In particular, a shift register circuit or a counter circuit that performs a clock operation is a circuit that requires the highest speed operation.
[0134]
FIG. 14A shows a shift register circuit constituting a gate driver unit. This shift register circuit has a function for selecting the gate lines arranged in the pixel region sequentially (or one by one). Therefore, when the operation speed of the shift register circuit is slow, it takes time to select the gate line, and finally the time until one field (or one frame) of the display screen is completed becomes long. That is, the screen appears to flicker.
[0135]
This shift register circuit basically includes a clocked inverter circuit as shown in FIG. 14B and an inverter circuit as shown in FIG. Since both FIGS. 14B and 14C are configured by CMOS circuits, a CMOS circuit manufactured by using the present invention is used here.
[0136]
As shown in Embodiment 1, the CMOS circuit manufactured by using the present invention is characterized in that the absolute value of the threshold voltage is almost the same between the N-channel TFT and the P-channel TFT, and the window is Almost symmetrical with respect to Vg = 0V. Therefore, it has a well-balanced characteristic with no output voltage bias. Further, since the window width is narrow (the absolute values of Vth, n and Vth, p are small), there is an advantage that power consumption for driving is low.
[0137]
As described above, it is very effective to produce a CMOS circuit having a good characteristic balance by using the present invention and use it as a peripheral drive circuit. Usually, a drive circuit that operates at high speed has a low withstand voltage and may be severely degraded. However, since the TFT manufactured according to Embodiment 1 can reduce power consumption, that is, driving voltage, a driving circuit having high reliability with little risk of deterioration can be configured.
[0138]
Example 8
This example
An active layer made of a crystalline silicon film disposed on a substrate having an insulating surface;
A gate insulating film obtained by subjecting the active layer to a thermal oxidation treatment;
A gate electrode disposed on the gate insulating film;
In a semiconductor device having a CMOS structure in which an N-channel semiconductor device and a P-channel semiconductor device are complementarily combined,
An impurity element imparting P-type is intentionally added only in the active layer of the P-channel semiconductor device,
The concentration distribution of the impurity element is discontinuous at the interface between the active layer and the gate insulating film, and tends to continuously decrease toward the interface in the vicinity of the interface on the active layer side,
The present invention relates to a semiconductor device characterized in that the impurity element remaining in the vicinity of the interface on the active layer side is used for controlling a threshold voltage.
[0139]
Another example of manufacturing a CMOS circuit in which an N-channel TFT and a P-channel TFT are complementarily combined using the present invention will be described. The CMOS circuit manufactured in this embodiment is an inverter circuit having the simplest configuration as shown in FIG. Further, an example in which B (boron) ions are added only to a P-channel TFT to control the threshold voltage. FIG. 15 is used for the description.
[0140]
In FIG. 15A, reference numeral 1501 denotes a substrate. As the substrate 1501, a glass substrate, a quartz substrate, a silicon substrate (wafer), or the like can be used. However, when the temperature of the subsequent thermal oxidation process is high, specifically when it exceeds 650 ° C, a quartz substrate with excellent heat resistance is used instead of a glass substrate with a low softening point. It is preferable. In this embodiment, a quartz substrate is used as the substrate 1501, and a silicon oxide film is formed as a base film 1502 on the surface thereof.
[0141]
  Next, a crystalline silicon film to be an active layer of the TFT later is formed. In this embodiment, an amorphous silicon film is crystallized to obtain a crystalline silicon film. First, an amorphous silicon film (not shown) is formed by a low pressure thermal CVD method or a plasma CVD method.100nmThe film is formed to a thickness of Since film loss occurs in the subsequent thermal oxidation step, it is preferable to make the thickness thicker than the desired film thickness by taking into account that area.
[0142]
After the amorphous silicon film is formed, the amorphous silicon film is crystallized by means of heat treatment, laser annealing treatment or a combination of both. In this embodiment, crystallization is performed using the techniques described in Japanese Patent Laid-Open Nos. 6-232059 and 7-321339 by the present inventors. These technologies hold 500 to 700 ° C, typically 600 to 650 ° C with metal elements (eg nickel, copper, etc.) in the range of 1 to 24 hours, typically about 4 to 12 hours. By performing the treatment, a silicon film having excellent crystallinity is obtained.
[0143]
By the above means, an amorphous silicon film (not shown) is crystallized to obtain a crystalline silicon film 1503. The crystalline silicon film 1503 thus obtained has superior crystallinity as compared with the case where the technique described in the above publication is not used. Further, according to the knowledge of the present inventors, it is possible to further improve crystallinity by performing laser annealing treatment after crystallization by heat treatment. In this way, the state shown in FIG.
[0144]
Next, the crystalline silicon film 1503 is patterned to form an island-shaped semiconductor layer 1504 that will later constitute an active layer of an N-channel TFT, and an island-shaped semiconductor layer 1505 that will later constitute an active layer of a P-channel TFT.
[0145]
Next, after removing a resist mask (not shown) for patterning the island-shaped semiconductor layers 1504 and 1505 with a dedicated stripping solution, the island-shaped semiconductor layer 1504 that becomes an active layer of the N-channel TFT is covered again. A resist mask 1506 is formed. In this state, B ions that are impurity elements imparting P-type are added only to the island-shaped semiconductor layer 1505 (channel doping step).
[0146]
In this example, B ions are added by mass separation of B ions 1 × 10¹⁶~ 1 × 10¹⁹/cm^Three Implantation is carried out by an ion implantation method at a concentration of In this method, since B ions are added in the form of atoms, they can be uniformly distributed in the island-shaped semiconductor layer. In addition, when ion implantation is performed without mass separation, B ions are added together with other atoms and molecules in the form of clusters (lumps). Therefore, it is necessary to provide a diffusion step later and distribute the ions uniformly.
[0147]
Further, since the amount of B ions added (added concentration) varies depending on how much Vth is changed, the optimum value must be obtained experimentally. In the configuration of the present invention, the actual channel forming region Si / SiO₂ The B ion concentration in the vicinity of the interface is determined after the subsequent thermal oxidation step. Therefore, it is necessary to adjust the addition concentration based on this.
[0148]
Note that although an example in which B ions are added by an ion implantation method is described in this embodiment, a gas containing a composition containing B ions (such as diborane) is included in the deposition gas when the amorphous silicon film is formed. Therefore, a means for adding B ions can be taken. However, in this case, care must be taken because the threshold voltage of the N-channel TFT is also shifted in the positive direction.
[0149]
When the addition of B ions is completed, the resist mask 1506 is removed and a thermal oxidation process is performed. In this embodiment, as the thermal oxidation step, oxygen (O₂ ) In an oxidizing atmosphere containing 1 to 10%, preferably 3% of hydrogen chloride (HCl), at a temperature of 800 to 1100 ° C., specifically 950 ° C., for 30 minutes. (Figure 15 (C))
[0150]
This thermal oxidation process in this example mainly has three purposes.
First, gettering removal of the catalyst element (nickel in this embodiment) used during crystallization,
Second, Si / SiO by incorporating B ions into the thermal oxide film₂ Reduction (or control) of B ion concentration at the interface,
Third, the formation of gate insulating films 1507 and 1508,
It is. In particular, the essential item of the present invention is the second object, Si / SiO.₂ This is a reduction in the B ion concentration at the interface.
[0151]
As is clear from FIG. 4, boron is less diffused than nickel. For example, when the temperature of the thermal oxidation process is 950 ° C, the diffusion coefficient of nickel is about 4 × 10^-8cm²/ S and boron diffusion coefficient (approximately 4 × 10^-14cm²/ S) is approximately 10,000 times.
[0152]
Accordingly, nickel in the island-like semiconductor layers 1504 and 1505 moves quickly and combines with Cl ions to become nickel chloride. Since this nickel chloride is a highly volatile substance, it is desorbed into the gas phase, and the nickel in the film is gettered and removed.
[0153]
Also, Si / SiO by the above-mentioned thermal oxidation process₂ The concentrations of B ions and P ions in the vicinity of the interface are shown in FIG.
[0154]
  Further, in this example, it was formed by this thermal oxidation process.50nmThe thermal oxide film is used as a gate insulating film. When a thermal oxide film is used as a gate insulating film, Si / SiO₂Near the interfaceInSince the interface state and the like can be reduced, a TFT having extremely excellent electrical characteristics can be obtained. The film thickness can be adjusted by changing the temperature, time, and atmosphere of the thermal oxidation process.
[0155]
Further, in the case of this embodiment, since this thermal oxidation process is performed at a relatively high temperature of 950 ° C., the crystallinity of the island-shaped semiconductor layers 1504 and 1505 is greatly improved. This is because when nickel is gettered by Cl ions, the Si dangling bonds left after the nickel is released recombine with each other adjacent Si to form Si-Si bonds. Therefore, the defects in the crystal grains and the defects at the grain boundaries are greatly reduced, and the crystallinity is improved.
[0156]
When the thermal oxidation step is completed and the state shown in FIG. 15C is obtained, the semiconductor device as shown in FIG. 3D is formed in the same manner as in FIG.
[0157]
[Description of TFT in Example 8]
The electrical characteristics (Id-Vg characteristics) of the TFT shown in FIG. 3 (D) manufactured according to Example 8 are as shown in FIG. In FIG. 16, a curve (solid line) indicated by 1601 indicates the Id-Vg characteristic of the N-channel TFT, and a curve (solid line) indicated by 1602 indicates the Id-Vg characteristic of the P-channel TFT. A curve (broken line) indicated by 1603 is an Id-Vg characteristic of the P-channel TFT when the configuration of the present invention is not used. The horizontal axis represents the gate voltage (Vg) of the TFT, and the vertical axis represents the drain current (Id). Further, the Id-Vg characteristic was measured when the drain voltage Vd = 1V.
[0158]
In this embodiment, the threshold voltage Vth, n obtained by calculation from the Id-Vg characteristic 1601 of the N-channel TFT is within the range of 0.1 to 0.5 V, at least −0.2 to 0.5 V. Further, the threshold voltage Vth, p obtained by calculation from the Id-Vg characteristic 1602 of the P-channel TFT was within the range of -0.05 to -0.1 V, at least -0.5 to 0.2 V.
[0159]
Further, when compared with the conventional Id-Vg characteristic 1603, it is apparent that the Id-Vg characteristic 1602 using the present invention is shifted to the positive direction (arrow direction). Note that the threshold voltage obtained from the Id-Vg characteristic 1603 indicated by a broken line was within a range of about -1.5 to -1.0 V. Therefore, it can be understood that this shift amount is as small as a comma number V, and is so precise that it cannot be controlled by the conventional channel doping technique.
[0160]
This remarkably shows that the channel doping can be performed very precisely by the present invention. The present invention is particularly effective for a TFT having a sufficiently low threshold voltage without channel doping as in this embodiment.
[0161]
The semiconductor device manufactured using this embodiment is characterized by extremely excellent high-speed operability. Therefore, it requires a high-speed operability such as a peripheral drive circuit, particularly a shift register circuit, by configuring a CMOS circuit. It can be said that it is most preferable to arrange it at the place where it is placed.
[0162]
Further, the present applicant produced a closed circuit (ring oscillator) formed by connecting an odd number of CMOS circuits in series as shown in FIG. 3D, and examined the frequency characteristics thereof. As shown in FIG. It has been found that such excellent frequency characteristics can be realized. The measurement was performed with a ring oscillator to which 9, 19, and 51 sets (stages) of CMOS circuits were connected, and the relationship between the power supply voltage and the oscillation frequency was obtained.
[0163]
According to FIG. 18, for example, a power supply voltage of 10 (V) and a 9-stage ring oscillator realizes an oscillation frequency of 123 MHz, and it can be seen that the operation speed is extremely high. Such a result is one of the major factors that the S value is extremely small as described above. Therefore, when a circuit capable of high-speed operation as shown in FIG. 18 is configured, the S value needs to be 85 mV / dec or less, preferably 75 mV / dec or less.
[0164]
In this embodiment, a thin film transistor is formed using a crystalline silicon film formed on a quartz substrate. This also contributes to realizing high frequency characteristics. This will be described below.
[0165]
In MOSFETs formed on a silicon wafer, it is generally known that the operating frequency f is inversely proportional to the time constant τ and has a relationship of f = 1 / τ. Since τ can be expressed by the product of the capacitance C and the resistance R, it can be rewritten as f = 1 / CR. The capacitance C includes a gate capacitance, a depletion layer capacitance, a wiring capacitance, a wiring-substrate capacitance, and the like, and the resistor R includes a source / drain resistance, a wiring resistance, and the like. Therefore, the operating frequency is determined by all these capacitors and resistors.
[0166]
Reducing the wiring resistance has been actively researched to increase the operating frequency than before, but when it became difficult with the miniaturization of the wiring, the reduction of the capacitance between the wiring and the board attracted attention. . This is made possible by SOI technology, but the capacity is still being reduced.
[0167]
However, the thin film transistor technology that has been activated in recent years has an advantage that there is no wiring-substrate capacitance because of the great feature that it is formed on a glass substrate or a quartz substrate. The TFT manufactured according to this example has a level comparable to that of an SOI structure TFT in terms of performance (in terms of electrical characteristics), so that the frequency characteristics exceed those of an SOI structure TFT. Can be expected.
[0168]
  Further, it is known that the operating frequency f is inversely proportional to the square of the channel length L. For example, in order to realize a high-speed operation of 200 MHz in an IC, the channel length has to be 0.35 μm or less. However, the channel length is longer in SOI structure TFTsoEven if it is, 200 MHz can be achieved. The TFT of this example has a wiring-to-substrate capacitanceofSince it is superior to the TFT having the SOI structure, a margin can be given by the channel length L and, in some cases, it is expected that a high-speed operation of 200 MHz or more can be realized.
[0169]
As described above, in this embodiment, since only the threshold voltage of the P-channel TFT is controlled by channel doping, the window width is narrow and the Id-Vg characteristic balance is good. In particular, redistribution of added ions after channel doping and Si / SiO in the channel formation region₂ The greatest feature of the present invention is that the concentration of added ions in the vicinity of the interface is reduced.
[0170]
As a result, it becomes possible to control the threshold voltage delicately, which is very effective in the case where the threshold voltage is small and the channel doping is required to be performed with extremely delicate accuracy as described in the present embodiment. It can be used as a means.
[0171]
[Description of Eg of Active Layer]
By the way, the present applicant measured the energy band gap (Eg) at room temperature (10 to 30 ° C.) of the crystalline silicon film formed according to this example. The value of Eg is obtained by measuring the optical absorption spectrum of the crystalline silicon film to determine the optical wavelength dependence of the effective transmittance of the silicon film. The value of the optical wavelength at the absorption edge where the effective transmittance starts to decrease is expressed as E = It was defined as a value calculated by converting to an energy value using an expression represented by hc / λ.
[0172]
  Here, FIG. 19 shows experimental data when the optical absorption spectrum of the crystalline silicon film shown in this example is measured. In FIG. 19, the horizontal axis represents the light wavelength in the normal visible light region, and the vertical axis represents the effective transmittance obtained by calculating the ratio of the light intensity before and after being transmitted through the film (calculated by removing the reflected light component on the film surface). Transmittance). The film thickness of the silicon film is40nmWhen60nmTwo types of were measured.
[0173]
When light is transmitted through the silicon film, light in a wavelength region having an energy larger than Eg of the silicon film cannot be transmitted and absorbed, and light in a wavelength region having energy smaller than Eg is transmitted through the silicon film. From the fact, it is considered that the energy of light having the wavelength at the absorption edge of the optical absorption spectrum corresponds to Eg.
[0174]
In FIG. 19, the transmittance starts to fall in the region where the light wavelength is about 800 nm or less. When Eg is obtained from the wavelength of 800 nm, it is about 1.5 eV. This calculation was obtained from Einstein's photon energy equation, Eg = hc / λ (h: Planck's constant, c: speed of light, λ: light wavelength).
[0175]
The Eg obtained in this way is greatly related to the electrical characteristics of the TFT. For example, since the TFT manufactured in this embodiment is an enhancement type TFT, it must have normally-off characteristics (characteristics in which the TFT is turned off when not selected). For that purpose, it is important that Eg is 1.3 eV or more. The reason will be described below with reference to FIG.
[0176]
Here, FIG. 17 is a diagram schematically showing the band states of the conductive regions 1701 and 1702 serving as the source / drain regions and the channel formation region 1703. Note that ΔE is slightly smaller than that of the N-channel TFT because B ions are subtly added to the channel formation region of the P-channel TFT, but the difference is ignored here because the addition concentration is subtle. Think.
[0177]
As shown in FIG. 17, the conductive region 1701 (or 1702) forms an energy band difference (ΔE) with the channel formation region 1703. At this time, if ΔE is not sufficiently large, the TFT is turned on (normally on) even when it is not selected, resulting in a so-called depletion type TFT.
[0178]
For example, in the SOI structure, Eg = about 1.1 eV. In that case, ΔE is as small as about 0.5 V, and the TFT is normally on. For this reason, normally-off has only been realized by intentionally increasing the value of ΔE by channel doping.
[0179]
However, it is obvious that the value of ΔE naturally increases as the value of Eg increases in FIG. According to the applicant's knowledge, if Eg is 1.3 eV or more, the value of ΔE is large enough to realize normally-off. Therefore, it is important that Eg is 1.3 eV when the TFT of this embodiment is an enhancement type TFT.
[0180]
In the case of Eg = 1.3 eV, the optical wavelength is about 950 nm from the previous photon energy equation. Therefore, a high-performance TFT as shown in the present embodiment can be obtained in the above-described region where the light wavelength is 800 nm and has a range of ± 150 nm, that is, Eg is 1.3 to 1.9 eV, preferably 1.4 to 1.7 eV. It is considered possible.
[0181]
Example 9
In Example 8, gettering of the catalytic element (nickel) was performed using HCl gas._Three , ClF_Three A fluorine-based gas such as a gas can also be used. In this case, the dangling bond is terminated with fluorine in the gettering process, but the Si—F bond is preferable because the bonding force is stronger than the Si—H bond.
[0182]
Also, NF_Three Since the gas decomposes at a lower temperature (about 600 to 800 ° C.) than the HCl gas of Example 1, the temperature of the heat treatment can be lowered. In this embodiment, HCl is 0.1 to 10 wt%, typically 3 wt%, NF with respect to oxygen._Three Heat treatment is performed at 700 ° C. for 30 to 60 minutes in an atmosphere in which gas is mixed at 0.1 to 3 wt%, typically 0.3 wt%.
[0183]
As described above, after removing nickel, the dangling bonds of Si are recombined with each other, and the dangling bonds that could not be recombined are terminated with fluorine to further reduce the defect density. Further, since the temperature of the heat treatment can be lowered by 200 to 300 ° C., the throughput in the manufacturing process can be improved.
[0184]
Also, 3 wt% hydrogen with respect to oxygen, ClF_Three A similar effect can be obtained by performing a wet oxidation treatment for 30 to 60 minutes in a temperature range of 500 to 600 ° C. in an atmosphere containing 0.3 wt% of gas. In this case, there is an additional advantage that nickel gettering is performed between the Cl element and the F element.
[0185]
Example 10
The invention disclosed in this specification can be applied to an electro-optical device using a semiconductor device typified by a TFT (Thin Film Transistor). Examples of the electro-optical device include a liquid crystal display device, an EL (electroluminescence) display device, and an EC (electrochromic) display device.
[0186]
Application products include TV cameras, personal computers, car navigation systems, TV projections, video cameras, and the like. A brief description of these applications will be given with reference to FIG.
[0187]
FIG. 20A illustrates a TV camera, which includes a main body 2001, a camera portion 2002, a display device 2003, and operation switches 2004. The display device 2003 is used as a viewfinder.
[0188]
FIG. 20B illustrates a personal computer, which includes a main body 2101, a cover portion 2102, a keyboard 2103, and a display device 2104. The display device 2104 is used as a monitor, and is required to have a size of a dozen inches diagonal.
[0189]
FIG. 20C illustrates car navigation, which includes a main body 2201, a display device 2202, operation switches 2203, and an antenna 2204. Although the display device 2202 is used as a monitor, it can be said that the allowable range of resolution is relatively wide because the main purpose is to display a map.
[0190]
FIG. 20D illustrates a TV projection, which includes a main body 2301, a light source 2302, a display device 2303, mirrors 2304 and 2305, and a screen 2306. Since the image displayed on the display device 2303 is projected on the screen 2306, the display device 2303 is required to have a high resolution.
[0191]
FIG. 20E illustrates a video camera, which includes a main body 2401, a display device 2402, an eyepiece 2403, operation switches 2404, and a tape holder 2405. Since the photographed image displayed on the display device 2402 can be viewed in real time through the eyepiece 2403, the user can photograph while viewing the image.
[0192]
As described above, the application range of the present invention is extremely wide, and can be applied to manufactured products having various semiconductor circuits.
[0193]
【The invention's effect】
By implementing the invention disclosed in this specification, the conventional channel doping technique can be performed more precisely. Specifically, it becomes possible to control the threshold voltage, which has been controlled in the conventional several V order, in the comma number V order.
[0194]
In particular, the present invention is very effective for TFTs having extremely excellent characteristics (for example, the absolute value of the threshold voltage itself is very small and difficult to control). The window width that affects the power consumption can be set to at least 1 V or less, specifically in the range of 0.4 to 1.0 V.
[Brief description of the drawings]
FIG. 1 shows a structure and characteristics of a thin film transistor.
FIGS. 2A and 2B illustrate a manufacturing process of a thin film transistor. FIGS.
FIG. 3 illustrates a manufacturing process of a thin film transistor.
FIG. 4 is a graph showing the relationship between temperature diffusion coefficients.
[Figure 5] Si / SiO₂ The figure which shows the distribution state of the dopant in an interface.
FIG. 6 is a graph showing characteristics of a thin film transistor.
[Fig.7] Si / SiO₂ The figure which shows the distribution state of the dopant in an interface.
[Figure 8] Si / SiO₂ The figure which shows the distribution state of the dopant in an interface.
FIG. 9 is a view showing a structure of a silicon gate TFT.
FIG. 10 is a diagram showing a circuit configuration of an SRAM.
FIG. 11 is a diagram showing a configuration of an active layer in a CMOS.
FIG. 12 is a diagram showing a configuration of an active layer in a CMOS.
FIG. 13 illustrates a structure of an active matrix display device.
FIG 14 illustrates a structure of a shift register circuit.
FIGS. 15A and 15B illustrate a manufacturing process of a thin film transistor. FIGS.
FIG. 16 shows characteristics of a thin film transistor.
FIG. 17 is a band diagram for explaining Eg.
FIG. 18 is a diagram showing frequency characteristics of a CMOS circuit.
FIG. 19 is a graph showing the optical wavelength dependence of transmitted light.
FIG 20 illustrates an application example of a semiconductor device.
[Explanation of symbols]
101 Glass (or quartz) substrate
102 Silicon oxide film
103 Active layer of N-channel TFT
104 P-channel TFT active layer
105 Gate insulation film
106, 107 Gate electrode
108 Interlayer insulation film
109, 110 Source electrode
111 Drain electrode
112 Protective film

Claims (22)

An active layer comprising a crystalline silicon film disposed on a substrate having an insulating surface;
A gate insulating film formed on the surface of the active layer;
An N-channel TFT and a P-channel TFT each having a gate electrode formed on the gate insulating film;
An impurity element imparting P-type is added only to the active layer of the P-channel TFT,
The concentration of the impurity element in the vicinity of the interface between the active layer and the gate insulating film is such that the concentration of the active layer is less than the concentration of the gate insulating film,
The semiconductor device according to claim 1, wherein the concentration of the impurity element in the active layer decreases as it approaches the interface with the gate insulating film. Oite to claim 1,
The semiconductor device according to claim 1, wherein the concentration of the impurity element in the gate insulating film is 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ . According to claim 1 or claim 2,
The semiconductor device according to claim 1, wherein the gate insulating film is a thermal oxide film. In any one of Claims 1 thru | or 3 ,
The semiconductor device has a CMOS structure. In any one of Claims 1 thru | or 4 ,
A sub-threshold value of the N-channel TFT and the P-channel TFT is 85 mV / dec or less. In any one of Claims 1 thru | or 5 ,
The threshold voltage of the N-channel TFT is −0.2 to 0.5V,
The threshold voltage of the P-channel TFT is −0.5 to 0.2V,
A window width of the N channel type TFT and the P channel type TFT is 1 V or less. In any one of Claims 1 thru | or 6 ,
The semiconductor device according to claim 1 , wherein the gate insulating film contains a halogen element at a concentration of 1 × 10 ¹⁶ to 1 × 10 ²⁰ / cm ³ . In any one of Claims 1 thru | or 7 ,
A semiconductor device, wherein the active layer has a thickness of 10 to 300 nm. An electro-optical device using a semiconductor device according to any one of claims 1 to 8. Camera having an electro-optical device using a semiconductor device according to any one of claims 1 to 8. Computer having an electro-optical device using a semiconductor device according to any one of claims 1 to 8. Navigation system having an electro-optical device using a semiconductor device according to any one of claims 1 to 8. TV having an electro-optical device using a semiconductor device according to any one of claims 1 to 8. Forming a crystalline silicon film over a substrate having an insulating surface;
Patterning the crystalline silicon film to form a first semiconductor layer and a second semiconductor layer;
Adding an impurity element imparting P-type only to the first semiconductor layer;
By performing oxidation treatment on the first semiconductor layer and the second semiconductor layer, a first gate insulating film and a second gate electrode are formed on the surface of the first semiconductor layer and the surface of the second semiconductor layer, respectively. Forming a gate insulating film, and incorporating the impurity element from the first semiconductor layer into the first gate insulating film;
A method for manufacturing a semiconductor device, wherein a P-channel TFT is formed using the first semiconductor layer and an N-channel TFT is formed using the second semiconductor layer. Forming an amorphous silicon film over a substrate having an insulating surface;
After adding a metal element for promoting crystallization on the amorphous silicon film, the crystalline silicon film is formed by performing any one of heat treatment, laser annealing treatment, or heat treatment and laser annealing treatment in combination. Forming,
Patterning the crystalline silicon film to form a first semiconductor layer and a second semiconductor layer;
Adding an impurity element imparting P-type only to the first semiconductor layer;
By performing oxidation treatment on the first semiconductor layer and the second semiconductor layer, a first gate insulating film and a second gate electrode are formed on the surface of the first semiconductor layer and the surface of the second semiconductor layer, respectively. Forming a gate insulating film, and incorporating the impurity element from the first semiconductor layer into the first gate insulating film;
A method for manufacturing a semiconductor device, wherein a P-channel TFT is formed using the first semiconductor layer and an N-channel TFT is formed using the second semiconductor layer. In claim 15 ,
The method for manufacturing a semiconductor device, wherein the metal element is one or more elements selected from Ni, Co, Pt, Cu, and Fe. In any one of Claims 14 thru / or Claim 16 ,
The method for manufacturing a semiconductor device is characterized in that any of dry O ₂ oxidation, wet O ₂ oxidation, and pyrogenic oxidation is used for the oxidation treatment. In any one of Claims 14 thru / or Claim 16 ,
The method for manufacturing a semiconductor device, wherein the oxidation treatment is performed in an atmosphere containing a halogen element . In any one of Claims 14 thru / or Claim 16 ,
The method for manufacturing a semiconductor device, wherein the oxidation treatment is performed in an atmosphere containing at least HCl gas, NF ₃ gas, or ClF ₃ gas. In any one of Claims 14 thru / or Claim 16 ,
The method for manufacturing a semiconductor device, wherein the oxidation treatment is performed using NF ₃ at 500 to 700 degrees. In any one of Claims 14 to 20 ,
The method for manufacturing a semiconductor device, wherein the gate insulating film contains the impurity element at a concentration of 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ . In any one of Claims 14 to 21 ,
A method for manufacturing a semiconductor device, wherein the gate insulating film contains a halogen element at a concentration of 1 × 10 ¹⁶ to 1 × 10 ²⁰ / cm ³ .

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