JPS61182267A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61182267A JPS61182267A JP2185785A JP2185785A JPS61182267A JP S61182267 A JPS61182267 A JP S61182267A JP 2185785 A JP2185785 A JP 2185785A JP 2185785 A JP2185785 A JP 2185785A JP S61182267 A JPS61182267 A JP S61182267A
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin
- oxide film
- substrate
- gate oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000010408 film Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 239000010409 thin film Substances 0.000 claims abstract description 28
- 238000009792 diffusion process Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 21
- 230000003647 oxidation Effects 0.000 abstract description 7
- 238000007254 oxidation reaction Methods 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000007796 conventional method Methods 0.000 abstract description 5
- 230000001133 acceleration Effects 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 150000002500 ions Chemical class 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 17
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- 238000000206 photolithography Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は半導体装置、特に半導体基板表面部内の拡散
層上に位置して局所的に薄膜部を有するゲート酸化膜が
前記半導体基板上に形成されたＥＥＰＲＯＭセルを製造
する方法に関する。Detailed Description of the Invention (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a gate oxide film having a locally thin film portion located on a diffusion layer in a surface portion of a semiconductor substrate is formed on the semiconductor substrate. The present invention relates to a method of manufacturing an EEPROM cell.
（従来の技術）
上記Ｅ Ｅ Ｐ ＲＯＭ （Ｅｌｅｃｔｒｉｃａｌｌｙ
ＥｒａｓａｂｌｅＰｒｏｇｒａｍｍａｂｌｅ Ｒｅａ
ｄ ０ｎｌｙ Ｍｅｍｏｒｙ）セルの従来の製造方法を
第２図を参照して説明する。(Prior art) The above EEPROM (Electrically
ErasableProgrammable Rea
A conventional method for manufacturing a dOnly Memory) cell will be explained with reference to FIG.
第２図（，１において、１はＰ型シリコン単結晶基板で
あり、まず、この基板１の表面部に通常のＬＯＣＯ３法
によりフィールド酸化膜２を選択的に形成することによ
り、基板面をフィールド領域とアクティブ領域に分ける
。次に、アクティブ領域の基板１表面に酸化処理により
シリコン酸化膜３を形成する。In FIG. 2 (, 1), 1 is a P-type silicon single crystal substrate. First, a field oxide film 2 is selectively formed on the surface of the substrate 1 by the usual LOCO3 method. Next, a silicon oxide film 3 is formed on the surface of the substrate 1 in the active region by oxidation treatment.
次に、第２図ｆｂ）に示すように、シリコン酸化膜３の
一部にホトリソグラフィ技術により開口部４を形成する
。そして、この開口部４に対応する部分の基板１表面部
内にイオンインプランテーション技術により第１のＮ型
拡散層５を形成する。Next, as shown in FIG. 2fb), an opening 4 is formed in a part of the silicon oxide film 3 by photolithography. Then, a first N-type diffusion layer 5 is formed in a surface portion of the substrate 1 corresponding to this opening 4 by ion implantation technology.
その後、酸化処理を施すことにより、第１のＮ型拡散層
５上に第１図（ｃ）に示すように１００人厚程度の非常
に薄いシリコン酸化膜６を形成する。Thereafter, by performing an oxidation treatment, a very thin silicon oxide film 6 having a thickness of about 100 layers is formed on the first N-type diffusion layer 5, as shown in FIG. 1(c).
この時、シリコン酸化膜３は５００人厚程度となり、こ
のシリコン酸化膜３と前記シリコン酸化膜６とにより局
所的に薄膜部を有する第１のゲート酸化膜７が製造され
る。At this time, the silicon oxide film 3 has a thickness of about 500 nm, and the silicon oxide film 3 and the silicon oxide film 6 form a first gate oxide film 7 having locally thin film portions.
次に、第２図（ｄ）に示す第１のポリシリコン層８゜第
２のゲート酸化膜９および第２のポリシリコン層１０（
第１および第２のポリシリコン層８，１０には不純物が
高濃度にドープされる）を順次全面に形成した後、これ
らと前記第１のゲート酸化膜７をホトリソグラフィ技術
によりパターニングすることにより、それらを第２図（
ｄ）に示すようにゲート領域にのみ残す。Next, as shown in FIG. 2(d), the first polysilicon layer 8, the second gate oxide film 9 and the second polysilicon layer 10 (
The first and second polysilicon layers 8 and 10 are doped with impurities at a high concentration) are sequentially formed over the entire surface, and then these and the first gate oxide film 7 are patterned by photolithography. , they are shown in Figure 2 (
It is left only in the gate region as shown in d).
その後、前記パターニングにより露出した基板１の表面
部にソース・ドレイン領域となる第２のＮ型拡散層１１
ａ、ｌｌｂを自己整合技術により前記第２図（ｄ）に示
すように形成する。この時、前記第１のＮ型拡散層５が
ドレイン領域としての一方の第２のＮ型拡散層１１ｂと
接触し電気的に導通した状態となり、第１のＮ型拡散層
５はドレイン領域の一部となる。・
しかる後、第２図＋ｅ）に示すように全面にＰＳＧなど
の中間絶縁膜１２を形成し、これにホトリソグラフィ技
術によりコンタクト穴１３ ａ、 １３ ｂ。After that, a second N-type diffusion layer 11 which becomes a source/drain region is formed on the surface of the substrate 1 exposed by the patterning.
A, llb are formed by self-alignment technique as shown in FIG. 2(d). At this time, the first N-type diffusion layer 5 contacts one of the second N-type diffusion layers 11b serving as the drain region and becomes electrically conductive, and the first N-type diffusion layer 5 is in contact with the second N-type diffusion layer 11b serving as the drain region. Become a part. - Thereafter, as shown in FIG. 2+e), an intermediate insulating film 12 such as PSG is formed on the entire surface, and contact holes 13a and 13b are formed in this by photolithography.
１３ｃを開ける。さらに、このコンタクト穴１３ａ。Open 13c. Furthermore, this contact hole 13a.
１３ｂ、１３ｃを介して第２のＮ型拡散層１１ａ。A second N-type diffusion layer 11a via 13b and 13c.
１１ｂおよび第２のポリシリコン層１０に接続されるア
ルミ配線１４ａ、１４ｂ、１４ｃを形成し、最後に図示
しない保護膜を形成する。Aluminum wirings 14a, 14b, and 14c connected to 11b and the second polysilicon layer 10 are formed, and finally a protective film (not shown) is formed.
なお、このようにして製造されたＥＥＰＲＯＭセルの平
面図を第３図に示す。Incidentally, a plan view of the EEPROM cell manufactured in this manner is shown in FIG.
（発明が解決しようとする問題点）
以上のＥＥＰＲＯＭセルにおいては、シリコン酸化膜６
により、第１のゲート酸化膜の拡散層上の局所的な薄膜
部（１００人厚程度）が構成される。しかるに、上記従
来の方法では、その薄膜部を、拡散層５の形成後に形成
するため、増速酸化といった問題があり、膜厚の制御が
難しかった。(Problems to be Solved by the Invention) In the above EEPROM cell, the silicon oxide film 6
As a result, a local thin film portion (approximately 100 mm thick) on the diffusion layer of the first gate oxide film is formed. However, in the conventional method described above, since the thin film portion is formed after the formation of the diffusion layer 5, there is a problem of accelerated oxidation, and it is difficult to control the film thickness.
（問題点を解決するための手段）
この発明は上記問題点を解決するため、局所的に薄膜部
を有するゲート酸化膜を半導体基板上に形成し、その後
、前記薄膜部下の拡散層を半導体基板に形成する。(Means for Solving the Problems) In order to solve the above problems, the present invention forms a gate oxide film having a locally thin film portion on a semiconductor substrate, and then spreads a diffusion layer under the thin film onto the semiconductor substrate. to form.
（作 用）
このようにすると、半導体基板を直接酸化してゲート酸
化膜の薄膜部を形成するようになるので、薄膜部の膜厚
を高精度に制御できる。(Function) In this way, the thin film portion of the gate oxide film is formed by directly oxidizing the semiconductor substrate, so that the thickness of the thin film portion can be controlled with high precision.
（実施例）
以下この発明の実施例を図面を参照して説明する。まず
、第１の実施例について第１図を参照して説明する。(Example) Examples of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIG.
第１図体）において、２１はＰ型シリコン単結晶基板（
半導体基板）であり、まず、この基板２１の表面部に通
常のＬＯＣＯ８法によりフィールド酸化膜２２を選択的
に形成することにより、基板面をフィールド領域とアク
ティブ領域に分ける。In the first figure), 21 is a P-type silicon single crystal substrate (
First, a field oxide film 22 is selectively formed on the surface of the substrate 21 by the usual LOCO8 method, thereby dividing the substrate surface into a field region and an active region.
次に、アクティブ領域の基板２１表面に酸化処理により
シリコン酸化膜２３を５００人厚程度に形成する。次い
でシリコン酸化膜２３の一部にホトリソグラフィ技術に
より開口部２４を形成し、その後、再び酸化処理を実施
することにより、前記開口部２４により露出した基板２
１の表面に１００人厚程度にシリコン酸化膜２５を形成
する。これにより、アクティブ領域の基板２１上には、
シリコン酸化膜２３とシリコン酸化膜２５によって、局
所的に薄膜部を有する第１のゲート酸化膜２６が形成さ
れたことになる。Next, a silicon oxide film 23 is formed to a thickness of about 500 nm on the surface of the substrate 21 in the active region by oxidation treatment. Next, an opening 24 is formed in a part of the silicon oxide film 23 by photolithography, and then oxidation treatment is performed again to remove the substrate 2 exposed through the opening 24.
A silicon oxide film 25 is formed on the surface of the silicon oxide film 25 to a thickness of about 100 nm. As a result, on the substrate 21 in the active area,
A first gate oxide film 26 having locally thin film portions is formed by the silicon oxide film 23 and the silicon oxide film 25.
しかる後、イオンインブラン′チージョン技術によりＰ
またはＡｓなどのＮ型不純物を第１のゲート酸化膜２６
を介して基板２１に導入する。この時、イオンインプラ
ンテーションの加速電圧を３０ＫｅＶ程度に設定すれば
、第１のゲート酸化膜２６の薄膜部（シリコン酸化膜２
５）を介して、この薄膜部の下のみにＮ型不純物が導入
され、この部分に第１図（ｂ）に示すように第１のＮ型
拡散層２７が形成される。After that, P
Alternatively, N-type impurities such as As may be added to the first gate oxide film 26.
is introduced into the substrate 21 via. At this time, if the acceleration voltage of ion implantation is set to about 30 KeV, the thin film portion of the first gate oxide film 26 (silicon oxide film 2
5), an N-type impurity is introduced only under this thin film portion, and a first N-type diffusion layer 27 is formed in this portion as shown in FIG. 1(b).
以上により従来の第２図（Ｃ１と同一の構造が得られた
ことになる。その後は従来の方法と同一の工程（ここで
は説明を省略する）を行い、第２図（ｅ）に示したよう
なＥＥＰＲＯＭセルを完成させる。As a result, the same structure as the conventional method shown in FIG. Complete an EEPROM cell like this.
第４図はこの発明の第２の実施例を示す。この第２の実
施例では、第１のゲート酸化膜２６上に形成される第１
のポリシリコン層２８からの不純物拡散により第１のＮ
型拡散層２７を形成する。FIG. 4 shows a second embodiment of the invention. In this second embodiment, the first gate oxide film 26 is formed on the first gate oxide film 26.
The first N
A mold diffusion layer 27 is formed.
すなわち、第１の実施例と同様にしてフィールド酸化膜
２２および第１のゲート酸化膜２６を形成した後、この
第１のゲート酸化膜２６上を含む全面にＮ型不純物を高
濃度に含む第１のポリシリコン層２８を形成する。その
後、熱処理を行うもので、すると、第１のゲート酸化膜
２６の薄膜部（シリコン酸化膜２５）を介して、薄膜部
下の基板２１部分にのみＮ型不純物が第１のポリシリコ
ン層２８から拡散され、その部分に第１のＮ型拡散層２
７が形成される。その後は、従来の方法と同様に第２の
ゲート酸化膜の形成、第２のポリシリコン層の形成、パ
ターニング・・・と続き、最終的に第２図（ｅ）に示し
たＥＥＰＲＯＭセルを完成させる。That is, after forming a field oxide film 22 and a first gate oxide film 26 in the same manner as in the first embodiment, a first gate oxide film 22 containing a high concentration of N-type impurities is formed on the entire surface including the first gate oxide film 26. 1 polysilicon layer 28 is formed. After that, heat treatment is performed, and N-type impurities are transferred from the first polysilicon layer 28 only to the substrate 21 portion under the thin film through the thin film portion (silicon oxide film 25) of the first gate oxide film 26. is diffused, and a first N-type diffusion layer 2 is formed in that part.
7 is formed. After that, as in the conventional method, the formation of the second gate oxide film, the formation of the second polysilicon layer, patterning, etc. continued, and finally the EEPROM cell shown in Figure 2(e) was completed. let
（発明の効果）
以上詳述したように、この発明の方法では、局所的に薄
膜部を有するゲート酸化膜を半導体基板上に形成した後
、前記薄膜部下の拡散層を形成するもので、したがって
、半導体基板を直接酸化してゲート酸化膜の薄膜部を形
成するようになるので、薄膜部の膜厚制御が良好となり
、信頼性の高いＥＥＰＲＯＭセルを得ることができる。(Effects of the Invention) As detailed above, in the method of the present invention, after a gate oxide film having a locally thin film portion is formed on a semiconductor substrate, a diffusion layer is formed under the thin film. Since the thin film portion of the gate oxide film is formed by directly oxidizing the semiconductor substrate, the thickness of the thin film portion can be well controlled and a highly reliable EEPROM cell can be obtained.
第１図はこの発明の半導体装置の製造方法の第１の実施
例を示す断面図、第２図は従来のＥＥＰＲＯＭセルの製
造方法を示す断面図、第３図は完成したＥＥＰＲＯＭセ
ルの平面図、第４図はこの発明の第２の実施例を示す断
面図である。
２１・・Ｐ型シリコン単結晶基板、２３・・・シリコン
酸化膜、２５・・・シリコン酸化膜、２６・・・第１の
ゲート酸化膜、２７・・・第１のＮ型拡散層。
＝７−
第１図
第２図
第２図
第３図FIG. 1 is a sectional view showing a first embodiment of the semiconductor device manufacturing method of the present invention, FIG. 2 is a sectional view showing a conventional EEPROM cell manufacturing method, and FIG. 3 is a plan view of the completed EEPROM cell. , FIG. 4 is a sectional view showing a second embodiment of the invention. 21... P-type silicon single crystal substrate, 23... silicon oxide film, 25... silicon oxide film, 26... first gate oxide film, 27... first N-type diffusion layer. =7- Figure 1 Figure 2 Figure 2 Figure 3
Claims (1)
膜部を有するゲート酸化膜が前記半導体基板上に形成さ
れたＥＥＰＲＯＭセルにおいて、局所的に薄膜部を有す
るゲート酸化膜を半導体基板上に形成する工程と、その
後、前記薄膜部下の拡散層を半導体基板に形成する工程
とを具備することを特徴とする半導体装置の製造方法。In an EEPROM cell in which a gate oxide film having a locally thin film portion located on a diffusion layer in a surface portion of the semiconductor substrate is formed on the semiconductor substrate, the gate oxide film having a locally thin film portion is formed on the semiconductor substrate. A method for manufacturing a semiconductor device, comprising the steps of forming a diffusion layer under the thin film, and then forming a diffusion layer under the thin film on a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2185785A JPS61182267A (en) | 1985-02-08 | 1985-02-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2185785A JPS61182267A (en) | 1985-02-08 | 1985-02-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61182267A true JPS61182267A (en) | 1986-08-14 |
Family
ID=12066785
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2185785A Pending JPS61182267A (en) | 1985-02-08 | 1985-02-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61182267A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437876A (en) * | 1987-08-03 | 1989-02-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0196963A (en) * | 1987-10-09 | 1989-04-14 | Toshiba Corp | Manufacture of semiconductor nonvolatile memory |
| JPH01117365A (en) * | 1987-10-30 | 1989-05-10 | Matsushita Electron Corp | Manufacture of semiconductor memory device |
| JPH01129466A (en) * | 1987-11-16 | 1989-05-22 | Nippon Denso Co Ltd | Manufacture of nonvolatile memory cell |
| JPH01289282A (en) * | 1988-05-17 | 1989-11-21 | Ricoh Co Ltd | Semiconductor memory device |
| US6686622B2 (en) | 2001-08-31 | 2004-02-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and manufacturing method thereof |
| WO2014109175A1 (en) * | 2013-01-10 | 2014-07-17 | セイコーインスツル株式会社 | Semiconductor nonvolatile memory and method for manufacturing same |
-
1985
- 1985-02-08 JP JP2185785A patent/JPS61182267A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437876A (en) * | 1987-08-03 | 1989-02-08 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPH0196963A (en) * | 1987-10-09 | 1989-04-14 | Toshiba Corp | Manufacture of semiconductor nonvolatile memory |
| JPH01117365A (en) * | 1987-10-30 | 1989-05-10 | Matsushita Electron Corp | Manufacture of semiconductor memory device |
| JPH01129466A (en) * | 1987-11-16 | 1989-05-22 | Nippon Denso Co Ltd | Manufacture of nonvolatile memory cell |
| JPH01289282A (en) * | 1988-05-17 | 1989-11-21 | Ricoh Co Ltd | Semiconductor memory device |
| US6686622B2 (en) | 2001-08-31 | 2004-02-03 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device and manufacturing method thereof |
| WO2014109175A1 (en) * | 2013-01-10 | 2014-07-17 | セイコーインスツル株式会社 | Semiconductor nonvolatile memory and method for manufacturing same |
| JP2014150241A (en) * | 2013-01-10 | 2014-08-21 | Seiko Instruments Inc | Semiconductor nonvolatile memory and manufacturing method of the same |
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