JPS6315749B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor memory having a MOS transistor type memory cell, and particularly to a method for forming a PN junction in a self-junction manner to increase the capacity of a MOS type capacitor for information storage in the memory cell. Regarding the method.

Conventionally, in 1MOS transistor type memory cells, in order to increase the capacity of the information storage MOS type capacitor and increase the noise margin, P ⁺ N is applied to the capacitor placement area on the surface of the semiconductor substrate by ion implantation or diffusion. ⁺ A junction was formed. However, according to the conventional method, the
In order to form the N ⁺ type region in alignment with the P ⁺ type region, a mask alignment process is essential, and furthermore, the need to provide a margin for mask alignment has the disadvantage of restricting miniaturization of the cell size.

An object of the present invention is to provide a novel method for manufacturing a semiconductor memory in which a PN junction for increasing capacity is formed in a self-aligned manner and cell size can be reduced.

In the manufacturing method according to an embodiment of the present invention, a selective double ion implantation process is performed through a capacitor dielectric film and a polysilicon layer for a capacitor electrode thereon to form a PN junction for increasing capacitance. This method is characterized in that the polysilicon layer is selectively etched according to a pattern opposite to that of ion implantation to form a capacitor electrode layer.Hereinafter, an embodiment shown in the accompanying drawings will be described in detail.

1a to 1d show the manufacturing process of a 1MOS transistor type memory cell according to an embodiment of the present invention, and the steps a to d corresponding to each figure are as follows.

(a) First, a semiconductor substrate 10 made of P-type silicon
A feed oxide film 11 having an opening corresponding to the memory cell arrangement area is formed on the surface of the oxide film 11 by a known selective oxidation method, and then the substrate surface within the opening of the oxide film 11 is thermally oxidized to form a capacitor dielectric made of SiO ₂ . The film 12 is formed to a thickness of several tens of nanometers. and,
A first polysilicon layer 13A with a thickness of about 200 nm is formed on the dielectric film 12 by a known CVD (chemical vapor deposition) method.
Further, silicon nitride is deposited thereon in a similar manner, and then impurity permeation holes corresponding to the desired capacitor forming pattern are formed in the silicon nitride layer by photoetching, thereby forming an impurity mask layer 14. After this, boron ions and arsenic ions A are sequentially implanted into the substrate surface at a high concentration through the impurity permeation holes of the mask layer 14 and the underlying polysilicon layer and dielectric film parts, and are appropriately heat-treated to increase the capacity. for
A P ⁺ type region 15 and an N ⁺ type region 16 are formed.
In this case, to facilitate ion implantation,
It is preferable to dope the polysilicon layer 13A with phosphorus or the like in advance to increase the grain size of the layer 13. Note that the ion implantation energy can be, for example, 150 KeV or more for boron ions and 100 KeV or more for arsenic ions. By the above process, P ⁺ type area 1
5 and N ⁺ type region 16 for increasing capacity.
A P ⁺ N ⁺ junction is formed.

(b) Next, the impurity mask layer 14 made of silicon nitride is used as an oxidation mask.
The surface of the second polysilicon layer 13A is selectively oxidized to form an oxide film 17A. Then, by performing selective etching using the oxide film 17A as a mask, the mask layer 14 and the polysilicon layer portion below it are removed in a pattern opposite to the ion implantation pattern described above, and the capacitor electrode layer 13 is removed.
form. In this case, if necessary, a portion of the dielectric film 12 other than directly below the capacitor electrode layer 13 may be removed to expose the substrate surface.

(c) Next, thermal oxidation treatment is performed again to form an oxide film 17 covering the capacitor electrode layer 13 and a gate insulating film 12'. here,
The gate insulating film 12' is formed of a newly thermally generated silicon oxide film when the substrate surface is exposed in the selective etching in step (b) described above, but when the substrate surface is not exposed, the gate insulating film 12' is formed of a composite film of the dielectric film 12 and a newly thermally generated silicon oxide film. Thereafter, a second polysilicon layer is formed covering the gate insulating film 12' by the CVD method, and is patterned appropriately to form the gate electrode layer 18.

(d) After this, an N ⁺ type drain region is formed that is self-aligned with both electrode layers 18 and 13 by selective impurity introduction treatment using the gate electrode layer 18 and capacitor electrode layer 13 as a mask, for example, selective ion implantation treatment. (Data line) 19 and N ⁺ type source region 20 are formed.

According to the series of steps described above, the P ⁺ type region 15 and the N ⁺ type region 16 for increasing the capacitance can be formed in a self-aligned manner with the capacitor electrode layer (fixed potential line) 13, and the gate electrode layer (word line) ) 18 and the capacitor electrode layer 13 in a self-aligned manner. For this reason, P ⁺ N ⁺ for capacity increase
It simplifies the process by eliminating the need for mask alignment work associated with bond formation, and also has excellent effects such as eliminating the need for mask alignment margins, making it possible to reduce the cell size by that amount, and improving the degree of integration. is obtained.

In the above example, the inverted pattern etching was performed using oxidation treatment using silicon nitride as a mask (step (b) above), but this was done by using a photoresist layer as the mask layer 14 and forming a layer under the photoresist layer in advance. Inverted pattern etching may be used to selectively remove the formed oxide film by plasma etching in HF gas using a photoresist layer as a mask.

[Brief explanation of the drawing]

FIGS. 1a to 1d are cross-sectional views of a substrate showing the manufacturing process of a semiconductor memory according to an embodiment of the present invention. 10... Semiconductor substrate, 11... Field oxide film, 12... Capacitor dielectric layer, 12'... Gate insulating film, 13... Capacitor electrode layer (first poly-Si layer), 14... Impurity mask layer , 15...
P ⁺ type region for increasing capacity, 16... N ⁺ type region for increasing capacity, 18... gate electrode layer (second poly-Si layer),
19...N ⁺ type drain region, 20...N ⁺ type source region.

Claims (1)

[Scope of Claims] 1. After forming a polysilicon layer as a first conductive layer in a memory cell arrangement portion on the surface of a semiconductor region via a capacitor dielectric film, To increase the capacitance by selectively performing double ion implantation treatment on the surface of the substrate according to a desired capacitor formation pattern.
forming a capacitor electrode layer by forming a PN junction and selectively etching the polysilicon layer of the first conductive layer in the memory cell placement area according to a pattern opposite to the ion implantation pattern; a step of forming a gate electrode layer as a second conductive layer on a portion of the substrate surface spaced apart from the capacitor electrode layer via a gate insulating film;
A method for manufacturing a semiconductor memory comprising the step of forming source and drain regions self-aligned with the electrode layer by selective impurity introduction treatment using the gate electrode layer as a mask. 2. In the manufacturing method according to claim 1, the steps include: forming a nitride film on the first polysilicon layer; etching the nitride film according to a capacitor forming pattern; oxidizing the first layer polysilicon to form an oxide film using the oxide film as an oxidation mask, and etching the first layer polysilicon layer using the oxide film as a mask. Manufacturing method of semiconductor memory.