JPS584966A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS584966A JPS584966A JP56102563A JP10256381A JPS584966A JP S584966 A JPS584966 A JP S584966A JP 56102563 A JP56102563 A JP 56102563A JP 10256381 A JP10256381 A JP 10256381A JP S584966 A JPS584966 A JP S584966A
- Authority
- JP
- Japan
- Prior art keywords
- mask
- film
- sio2
- capacitance
- storage region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 238000003860 storage Methods 0.000 claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims abstract 3
- 238000005530 etching Methods 0.000 claims abstract 2
- 239000003990 capacitor Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims 2
- 239000011810 insulating material Substances 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 24
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 12
- 239000000377 silicon dioxide Substances 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 6
- 230000015654 memory Effects 0.000 abstract description 4
- 238000007796 conventional method Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 4
- 229910052906 cristobalite Inorganic materials 0.000 abstract 4
- 229910052682 stishovite Inorganic materials 0.000 abstract 4
- 229910052905 tridymite Inorganic materials 0.000 abstract 4
- 238000006073 displacement reaction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 13
- -1 boron ions Chemical class 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- MYLBTCQBKAKUTJ-UHFFFAOYSA-N 7-methyl-6,8-bis(methylsulfanyl)pyrrolo[1,2-a]pyrazine Chemical compound C1=CN=CC2=C(SC)C(C)=C(SC)N21 MYLBTCQBKAKUTJ-UHFFFAOYSA-N 0.000 description 1
- 241000532784 Thelia <leafhopper> Species 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、多結晶シリコンからなる二重電極構造を有す
るメモリ・セルを含む半導体装置を製造する方法の改良
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a semiconductor device including a memory cell having a double electrode structure made of polycrystalline silicon.
従来、高容量ＲＡＭ （ｒａｎｄｏｍ ａｃｃｅｓｓ
ｍ＠ｍｏｒｙ ） ｍｌの１トランジスタ・１キヤパシ
タ・メモル・セルで鉱、キャパシタの容量を大にする為
、キャパシタ用電極下方の半導体基板表面には不純物拡
散領域を形成しているが、その領域とキャパシタ用電極
とはセルフ・アテインメントで形成されていない為、そ
れ等の間にずれを生じ易く、電気特性のバラツキが著し
かつえ。Conventionally, high capacity RAM (random access
m@mory ) In order to increase the capacitance of a 1-transistor, 1-capacitor memory cell, an impurity diffusion region is formed on the surface of the semiconductor substrate below the capacitor electrode, but this region and Since the capacitor electrodes are not formed with self-attainment, misalignment between them is likely to occur, resulting in significant variations in electrical characteristics.
第１図乃至第８図は、この種半導体装置を製造する従来
技術を説明する為の工程要所に於ける装置の要部断面説
明図であり・、次に、これ等の図を参照しつつ説明する
。1 to 8 are cross-sectional explanatory views of the main parts of the device at important points in the process to explain the conventional technology for manufacturing this type of semiconductor device.Next, please refer to these figures. I will explain.
第１図参照
（１）例えば窒化７リコン属ｉスクなどを使用し九遇択
的熱酸化法に依ｂ、ｐｍシリコン半導体基板１上にフィ
ールド用二酸化シリコン絶縁膜８を形成する。Refer to FIG. 1. (1) A field silicon dioxide insulating film 8 is formed on the PM silicon semiconductor substrate 1 by a selective thermal oxidation method using, for example, a silicon nitride silicon disk.
（２）前記窒化シリコン属ｉスクなどを除去してから、
熱酸化法に依り、ゲーート絶縁膜３を形成する。(2) After removing the silicon nitride disk, etc.,
A gate insulating film 3 is formed by thermal oxidation.
第８図参照
（３） キャパシタ部分に窓を有するフォト・レジス
ト膜４を形成する。尚、 ４には窓を示している。Refer to FIG. 8 (3) A photoresist film 4 having a window is formed in the capacitor portion. Note that 4 shows a window.
（４） 例えば硼素イオンを注入してｐ＋ｌｉ！遮蔽
領域５を形成する。(4) For example, by implanting boron ions, p+li! A shielding region 5 is formed.
（５） 引き続き、例えば砒素イオンを注入してｎｕ
ｌｌ蓄積領域６を形成する。(5) Continue to implant nu, for example, arsenic ions.
ll accumulation region 6 is formed.
第３図参照
（６） フォト・レジス１１を除去してから化学気相
成長法（ＣＶＤ法〕を適用して１ｍ＋ｆｆｉ多結晶シリ
多結晶シリコ成膜７゜尚、多結晶シリコンへの不純物の
導入と多結晶シリコンの成長とは別にしても良い。Refer to Figure 3 (6) After removing the photoresist 11, chemical vapor deposition (CVD) is applied to form a 1m+ffi polycrystalline silicon film.In addition, impurities are introduced into the polycrystalline silicon. This may be done separately from the growth of polycrystalline silicon.
３１１４図参照
（７） ｎｕｌｌ多結晶多結晶シリコ金膜７−ニング
してキャパシタ用電極を形成する為のマスクとなるフォ
ト・レジスト膜８を通常のフォト・リングラフィ技術に
て形成する。(7) Null polycrystalline polysilicon gold film 7 is coated to form a photoresist film 8 which will serve as a mask for forming capacitor electrodes using ordinary photolithography technology.
第６図参照
（８） フォト・レジスト膜８をマスクとして多結晶
電極７′を形成する。Refer to FIG. 6 (8) Polycrystalline electrode 7' is formed using photoresist film 8 as a mask.
第６図参照
（９） 熱酸化法を適用してキャパシタ用電極７′の
表面に分離絶縁膜９を形成する。Refer to FIG. 6 (9) A thermal oxidation method is applied to form an isolation insulating film 9 on the surface of the capacitor electrode 7'.
第７図参照
（２）化学気相成長法にて１＋ｆｉ多結晶シリコン膜を
成長させ、これをフォト・リソグラフィ技術にてパター
冊ングし、トランスファ・ゲート用トランジスタのゲー
ト電極１０を形成する。Refer to FIG. 7. (2) A 1+fi polycrystalline silicon film is grown by chemical vapor deposition and patterned by photolithography to form the gate electrode 10 of the transfer gate transistor.
第８図参照
（ロ） 例えば、イオン注入法にて砒素イオンを注入し
てトランスファ・ゲート用トランジスタのｎ＋瀝拡歓領
域１１を形成する。Refer to FIG. 8 (b) For example, arsenic ions are implanted using an ion implantation method to form the n+ diffusion region 11 of the transfer gate transistor.
（ロ）化学気相成長法にて燐硅酸ガラス絶縁膜νを成長
させ、これを通常のフォト・リングｚ）フイ技術にてパ
ターニングして電極コンタクト窓を形成する。この後、
必要に応じて熱処理して所謂ガラス・す７ｏ−を行な２
ても良い。(b) A phosphosilicate glass insulating film ν is grown by chemical vapor deposition, and patterned by a conventional photo-ring-fi technique to form an electrode contact window. After this,
If necessary, heat treatment is performed to form a so-called glass 7o-2.
It's okay.
（２）蒸着法にてアル（＝ラム膜を形成し、それをフォ
ト・リソグラフィ技術にてパターニングし電極・配線１
３を形成する。(2) Form an aluminum film using the vapor deposition method, pattern it using photolithography technology, and conduct electrode/wiring 1.
form 3.
前記工程説明から判るように、蓄積領域６とキャパシタ
用電極７′の位置合せは完全にフォト・リングラフィの
位置合せ精度に依存している。従って前記したように特
性のバラツキを生じ易い。As can be seen from the above process description, the alignment of the storage region 6 and the capacitor electrode 7' completely depends on the alignment accuracy of photolithography. Therefore, as described above, variations in characteristics are likely to occur.
本発明は、゛製造工程に僅かな改変を加えるだけで、キ
ャパシタの電荷蓄積領域とキャパシタ用電極とをセルフ
・アラインメント方式で形成できるようにするものであ
シ、以下これを詳細に説明する。The present invention enables the formation of a charge storage region of a capacitor and a capacitor electrode in a self-alignment manner by only making slight modifications to the manufacturing process. This will be described in detail below.
第９図乃至第臆図嬬本発明−実施例を説明する為の工程
要所に於ける半導体装置の要部断面説明図であり、次に
、これ等の図を参照しつつ記述する。尚、本発明は工程
の前半に特徴があり、後手は前記従来技術と変りない。FIGS. 9 to 9 are explanatory cross-sectional views of main parts of a semiconductor device at key process points for explaining embodiments of the present invention, and the description will now be made with reference to these figures. Note that the present invention is characterized by the first half of the process, and the latter part is the same as the prior art described above.
第９図参照
（１）ｐｆｆｉシリコン半導体基板１に通常の技術を適
用してフィールド用二酸化シリコン絶縁膜２及び二酸化
シリコンのゲート絶縁膜３を形成する。Refer to FIG. 9. (1) A field silicon dioxide insulating film 2 and a silicon dioxide gate insulating film 3 are formed on a pffi silicon semiconductor substrate 1 by applying a conventional technique.
第１０図参照
（２）化学気相成長法にてｉ子機多結晶りリコン膜７を
成長させる。Refer to FIG. 10 (2) Grow the i-child polycrystalline silicon film 7 by chemical vapor deposition.
（３） 例えば熱酸化法にて厚さ例えば５００ （Ｘ
） ｓ＊の二酸化クリコン＠ １４ ｉ形成する。(3) For example, the thickness is 500 (X
) Forms s* of cricon dioxide @ 14 i.
第１１図参照
（４）通常のフォト・リングラフィ技術にてキャノ（７
タ領域形成窓ｔＶするフォト・レジスト膜ルを形成すと
。尚、このフォト・レジストはネガ臘のものを使用する
。See Figure 11 (4) Cano (7) using normal photo-phosphorography technology
A photoresist film is formed to form a photoresist region forming window tV. Incidentally, this photoresist is a negative one.
（５）イオン注入法を適用し、例えば硼素イオンを注入
してｐ中温遮蔽領域Ｓを形成する。(5) Applying an ion implantation method, for example, implanting boron ions to form a p-moderate shielding region S.
（６）引き続き例えば砒素イオンを注入してｎ十臘蓄積
領域６を形成する０
第Ｕ図参照
（７）常温で圧力例えば５（Ｔｏｒｒ）の弗［（ＨＦ）
ガス中に於いて二酸化シリ；ン膜１４のエツチングを行
なう。(6) Subsequently, for example, arsenic ions are implanted to form an accumulation region 6 (see Figure U).
The silicon dioxide film 14 is etched in gas.
これに依シ、ネガ溢のフォト・レジスト膜「の下に在る
二酸化クリコン膜のみがエッチングされる。Depending on this, only the silicon dioxide film under the negative photoresist film is etched.
このような現象が起きる理由は解明されていないが、実
験的にｉｌｍすることは容易である。Although the reason why such a phenomenon occurs has not been elucidated, it is easy to illuminate it experimentally.
（８） この後、フォト・レジスト膜１５を除去し、
バターニングされた二酸化シリコン膜１４ヲマスクにし
てｎ十置多結晶シリコン膜７をバターニングし、二酸化
シリコン膜１４を除去すれば１８５図に見られる構造が
得られる。従って、前記従来技術を適用してｌｉａ図に
見られる完成品を得ることがで龜る。(8) After this, the photoresist film 15 is removed,
By using the patterned silicon dioxide film 14 as a mask, the n-decade polycrystalline silicon film 7 is patterned, and the silicon dioxide film 14 is removed to obtain the structure shown in FIG. 185. Therefore, it is difficult to obtain the finished product shown in the lia diagram by applying the prior art.
以上の説明で判るように、本発明に依れば、高容量ＲＡ
ＭＩＩＩ）ランジスタ・ｌキャパシタ・メモリを製造す
るに除し、電荷蓄積領域とキャパシタ用電極をセルフ・
アラインメント方式で形成することができるから、それ
等の間に位置ずれは発生せず、従って、電気特性のバラ
ツキ拡僅少になる。As can be seen from the above explanation, according to the present invention, high capacity RA
MIII) When manufacturing transistors, l-capacitors, and memories, charge storage regions and capacitor electrodes are self-contained.
Since they can be formed using an alignment method, no misalignment will occur between them, and therefore variations in electrical characteristics will be reduced.
第１図乃至第８図線従来技術に依る工程を１！明する為
の工１ｍｌ！所に於ける牛導体装置の要部断面説明図、
縞９図乃至籐シ図社本発明−実施例を観閲説明図である
。
図に於いて、ｌは基板、！ｉｉ絶縁膜、３はゲート絶縁
膜、５は遮蔽領域、６は蓄積領域、７は多結晶シリコン
膜、１４は二酸化シリコン膜、ｔはフォト・レジスト膜
、７′紘キヤパシタ用電極である。
特許出願人 富士通株式会社
代理人弁理士 玉 蟲 久 五 部（外３名）第１図
第２図
第３図
第４図
第７図
第９図
第１１図
第１２図Figures 1 to 8 show the process according to the prior art 1! 1ml of work to clarify! A sectional explanatory diagram of the main part of the cow conductor device at the location,
FIGS. 9A and 9B are explanatory diagrams of the present invention-embodiments published by Shimazusha. In the figure, l is the substrate! ii is an insulating film, 3 is a gate insulating film, 5 is a shielding region, 6 is an accumulation region, 7 is a polycrystalline silicon film, 14 is a silicon dioxide film, t is a photoresist film, and 7' is a capacitor electrode. Patent Applicant: Fujitsu Limited Patent Attorney Hisashi Gobe Tamamushi (3 others) Figure 1 Figure 2 Figure 3 Figure 4 Figure 7 Figure 9 Figure 11 Figure 12
Claims (1)
膜を形成し、更にその上に絶縁膜を形成し、腋絶縁膜を
キャパ７タ領域形成用窓を有するネガｆｆｉフォト・レ
ジスト膜で覆い、該ネガ潅フォト・レジスト膜をマスク
にして前記半導体基板にイオン注入して電荷蓄積領域を
形成し、しかる後、弗酸系ガス中にて前記ネガ臘フォト
・レジスト膜直下の絶縁属をエツチングしてから前記窓
内に残され九絶縁膜をマスクにして前記シリコン膜をバ
ターニングしキャパシタ用電極を形成する工程が含まれ
てなることを特徴とする半導体装置の製造方法。A thin insulating film is formed on a semiconductor substrate, a silicon film is formed on it, an insulating film is further formed on that, and the underarm insulating film is a negative FFI photoresist film having a window for forming a capacitor region. Then, using the negative photoresist film as a mask, ions are implanted into the semiconductor substrate to form a charge storage region, and then the insulating material directly under the negative photoresist film is removed in hydrofluoric acid gas. 1. A method of manufacturing a semiconductor device, comprising the steps of etching and then buttering the silicon film using the insulating film left in the window as a mask to form a capacitor electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56102563A JPS584966A (en) | 1981-06-30 | 1981-06-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56102563A JPS584966A (en) | 1981-06-30 | 1981-06-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS584966A true JPS584966A (en) | 1983-01-12 |
Family
ID=14330689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56102563A Pending JPS584966A (en) | 1981-06-30 | 1981-06-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS584966A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0142252A2 (en) * | 1983-09-26 | 1985-05-22 | Fujitsu Limited | Method for producing semiconductor device |
| EP0167024A2 (en) * | 1984-07-02 | 1986-01-08 | International Business Machines Corporation | Process for making an improved dynamic memory cell structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649554A (en) * | 1979-09-28 | 1981-05-06 | Hitachi Ltd | Manufacture of semiconductor memory |
-
1981
- 1981-06-30 JP JP56102563A patent/JPS584966A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5649554A (en) * | 1979-09-28 | 1981-05-06 | Hitachi Ltd | Manufacture of semiconductor memory |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0142252A2 (en) * | 1983-09-26 | 1985-05-22 | Fujitsu Limited | Method for producing semiconductor device |
| EP0167024A2 (en) * | 1984-07-02 | 1986-01-08 | International Business Machines Corporation | Process for making an improved dynamic memory cell structure |
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