JPH0644604B2 - Manufacturing method of complementary semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an improvement in a method for manufacturing a complementary semiconductor device.

[Technical background of the invention]

Conventionally, as a complementary semiconductor device such as a complementary (C) MOS inverter, as shown in FIG. 1, a P-type well region 2 is provided on an N-type (100) silicon substrate 1 and the P-type well region 2 of the substrate 1 is provided. There is known a structure in which a P channel transistor T _p is provided outside and an N channel transistor T _N is provided in the P type well region 2. The manufacturing procedure of this inverter will be described below.

First, after forming the well region 2 on the substrate 1, the substrate 1 is formed.
Then, a thick element isolation region 3 is formed. Subsequently, gate electrodes 5 ₁ and 5 ₂ made of polysilicon or the like are formed on the substrate 1 and the well region 2 via gate insulating films 4 ₁ and 4 ₂ , respectively. Then, on the well region 2 is selectively coated photoresist film, the substrate 1 a gate electrode 5 ₁ and the photoresist film P Channel transistor T _p-side as a mask
Then, for example, boron is ion-implanted to form p ⁺ type source and drain regions 6 and 7. Similarly, applying a photoresist side P Channel transistor T _p side, arsenic or phosphorus is ion-implanted the photoresist film and the gate electrode 5 ₂ as a mask, N ⁺ -type source and drain regions 8 and 9 form To do. After that, the interlayer insulating film 10 is further deposited, the contact holes 11 are opened, and the wiring layers 12 are deposited. As a result, a CMOS inverter having the P-channel transistor (T _p ) on the substrate 1 and the N-channel transistor (T _N ) on the well region 2 is manufactured. The source and drain regions 6 to 9 of this CMOS inverter have a substantially uniform impurity concentration of 10 ¹⁹ to 10 ²⁰ cm ⁻³ .

[Problems of background technology]

However, according to the CMOS inverter described above,
It has the following drawbacks.

In the above device, if the gate length is shortened in order to increase the degree of integration, the source / drain region 6
The electric field of up to 9 becomes strong and causes so-called impact ionization (collision ionization). In the N-channel transistor, a photoelectron is injected into the gate insulating films 4 ₁ and 42, and in the P-channel transistor, a photohole is injected into each gate insulating film 4 ₁ and 4 _2. Cause a threshold fluctuation of. Especially, the efficiency of this impact ionization is significantly high in the N-channel transistor T _N.
It is difficult and often problematic to reduce the gate length of the N-channel transistor T _N.

Boron implanted in the source and drain regions 6 and 7 of the P channel transistor T _p has a large diffusion coefficient,
The source, in the heat treatment step after the drain region 6 and 9 form, also diffuse laterally as well as the depth direction in the figure, the gate insulating film 4 ₁ source down the drain region 6,
7 greatly increases. In particular, lateral diffusion extending 4 ₁ under the gate insulating film may also 0.7～0.8Myuemu, gate electrode 5 and the source worsens characteristics inviting increase in parasitic capacitance between the drain region 6,7.

As described above, boron injected into the source and drain regions 6 and 7 of the P-channel transistor T _p has a large diffusion coefficient, and the junction depth of the source and drain regions 6 and 7 is reduced as the transistor is miniaturized. In order to do so, it is necessary to lower the impurity concentration, which causes an increase in the resistance of the source / drain regions 6 and 7 and deteriorates the transistor characteristics. Note that the gate electrode of a transistor is generally used also as a wiring, and this resistance also deteriorates the signal transfer characteristic, which is not preferable.

[Object of the Invention]

The present invention has been made in view of the above circumstances and is based on the fluctuation of the threshold value due to the photoelectrons in the N-channel transistor and the lateral diffusion of the source and drain regions extending below the gate electrode across the gate insulating film in the P-channel transistor. Prevents deterioration of characteristics and
Source and drain region resistance of channel transistor,
It is an object of the present invention to provide a method for manufacturing a complementary semiconductor device capable of reducing the resistance of a gate electrode.

[Summary of the Invention] The present invention provides a method for manufacturing a complementary semiconductor device including an N-channel transistor and a P-channel transistor each having a gate electrode, a source, and a drain region formed on a semiconductor substrate having a well region on the surface thereof. Forming a well region on a semiconductor substrate and dividing the substrate surface into a P-type semiconductor region and an N-type semiconductor region;
Forming a gate electrode on each of the N-type semiconductor region and the N-type semiconductor region via a gate insulating film, and ion-implanting a low concentration N-type first impurity into the P-type semiconductor region using one of the gate electrodes as a mask. Then, a step of forming a low-impurity region, a step of forming an insulator on the side wall of the gate electrode, and a step of forming a high-concentration N-type second region in the P-type semiconductor region using the gate electrode and the insulator as a mask, respectively. An impurity is ion-implanted to form a high-impurity region, and a P-type third impurity having a larger diffusion coefficient than the first impurity and the second impurity is ion-implanted into the N-type semiconductor region to form a high-impurity region. And a step of forming a metal silicide layer on the source and drain regions and the gate electrode of at least the P-channel transistor of the above-mentioned two types of transistors. After the formation of the metal silicide layer or the formation of the metal silicide layer, a heat treatment is performed to form N-type source / drain regions composed of a low impurity region and a high impurity region in the P-type semiconductor region, and at the same time, from the high impurity region And a P-type source / drain region are formed.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to FIGS. 2 (a) to (e).

[I] First, a P-type well region 22 was formed on the surface of an N-type (100) silicon substrate (wafer) 21 as a semiconductor substrate, and then an element isolation region 23 was formed on the substrate 21. Subsequently, a thermal oxide film and an electrode material such as polysilicon are laminated and deposited on the substrate 21, and these are photo-etched at the same time to form gate insulating films 24 ₁ and 24 ₂ and the gate insulating films 24 ₁ and 24 ₁ . 24 gate electrode ₂₅ on the ₂ 1, 25 ₂ and were formed respectively (FIG. 2 (a) illustrated). Then, by applying a resist film (not shown) in the P-type Channel transistor forming scheduled portion side, the N Channel transistor forming scheduled portion side, for example, phosphorus ions are implanted using the gate electrode 25 ₂ is used as a mask,
Low concentration first impurity regions (low impurity regions) 26 ₁ and 26 ₂ of 10 ¹⁷ to 10 ¹⁹ cm ⁻³ were formed. Further, after removing the resist film, a thickness of 2000 to
A 5000 Å SiO ₂ film 27 is formed by CVD (Chemical Vapor
Deposition) method was used (Fig. 2 (b)).
Here, since the SiO ₂ film 27 is deposited with a substantially constant film thickness regardless of the direction of the surface to be deposited, the film thickness in the vertical direction of the wafer 21 surface is large in the step portion. Then, the SiO ₂ film 27 is removed by RIE (Reactive Ion Etchin).
g) Etching was performed by anisotropic etching such as the method. At this time, since the SiO ₂ film 27 deposited on the step portion of the end faces of the gate electrodes 25 ₁ and 25 ₂ is thick, the gate electrode 2
The SiO ₂ film 27 ′ remained on the side walls of 5 ₁ , 25 ₂ . The side wall SiO ₂ film left on the element isolation region 23 side is not shown in the drawing. After that, a resist film was deposited on the wafer 21, and the resist film was selectively etched and removed so that the N channel transistor formation planned portion side was exposed to form a resist pattern 28. Subsequently, the resist pattern 28 and the gate electrode 25 ₂ and the like arsenic is ion-implanted at a dose 3 × 10 ¹¹ cm ^-2 as a mask, the second impurity regions (high impurity _region) of the high concentration 29 1, 29 ₂
Was formed. As a result, the source region 30 is formed from one of the first and second impurity regions 26 ₁ and 29 ₁ .
First while the second impurity region ₂₆ 2, 29 ₂ from the drain region 31 are formed (FIG. 2 (c) shown).

[Ii] Next, after removing the resist pattern 28,
Cover the P-type well 22 with a photoresist film so that boron is 1 ×.
Ion implantation was performed at a concentration of 10 ^{13 to} 3 × 10 ¹⁵ cm ^-3 . Here, in this ion implantation, since the residual SiO ₂ film 27 ′ is formed in the step portion as in the case of the N channel transistor, the residual SiO ₂ film 27 ′ is also used as a mask. Then, P ⁺ type source and drain regions 32 and 33 of the P channel transistor are formed. Continuing, 700-1
The implanted impurities were activated and diffused by heat treatment at 000 ° C. As a result, the source / drain regions 3
2 and 33 are the gate electrodes 25 of the P-channel transistor
_{It became} self-aligned to ₁ . Then, the thickness 500 ~
After depositing a titanium layer of 1000Å on the whole surface, 700 ~ 9
It heat-processed at 00 degreeC for 30 minutes. As a result, the source and drain regions 3 of the N channel and P channel transistors are formed.
Silicon of 0 to 33 and the gate electrodes 25 ₂ and 25 ₁ reacted with the titanium to form titanium silicide layers 34 ... As a low resistance layer. At this time, in other regions, the titanium silicide layer is not formed and the titanium layer remains as it is. Further, only the titanium layer was selectively removed by etching with a mixed solution of hydrogen peroxide: ammonia: water = 5: 1: 1 (shown in FIG. 2 (d)). Then, after forming the interlayer insulating layer 35 on the entire surface,
N-channel, P Channel transistor source, and selectively opening the interlayer insulating film 35 corresponding to a portion of the drain region 30 to 33 and the gate electrode ₂₅ 2, 25 ₁ to form a contact hole 36 ... further Al wiring 37 are formed to manufacture a CMOS inverter (shown in FIG. 2 (e)).

The CMOS inverter according to the present invention is provided with a P-type well region 22 on a silicon substrate 21 as shown in FIG.
The well region 22 has a low concentration and a high concentration impurity region 26.
_A source region 20 made of ₁ , 29 ₁ and a drain region 3 made of low-concentration and high-concentration impurity regions 26 ₂ , 29 _2.
1 is provided, and the source and drain regions 29 to 32 and the gate electrode 2 of the N channel and P channel transistors are further provided.
5 _2, 25 is decreased to the structure in which a titanium silicide layer 33 ... on _1.

Thus, according to the CMOS inverter of the present invention,
Between the high-concentration second impurity regions 26 ₂ and 29 ₂ and the gate insulating film 24 ₂ , the low-concentration first impurity regions 26 ₁ and 2 2 are formed.
Since 9 ₁ is formed, a voltage can be dispersed electric field generated near the drain region 31 upon application to the drain region 31, can control the impact Iona Lee THEY Chillon. Further, due to the presence of the metal silicide layer 34 on the source and drain regions 30 to 33 and the gate electrodes 25 ₂ and 25 _{1 of} the N-channel and P-channel transistors, the source and drain regions 30 to 33 and the gate electrodes 25 ₂ and 25. ₁ can be reduced in resistance, and device characteristics can be improved.

Further, according to the present invention, in the production of P Channel transistor, previously formed residual SiO ₂ film 27 'on the side walls of the gate electrode 25 ₁ is expected to lateral diffusion of large boron diffusion coefficient in advance, the remaining SiO ₂ film 27 'boron to ion implantation as a mask, source extending down _one gate electrode 25 sandwiching the gate insulating film 24 _1, the drain region 3
1, 32 can be easily suppressed to 0.2 μm or less, and the parasitic capacitance can be reduced.

In the above embodiment, the case where the titanium silicide layer is formed on the source and drain regions and the gate electrode of each of the N-channel and P-channel transistors has been described. However, the present invention is not limited to this, and the source of each of the P-channel transistors can be used, for example. Even when it is formed only on the drain region and the gate electrode, the same effect can be expected. Hereinafter, such a case will be described with reference to FIGS. 3 (a) and 3 (b). That is, as in the above embodiment, the P ⁺ type source / drain regions 32,
After forming 33, the titanium silicide layer 41 having a thickness of 1000~1500Å deposited on the entire surface by sputter method, a titanium silicide layer in the P-Channel transistor source, only the drain regions 31 and 32 and the gate electrode 25 on _one by photoetching method 41 was left (shown in FIG. 3 (a)). Thereafter, the interlayer insulating film 34 and the contact hole 3 are formed in the same manner as in the embodiment.
6 and Al wiring 37 are formed to manufacture a CMOS inverter (shown in FIG. 3 (b)).

Further, although the titanium silicide layer is used as the low resistance layer in the above-mentioned embodiments, the present invention is not limited to this, and a metal silicide layer such as a molybdenum silicide layer, a platinum silicide layer, a tantalum silicide layer, a tungsten silicide layer, or another material layer. But it's okay. However, since the silicide formation temperature changes depending on the material, it is necessary to appropriately change the heat treatment temperature.

〔The invention's effect〕

As described above in detail, according to the present invention, the threshold variation due to the photoelectrons of the N-channel transistor, the deterioration of the characteristics due to the lateral diffusion of the source and drain regions extending to the gate electrode of the P-channel transistor, the source, the drain region and the gate. It is possible to provide a highly reliable method of manufacturing a complementary semiconductor device capable of suppressing deterioration of characteristics due to high resistance of electrodes.

[Brief description of drawings]

FIG. 1 is a sectional view of a conventional CMOS inverter, and FIG.
3A to 3E are sectional views showing a method of manufacturing a CMOS inverter according to an embodiment of the present invention in the order of steps, and FIGS. 3A and 3B are CMOS inverters according to another embodiment of the present invention. FIG. 6 is a cross-sectional view showing the method of manufacturing in the order of steps. 21 ... N-type (100) silicon substrate (semiconductor substrate),
22 ... P-type well region, 23 ... Element isolation region, 24
₁ , 24 ₂ ... Gate insulating film, 25 ₁ , 25 ₂ ... Gate electrode, 26 ₁ , 26 ₂ , 29 ₁ , 29 ₂ ... Impurity region, 27, 27 ′ ... SiO ₂ film, 30, 32 ... Source region, 31, 33 ... Drain region, 34, 41 ... Titanium silicide layer (low resistance layer), 35 ... Interlayer insulating film, 3
6 ... Contact hole, 37 ... Al wiring.

Claims (5)

[Claims] 1. A method of manufacturing a complementary semiconductor device comprising an N-channel transistor and a P-channel transistor having a gate electrode, a source, and a drain region formed on a semiconductor substrate having a well region on the surface, and a well on the semiconductor substrate. Forming a region and dividing the surface of the substrate into a P-type semiconductor region and an N-type semiconductor region;
Forming a gate electrode on each of the N-type semiconductor region and the N-type semiconductor region via a gate insulating film, and ion-implanting a low concentration N-type first impurity into the P-type semiconductor region using one of the gate electrodes as a mask. Then, a step of forming a low-impurity region, a step of forming an insulator on the side wall of the gate electrode, and a step of forming a high-concentration N-type second region in the P-type semiconductor region using the gate electrode and the insulator as a mask, respectively. An impurity is ion-implanted to form a high-impurity region, and a P-type third impurity having a larger diffusion coefficient than the first impurity and the second impurity is ion-implanted into the N-type semiconductor region to form a high-impurity region. And a step of forming a metal silicide layer on at least a source / drain region and a gate electrode of at least a P-channel transistor of the above two types of transistors. After the formation of the metal silicide layer or the formation of the metal silicide layer, a heat treatment is performed to form N-type source / drain regions composed of a low impurity region and a high impurity region in the P-type semiconductor region, and at the same time, from the high impurity region And a P-type source / drain region are formed. 2. The method of manufacturing a complementary semiconductor device according to claim 1, wherein the second impurity is arsenic and the third impurity is boron. 3. A metal silicide layer is a titanium silicide layer, a molybdenum silicide layer, a platinum silicide layer,
The method for manufacturing a complementary semiconductor device according to claim 1, wherein the method is a tantalum silicide layer or a tungsten silicide layer. 4. The method of manufacturing a complementary semiconductor device according to claim 1, wherein the material of the semiconductor substrate is silicon, and the material of the gate electrode is polysilicon. 5. After forming N-type and P-type source and drain regions, a metal is vapor-deposited on the entire surface and heat-treated to react the metal with the silicon in the source and drain regions and the gate electrode to form a metal silicide layer. The method for manufacturing a complementary semiconductor device according to claim 1, wherein the complementary semiconductor device is formed.