JPS6084859A - Complementary type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent the variation in the threshold value and the like due to hot electrons by a method wherein the source and drain regions of an N-channel transistor are constructed of a region of low impurity concentration formed with its gate electrode as a mask and a region of high impurity concentration formed by superposition on the region alienated from the gate electrode. CONSTITUTION:An Si substrate 21 is provided with a P type well region 22, and this well region is provided with the source region 30 consisting of impurity regions 261 and 291 respectively of a low concentration and a high one and the drain region 31 consisting of impurity regions 262 and 292 respectively of a low concentration and a high one. Further, Ti silicide layers 34 are provided on the source and drain regions 29-32 and the gate electrodes 252 and 251 of N-channel and P-channel transistors. Thereby, an electric field generating in the neighborhood of the drain region 31 on application of a voltage to this region can be dispersed, and the presence of the metal silicide layer 34 enables the source and drain regions 30-33 and the gate electrodes 252 and 251 to be reduced in resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in complementary semiconductor devices and methods for manufacturing the same.

[Technical background of the invention]

Conventionally, as shown in FIG. 1, a complementary semiconductor device, for example, a complementary (C) MOS inverter, has a P-type well region 2 provided on an N-type (100) silicon substrate 1. A P-channel transistor Tp externally,
and an N-channel transistor TN in the P-type well region 2.
One made of paulownia wood is known. The manufacturing procedure of this inverter will be explained below.

First, after forming the well region 2 on the substrate 1,
A thick element isolation region 3 is formed in the area.

Subsequently, gate electrodes 51+52 made of polysilicon or the like are formed on the substrate 1 and the well region 2, respectively, via the gate insulating film 41t'R. Next, a photoresist film is selectively coated on the well mounting 2, and the gate electrode 5 on the side of the P-channel transistor T is coated. Then, using the above photoresist film as a mask, S-beak ηN ions are implanted to form a p+ type sheath and drain region 6.2.

Similarly, a photoresist film is applied to the P-channel transistor Tp side, and this photoresist film and gate electrode 5.
Arsenic or phosphorus is ion-implanted using the mask as a mask to form N-type source and drain regions 8 and 9. After that, the interlayer insulating film 10 is further covered, and the contact holes 11...
・Open the wiring layer 12 and cover it with the wiring layer 12. As a result, a transistor having a P-channel transistor (Tp) in the substrate 1 and an N-channel transistor (TN) in the well region
MOS inverter 4 is manufactured. Note that each source and drain region 6 to 9 of this CMOS inverter has a thickness of 10"
It has an approximately average impurity concentration of ~10'' crn-3 (D).

[Problems with background technology]

However, according to the CMOS inverter mentioned above,
It has the following drawbacks.

■ In the above device, when the gate length is shortened to increase the degree of integration, the source/drain region 6
The electric field at ~9 becomes stronger, causing so-called impact ionization (@sudden ionization), and hot eftrons are injected into the N-channel transistor and hot holes are injected into the P-channel transistor into the respective gate insulating films 'I*'l. This causes threshold fluctuations of each transistor. In particular, the effect of this impact ionization is extremely large in the N-channel transistor TN, so
It is difficult to shorten the gate length of the N-channel transistor TN, which often results in a gap.

■ Since the boron implanted into the source and drain regions 6 and 7 of the P-channel transistor Tp has a large diffusion coefficient,
In the heat treatment step after forming the source and drain regions 6 and 9, the gate insulating film 4 is diffused not only in the depth direction but also in the lateral direction in the figure. Source and drain regions 6 below,
7 grows significantly. In particular, gate insulating film 4. The width of the lateral diffusion extending downward may be as much as 0.7 to 0.8 μm, leading to an increase in the parasitic capacitance between the gate electrode 5 and the source and drain regions 6.7, thereby degrading the characteristics.

■ As mentioned above, the poron implanted into the source and drain regions 6 and 7 of the P-channel transistor T has a large diffusion coefficient, and as transistors are miniaturized, the junction depth of the source and drain regions 6 and 7 is reduced. In order to prevent leakage, it is necessary to lower the impurity concentration, which causes an increase in the resistance of the source and drain regions 6.2 and deteriorates the transistor characteristics. Note that the gate electrode of a transistor is generally also used as a wiring, and this resistance is also undesirable because it deteriorates signal transmission characteristics.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and is based on the opening of the threshold by hot electrons in an N-channel transistor, and the lateral diffusion of the source and drain regions that sandwich the gate insulating film and extend below the gate electrode in a P-channel transistor. In addition to preventing deterioration of characteristics, P
resistance of the source and drain regions of the channel transistor,
It is an object of the present invention to provide a complementary semiconductor device that can reduce the resistance of a gate electrode and a method for manufacturing the same.

[Summary of the invention]

The first invention of the present application provides a source of an N-channel transistor;
The drain region consists of a low impurity region formed using the gate electrode as a mask, and a high impurity region formed overlapping the low impurity region spaced apart from the gate electrode, and The gist of the present invention is to achieve the above object by providing a low resistance j so on at least the source, drain region and gate electrode of a P-channel transistor.

In the second invention of the present application, after forming a well region on a semiconductor substrate, gate electrodes are respectively formed on the substrate and the well region through a gate insulating film, and one gate electrode is used as a mask to form a well region on the substrate or the well region. A low impurity region is formed by ion-implanting N-type impurities at a high concentration, an insulator is formed on each side wall of the gate electrode, and different high concentrations are formed on the substrate and well region using the gate electrode and the insulator as a mask. By ion-implanting impurities to form high impurity regions, N-type source and drain regions consisting of low impurity regions and high impurity regions are formed, and P-type source and drain regions consisting of high impurity regions are formed. However, by forming a low-resistance layer at least on the source, drain region, and gate electrode of the P-channel transistor, the present invention aims to obtain the same effect as the first invention of the present invention.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIGS.

[1] First, a P-type well region 22 was formed on the surface of an N-type (100) silicon substrate (Unihachi) 21 as a semiconductor substrate, and then an element isolation region 23 was formed on the substrate 21. Subsequently, a thermal oxide film and an electrode material such as polysilicon are laminated and coated on the substrate 21, and then these are simultaneously photo-etched to form a gate insulating film 24. , 24° and this gate insulation If! 2'+ + 24 to upper gate electrode 25
．． ．． 25. and were formed respectively (as shown in FIG. 2 (-)). Next, a resist film (not shown) is applied to the side where the P channel transistor and star are to be formed, and the gate electrode 25. Using as a mask, ions of, for example, phosphorus are implanted into the portion where the N-channel transistor is to be formed, and the first impurity regions (low impurity regions) 26, . 26. Fully formed. Furthermore, after removing the resist film, the wafer 21
Upper ItIK thick 20ρo ~ 5000AcDstO, [
2ylCV D (Chemica6Vapour D
deposition) method (Fig. 2 (
b) As shown). Here, the film thickness in the vertical direction on the two sides of the sea urchin becomes thinner. After that, the SiO, l sample 27 was subjected to RIE (Reactive Ion Etc.
Etching was performed by anisotropic etching such as the hing method.

At this time, the gate electrode 25. , 25. Since the SIO film 27 deposited on the stepped portion of the end face of the gate electrode 25. ．． 25. A film 27' of S t O was left on the side wall. In addition, in the figure, the side wall Si remaining on the element isolation region 23 side
n, membrane is not particularly shown. After this, a resist film is placed on top of the sea urchin 2, and the resist film is selectively etched away so that the N-channel transistor forming limbs are covered with silver to form a resist pattern 28, and arsenic is dosed i3.
xlom ion implantation to form a highly concentrated second impurity region (additional impurity region) 29. , 29. was formed. Note that as a result, one of the first and second impurity regions 26, . 2
9. A source region 30 is formed from the other first and second
Impurity region 26. .

29, the drain region 3 was formed (Fig. 2(c)
).

(II) Next, after removing the resist pattern 28, the P-type well 22 was covered with a photoresist film, and ions were implanted into the void at a concentration of I x 10'' to 3 x 10''cra-''. , this ion implantation removes residual S i O in the stepped portion as in the case of N-channel transistors.
Since the H film 22' is formed, the remaining S10 is transferred to the film 27.
' is also used as a mask. Then, P type source and drain regions 32 and 33 of a P channel transistor were formed. Subsequently, the implanted impurities were activated and diffused by heat treatment at 700 to 1000°C. As a result, the source and drain regions 32.3:l became self-aligned with the gate electrode 251 of the P-channel transistor. Next, the entire surface of the titanium layer with a thickness of 500 to 1000 A was steamed, and then heat treated at 700 to 900°C for 30 minutes.

As a result, source and drain regions 30 to 33 and gate electrodes 25 . ．． 2
The silicon 51 reacted with the titanium, and a titanium silicide layer 34 as a low resistance layer was completely formed. In this region 1, no titanium silicide layer is formed and the titanium layer remains. , Furthermore, titanium with a mixture of hydrogen peroxide: ammonia: water - 5:1:1! - was selectively removed by etching (as shown in FIG. 2(d)). After that, all 1
After forming the interlayer insulating layer 35 on the N-channel and P-channel transistors, the source and drain regions 30 to 33 and the gate electrode 25.1 are formed. ．． A contact hole 36 is formed by selectively opening the interlayer insulation yae corresponding to a part of 2.5□.
・ is formed, and the AE wiring 37 is formed properly to form the CMO.
An S inverter was manufactured (as shown in Fig. 2).

The CMOS inverter according to the present invention is shown in FIG. 2 (6) K
As shown, a P-type well region 22 is provided in a silicon substrate 21, and low-concentration and high-concentration impurity regions 26□, 22. A source region 3°O consisting of a low-integrity, high #i anti-impurity region 26. ', 29. A drain region sI7 is provided, and further includes source and drain regions 29 to 32 of N-channel and P-channel transistors, and gate electrodes 25. ．． 25. Titanium silicide layer 37 on top.
? It has a structure with...

According to the CMOS inverter according to the present invention,
High concentration second impurity region '26. .

2,! , and the gate insulating film 24. A low concentration first impurity region 26. ．． 2. Since the drain region 3 is formed with a radial force of 1, it is possible to disperse the electric field generated in the vicinity of the drain region 3 when a heavy pressure is applied to the drain region 3, and impact ionization can be controlled. In addition, the source and drain regions 30 to 33 of N-channel and P-channel transistors and the gate electrode 25. , 25 on the metal silicide #! Due to the presence of jSa..., the source and drain regions 30 to 33 and the gate electrode 25. ．． 25
．． It is possible to lower the resistance and improve device characteristics.

Further, according to the present invention, when manufacturing a P-channel transistor, in advance the lateral diffusion of poron having a large diffusion coefficient is anticipated, and residual StO is deposited on the side wall of the gate electrode 25m.
is formed, and this remaining SiO, II moxibustion layer '7' is also used as a mask for boron ion implantation, so that the gate insulating film 24. sandwiching the gate electrode 25. The source and drain regions 31 and 32 extending downward can be easily suppressed to KO, 2 μm or less, and the parasitic capacitance can be reduced. In the dW embodiment, a titanium silicide layer is formed on the source and drain regions and gate electrodes of N-channel and P-channel transistors, but the invention is not limited thereto. A similar effect can be expected even when the film is formed only on the region and the gate electrode. Hereinafter, such a case will be explained using FIGS. 3(a) and 3(b).

That is, after forming the P type source and drain regions 32 and 33 as in the above embodiment, a titanium silicide layer 41 with a thickness of 1000 to 1500 Å is deposited on the entire surface by sputtering, and the source of the P channel transistor is formed by photolithography. ,
Drain region 31.32 and gate electrode 25. The titanium silicide layer 41 was left only on the top (as shown in Figure 3 (-))
.

Thereafter, an interlayer insulating film 34, contact balls 3, 6... and Ae powder distribution 3 are formed in the same manner as in the example, and CMO
An S inverter is manufactured (as shown in FIG. 3(b)).

Further, in the above embodiments, a titanium silicide layer was used as the low resistance layer, but the layer is not limited to this, and metal silicide layers such as a molybdenum silicide layer, a platinum silicide layer, a tantalum silicide layer, a tungsten silicide JrJ layer, or other layers may be used. A layer of material may be used. However, since the silicide formation temperature changes depending on the phase material, it is necessary to change the heat treatment temperature appropriately. [Effects of the Invention] As detailed above, according to the present invention, the fluctuation of the threshold value due to hot electrons of an N-channel transistor can be reduced. The present invention can provide a source and drain region and a method for reducing characteristics due to lateral diffusion of a source and drain region extending to a gate electrode of a P-channel transistor.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of a conventional CMOS inverter, Figure 2 (
-) to (,) are cross-sectional views showing the manufacturing method of a CMOS inverter according to an embodiment of the present invention in the order of steps, FIG. 3(a)
e (b) is a sectional view showing a method for manufacturing a CMOS inverter according to another embodiment of the present invention in order of steps. 2-1... N type (100) silicon substrate (semiconductor substrate), 22... P type well region, 23... element isolation region, 24. ．． 24. ...Gate insulating film, 25I. 25! ...gate electrode, 26. , 2 ti,, 2
9. . 29,... impurity region, 27, 27'...510
2 film, 30.32...source region, 31.33...
Drain region, 34.41...Titanium silicide layer (
low resistance layer), 35... interlayer insulating film, 36... contact hole, 37... AJ wiring. Patent attorney Suzu Ushiki Hiko

Claims (1)

[Scope of Claims] (1) In a complementary semiconductor device consisting of an N-channel transistor and a P-channel transistor, each of which has a gate electrode and a source and drain region formed on a semiconductor substrate having a well region on its surface, the N-channel transistor The source and drain regions of the above are comprised of a low impurity region formed using the gate electrode as a mask, and a high impurity region formed overlapping the low impurity region spaced apart from the gate electrode, and A complementary semiconductor device characterized in that a low resistance layer is provided on the source, drain region and gate electrode of at least a P channel transistor of a 2 m long transistor. Q) The complementary semiconductor device according to claim 1, wherein the low resistance layer is a metal silicide layer. (3) The metal silicide layer is a titanium silicide layer,
3. The complementary semiconductor device according to claim 2, wherein the complementary semiconductor device is any one of a molybdenum silicide layer, a platinum silicide layer, a tantalum silicide layer, and a tungsten silicide layer. (4) The complementary semiconductor device according to claim 1, wherein the material of the semiconductor substrate is silicon, and the material of the gate electrode is polysilicon. (5) In a method for manufacturing a complementary semiconductor device comprising an N-channel transistor and a P-channel transistor having a gate electrode and source and drain regions formed on a semiconductor substrate having a well region on the surface, the well region is formed on the semiconductor substrate. a step of forming gate electrodes on the substrate and well region via a gate insulating film, and ion implantation of low-irregularity N-type impurities into the substrate or well region using one of the gate electrodes as a mask. Then, a step of forming a low impurity region, a step of forming an insulator on the sidewalls of the gate electrode, and ion implantation of impurities of different high intensity into the substrate and the well region using the gate electrode and the insulator as masks, respectively. forming a highly impurity region, forming an N-type source and drain region consisting of a low impurity region and a high impurity region, and forming a P-type source and drain region consisting of a high impurity region; A method for manufacturing a complementary semiconductor device, comprising the step of forming a low resistance layer on at least the source, drain region and gate electrode of a P-channel transistor of a glazed transistor. (6) The method for manufacturing a complementary semiconductor device according to claim 5, wherein the low resistance layer is a metal silicide layer. Q) The method for manufacturing a complementary semiconductor device according to claim 5, characterized in that the material of the semiconductor substrate is silicon and the material of the gate electrode is polycrystalline silicon. (8) After forming N-type and P-type source and drain regions,
Claim 5 or 6, characterized in that a metal is reacted with silicon in the source, drain region and gate electrode to form a metal silicide layer by vapor depositing metal on the entire surface and heat treating it. 8. A method for manufacturing a complementary semiconductor device according to item 7.