JPS6362108B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device including complementary MOS transistors on the same substrate.

As is well known, complementary MOS transistors (hereinafter referred to as
CMOS) usually creates a semiconductor substrate by selectively forming a p-type well on an n-type silicon substrate.
A p channel MOS transistor in the n region, p
This is obtained by forming n-channel MOS transistors in each region. Such CMOS has features such as consuming power only during transient times, being less susceptible to substrate effects, having a large noise margin, and operating over a wide power supply voltage range.

By the way, the following methods are conventionally known as methods for manufacturing CMOS. First, an insulating film is provided on a semiconductor substrate having p-type and n-type conductive regions, and openings are formed by removing the insulating film in each region where the source and drain are to be formed. Subsequently, a polycrystalline silicon film is deposited on the entire surface of the insulating film, and then patterned to form a gate electrode made of polycrystalline silicon and a source/drain electrode pattern in contact with each region of the semiconductor substrate through a portion of the opening. form. Then, in the p-type conductive region, n
By selectively ion-implanting phosphorus as a type impurity,
Boron ions as a p-type impurity are selectively implanted into the n-type conductive region. At this time, impurities are injected through the openings of the insulating film in each region and the source and drain electrode patterns made of polycrystalline silicon extending over a part of these openings, and the p-type regions are filled with n-type impurity diffusion layers and n-type impurity diffusion layers. A p-type impurity diffusion layer is formed in the type region. After that, heat treatment is performed to activate each diffusion layer to form an n ⁺ type source and drain in the p type region and a p ⁺ type source and drain in the n type region, and then a CVD-SiO ₂ film is formed on the entire surface. etc. to create CMOS.

In the conventional method described above, not only the gate electrode but also the source and drain electrode patterns are formed using polycrystalline silicon, so there are fewer steps than when forming source and drain electrodes of Al etc. through contact holes. It has the advantage of being able to alleviate the problem and realize good multilayer wiring. However, in this method, when forming a p ⁺ type or n ⁺ type diffusion layer in each region, source and drain electrode patterns made of polycrystalline silicon are formed in an opening in the insulating film and in a part of this opening. Since impurity ions are implanted into each region through the opening, the depth of the diffusion layer under the source and drain electrode patterns is shallower than the depth of the diffusion layer formed through the opening. For this reason, the source
It becomes impossible to connect the drain electrode and the diffusion layer with a sufficiently good low resistance contact. In order to improve this problem, it is possible to form a deep diffusion layer by increasing the amount of ion implantation in order to make good ohmic contact between the polycrystalline silicon source and drain electrodes and the diffusion layer. Then, diffusion in the lateral direction progresses, and even during heat treatment for activation, re-diffusion in the lateral direction increases, resulting in a disadvantage of short channel effect.

For these reasons, the present inventor has made various studies to overcome the above-mentioned drawbacks, and has created an opening to be used as a source, drain diffusion hole, etc. in an insulating film on a semiconductor substrate having p-type and n-type regions. After depositing a polycrystalline silicon film on the entire surface, the polycrystalline silicon film portion above the p-type region is doped with an n-type impurity, and the polycrystalline silicon film portion above the n-type region is doped with a p-type impurity. Further, the polycrystalline silicon film is patterned to form a gate electrode and a source/drain electrode pattern that is partially in contact with each region through the opening, and then an n-type electrode is injected into the p-type region by, for example, ion implantation. P-type impurities were introduced into the n-type region by the same ion implantation method, and the impurities were also diffused from the source and drain electrode patterns of the impurity-doped polycrystalline silicon. As a result, the impurity diffusion depth under the source and drain electrodes is deep, and the impurity diffusion depth introduced directly from the opening is shallow, making it possible to form sources and drains, suppressing the short channel effect, and suppressing the short channel effect. A semiconductor device including complementary MOS transistors having source and drain electrode patterns connected with good low resistance could be obtained. However, in such a method, the polycrystalline silicon film portion on the p-type region is doped with n-type impurities, the gate electrode, source, and drain electrode patterns on the n-channel transistor side become n-type, and the polycrystalline silicon film on the one-type region is doped with n-type impurities. The silicon film portion is doped with p-type impurities, and the gate electrode, source, and drain electrode patterns on the p-channel transistor side become p-type. For this reason, for example, if each gate electrode of CMOS is made of the same polycrystalline silicon film,
A pn junction is always formed somewhere in the polycrystalline silicon film, interfering with normal operation. Therefore,
In order to make a common connection between the gate electrode on the p channel side and the gate electrode on the n channel side,
Al electrodes etc. must be used. the result,
In order to commonly connect each gate electrode with an Al electrode, it is unavoidable to drill a contact hole, which not only increases manufacturing man-hours but also
This poses an inconvenience that hinders the miniaturization and increase in density of semiconductor devices equipped with this technology, and also causes a decrease in yield. In addition, when polycrystalline silicon used as a gate electrode material is doped with phosphorus, boron, etc., its resistivity decreases compared to undoped polycrystalline silicon, but
It has a high resistance of approximately 1×10 ^-3 Ωcm, and when used as a gate electrode for CMOS, which requires high density and high speed operation,
The time constant becomes larger and the signal propagation speed becomes slower.

Therefore, as a result of further intensive research based on the above knowledge, the present inventor doped impurities corresponding to each region in the polycrystalline silicon film on the semiconductor substrate, then deposited a high melting point metal silicide film, and As described above, these double-structured films were patterned and impurities were introduced to form a diffusion layer. As a result, (1) the short channel effect of each channel is suppressed and the source and drain electrode patterns are connected to the source and drain with good low resistance; (2) the gate, source,
By forming each drain electrode pattern with a double structure film of an impurity-doped polycrystalline silicon film and a high melting point metal silicide film, when the gate electrodes on the p-channel side and the n-channel side are commonly connected, the polycrystalline silicon (3) Abnormal operation caused by internal p-n junctions can be resolved and the device can be driven in normal operation.
A semiconductor equipped with a complementary MOS transistor that achieves high integration and high-speed operation due to various excellent characteristics such as the ability to increase the signal propagation speed of the gate electrode due to the low resistivity of high-melting point metal silicide. We have found a way to manufacture the device.

That is, the present invention provides a method for manufacturing a semiconductor device including complementary MOS transistors on the same substrate.
coating each region of the semiconductor substrate having p-type and n-type conductivity regions with an insulating film; selectively removing a portion of the insulating film to form an opening; After exposing a part of the region, the entire surface is covered with a polycrystalline silicon film, and the polycrystalline silicon film portion on the p-type conductive region is selectively doped with an n-type impurity, and the n-type a step of selectively doping a portion of the polycrystalline silicon film on the conductive region with a p-type impurity; a step of covering the doped polycrystalline silicon film with a high melting point metal silicide film; A step of selectively etching the silicide film and the polycrystalline silicon film to expose a portion of the opening, forming a source and drain electrode pattern in contact with the gate electrode and a portion of each region, and diffusing the opening. Impurities having conductivity types opposite to those of the p-type and n-type regions are introduced into the p-type and n-type regions using the holes, and impurities doped into the polycrystalline silicon film of the source and drain electrode patterns are introduced through the openings. The method is characterized by comprising a step of forming source and drain impurity diffusion layers by diffusing into each region.

As the semiconductor substrate used in the present invention, for example, n
For example, a type or p-type silicon substrate in which a well of a conductivity type opposite to that of the substrate is selectively formed is included.

In the present invention, impurities doped into the polycrystalline silicon film include n-type impurities such as phosphorus and arsenic;
Examples include p-type impurities such as boron. Such impurity doping methods include, for example, ion implantation, or various methods using impurity-doped glass films such as phosphorus-doped glass films (PSG films), arsenic-doped glass films (AsSG films), and boron-doped glass films (BSG films) as a diffusion source. Examples include a method of doping a polycrystalline silicon film with an impurity from the above diffusion source by coating a crystalline silicon film at a predetermined location and subjecting it to heat treatment. However, the ion implantation method is useful because the amount of impurity doped can be easily and precisely controlled.

Examples of the high melting point metal silicide used in the present invention include silicides such as molybdenum, tungsten, tantalum, and niobium, and these high melting point metal silicide films can be formed by sputtering, vapor deposition, and CVD.

Examples of means for introducing impurities into each region of the semiconductor substrate in the present invention include an ion implantation method and a method of introducing an impurity-doped glass film as a diffusion source. In particular, when the latter method of introducing impurities is adopted, it is necessary to use a glass film doped with a smaller amount of impurity than the amount of impurity doped into the polycrystalline silicon film as a diffusion source. In addition,
When introducing impurities, an ion implantation method is advantageous because it can accurately introduce the amount of impurities from the viewpoint of reducing the depth of the diffusion layer other than those in contact with the source and drain electrode patterns.

Next, embodiments of the present invention will be described with reference to the drawings.

Example [1] First, as shown in FIG. 1a, boron is selectively ion-implanted into an n-type silicon substrate 1.
After forming the semiconductor substrate 3 with the mold well 2 formed,
A field oxide film 4 is formed by selective oxidation to separate the p-channel and n-channel transistor formation regions, and a silicon oxide film 5 is formed in each transistor formation region by thermal oxidation, followed by selective etching of the oxide film 5. Then, four openings 6...6 were provided to expose each area. Thereafter, a polycrystalline silicon film 7 having a thickness of about 1000 Å was deposited on the entire surface by a vapor phase growth method using SiH ₄ (as shown in FIG. 1b).

[]Next, 10 21 cm ^-3 ions of phosphorus were selectively implanted into the polycrystalline silicon film 7 portion on the p-type well 2 under the condition of an acceleration voltage of 30 keV, while the polycrystalline silicon film 7 portion on the silicon substrate 1 was implanted with 10 ²¹ cm -3 ions. Boron ions were selectively implanted at 10 ²¹ cm ^-3 at an acceleration voltage of 20 keV (as shown in Figure 1c). After doping with impurities, MoSi ₂ is deposited on the entire surface of the polycrystalline silicon film 7 by sputtering in an Ar atmosphere to a thickness of approximately
A 2000 Å MoSi ₂ film 8 was deposited (as shown in FIG. 1d).

[] Next, a resist pattern (not shown) is provided on the MoSi ₂ film 8 by photoetching, and using this resist pattern as a mask, the MoSi ₂ film 8 and the impurity-doped polycrystalline silicon film 7 are sequentially selectively etched by a plasma etching method. Removed. At this time, as shown in FIG. 1e, gate electrodes 7 ₁ , 8 ₁ and 7 2 having a double structure made of MoSi ₂ and impurity-doped polycrystalline silicon are formed in each region of the p-type well 2 and the n-type silicon substrate ₁ . 8 ₂ , opening 6...6
Source electrode patterns 7 ₃ , 8 ₃ and 7 ₄ , 8 ₄ and common drain electrode patterns 7 ₅ , 8 ₅ were formed, which were in contact with a part of each region via. Subsequently, the silicon oxide film 5 was etched using the gate electrodes 7 ₁ , 8 ₁ and 7 ₂ , 8 ₂ as masks to form a gate oxide film 9 (as shown in FIG. 1e). Note that the gate electrodes 7 ₁ , 8 ₁ and 7 ₂ , 8 ₂ are patterned so as to be commonly connected outside the transistor formation region, as shown in FIG. 2, and the source electrode patterns 7 ₃ , 8 ₃ and 7 ₄ , 8 ₄ and the common drain electrode patterns 7 ₅ , 8 ₅ were patterned to extend outside the device region as shown in FIG.

[] Next, the n-type silicon substrate 1 is masked with a resist film, and arsenic as an n-type impurity is applied to the p-type well 2 side at an acceleration voltage of 50 keV and a dose of 3×.
After ion implantation under the conditions of 10 ¹⁵ cm ^-2 , the resist film was removed, the p-type well 2 was masked again with a resist film, and boron as a p-type impurity was implanted on the n-type silicon substrate 1 side at an accelerating voltage of 30 keV. Ion implantation was performed at a dose of 1.5×10 ¹⁵ cm ⁻² . At this time, a shallow n + -type diffusion layer of 0.3 μm is formed in the p-type silicon substrate 2 portion exposed from the openings 6 , 6 , while a 0.3 μm shallow n ⁺ type diffusion layer is formed in the n-type silicon substrate 1 portion exposed from the openings 6 , 6 . A shallow p ⁺ type diffusion layer of μm was formed. Then 20 min in _N2 atmosphere at 1000 °C
Heat treated for minutes. At this time, phosphorus is removed from the phosphorus-doped polycrystalline silicon films 7 ₃ and 7 ₅ , which are part of the source and drain electrode pattern, which are in contact with a part of the p-type well 2 through the openings 6 and 6 on the p-type well 2 side. is diffused into the well 2, while a boron-doped polycrystalline silicon film 7, which is a component of the source and drain electrode patterns, is in contact with a part of the silicon substrate 1 through the openings 6, 6 on the n-type silicon substrate 1 side. ₄ and ₇₅ , boron was diffused into the silicon substrate 1, and the shallow n ⁺ type diffusion layer and p ⁺ type diffusion layer formed by the ion implantation were activated. As a result, as shown in FIG. 1f, the depth of the portion exposed from the openings 6, 6 in the p-type well 2 is 0.3 μm, the source electrode patterns 7 ₃ , 8 ₃ and the common drain electrode patterns 7 ₅ , 8 ₅ The depth of contact with
An n ⁺ -type source 10 and drain 11 were formed with a thickness of 0.7 mm and were self-aligned with respect to the gate electrodes 7 ₁ and 8 ₁ to fabricate an n-channel transistor. Further, as shown in FIG. 1f, the depth of the portion exposed from the openings 6, 6 in the n-type silicon substrate 1 is 0.3 μm, and the source electrode pattern 7 is
₄ , 8 ₅ , p ⁺ type source 12 and drain 13 are formed with a depth of 0.7 μm in contact with the common drain electrode patterns 7 ₅ , 8 ₅ and self-aligned with the gate electrodes 7 ₂ , 8 ₂ . A p-channel transistor was fabricated.

[] Next, a CVD-SiO ₂ film 14 was deposited on the entire surface to manufacture a semiconductor device having a CMOS on the same body (as shown in FIG. 1g).

The CMOS of the obtained semiconductor device is a channel,
Source 10 on the transistor side of the p-channel,
12, drains 11 and 13 are both gate electrodes 7
_The source electrode patterns 7 _{3 ,} 8 ₃ and ₇ are formed in self-alignment with respect to the source electrode patterns 7 ₃ , 8 1 and 7 2 , 8 ₂ and can suppress the short channel effect.
₄ , 8 ₄ and the common drain electrode patterns 7 ₅ , 8 ₅ are sufficiently deep at 0.7 μm, so that the source,
Each electrode could be connected to the drain with low resistance. Further, gate electrodes 7 ₁ , 8 ₁ and 7 ₂ , 8 ₂ ,
The source electrode patterns 7 ₃ , 8 ₃ and 7 ₄ , 8 ₄ and the drain electrode patterns 7 ₅ , _{8 5} are made of a double structure film of an impurity-doped polycrystalline silicon film and a MoSi ₂ film. Even if 8 _1, 7 ₂ , and 8 ₂ are connected in common, the MoSi ₂ film has good ohmic contact with the polycrystalline silicon film, resulting in a pn junction generated inside the polycrystalline silicon film doped with different impurities. This eliminates abnormal operation and enables normal operation. Furthermore, the MoSi ₂ film is highly resistant to oxidation and can be lowered in resistance, making it possible to achieve high-speed operation.

As detailed above, according to the present invention, the short channel effect of each channel is suppressed, and the source and drain electrode patterns are connected to the source and drain with good low resistance.
When the gate electrodes on each channel side are commonly connected, the abnormal operation caused by the formation of a pn junction due to the use of a polycrystalline silicon film doped with different impurities as the gate electrode can be prevented by using a high melting point metal silicide. It is possible to solve this problem by changing the structure and improve the increase in manufacturing man-hours and decrease in yield due to common connection between gate electrodes using aluminum electrodes, etc.
A complementary type that has various excellent characteristics such as the ability to increase signal propagation speed by lowering the specific resistance of the gate electrode, source, and drain electrode patterns, and achieving high reliability, high integration, and high-speed operation. A method for manufacturing a semiconductor device including a MOS transistor can be provided.

[Brief explanation of drawings]

FIGS. 1a to 1g show embodiments of the present invention.
FIG. 2 is a cross-sectional view showing the manufacturing process of a semiconductor device equipped with CMOS, and FIG. 2 is a plan view of FIG. 1g. 1...n-type silicon substrate, 2...p-type well,
3... Semiconductor substrate, 4... Field oxide film, 6
...Opening, 7...Polycrystalline silicon film, 8...
MoSi ₂ film, 7 ₁ , 8 ₁ and 7 ₂ , 8 ₂ ... gate electrode,
7 ₃ , 8 ₃ and 7 ₄ , 8 ₄ ... source electrode pattern,
7 ₅ , 8 ₅ ... common drain electrode pattern, 9 ...
Gate oxide film, 10, 12... Source, 11, 1
3...Drain, 14...CVD-SiO ₂ film.

Claims (1)

[Claims] 1. In manufacturing a semiconductor device including complementary MOS transistors on the same substrate, there is a step of coating an insulating film on each region of a semiconductor substrate having p-type and n-type conductive regions, and a step of coating one of the insulating films. a step of selectively removing a portion of the substrate to form an opening and exposing a portion of each region of the substrate, and then covering the entire surface with a polycrystalline silicon film; A step of selectively doping a silicon film portion with an n-type impurity and selectively doping a polycrystalline silicon film portion on an n-type conductive region with a p-type impurity, and a step of doping the polycrystalline silicon film after doping. A step of coating a high melting point metal silicide film thereon, selectively etching the high melting point metal silicide film and the polycrystalline silicon film to expose a part of the opening, and forming a gate electrode and a part of each of the regions. forming source and drain electrode patterns in contact with the source and drain electrode patterns, and introducing impurities of opposite conductivity type into the p-type and n-type regions by using the openings as diffusion holes; a step of diffusing impurities doped into the polycrystalline silicon film into each region through the opening to form source and drain impurity diffusion layers. .