JPH03102875A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable decreases in large current and increases in operating current and threshold voltage absolute value by making a gate insulating film in the vicinity of a drain thicker than a gate insulating film adjacent to the source part in a polycrystalline SiMIS type field effect transistor. CONSTITUTION:SiO2 102 is formed and polycrystalline Si is deposited on a polycrystalline Si substrate 101. A gate electrode 103 is formed by phosphorus diffusion and polycrystalline Si patterning, and SiO2 to become a gate insulating film 104 is deposited. Next, a three-layer film of first polycrystalline Sia), SiO2 106 and second polycrystalline Si107 (a) is formed. After deposition of SiO2 109, the part to serve as a channel region 105 (a is coated with resist 110, and B.F2 ions are implanted into the part to serve as a source.drain 108. The resist 110 and SiO2 109 are removed to etch the natural oxide film of the surface of the second monocrystalline Si 107. And the wafer is dipped in hydrogen etching solution. Thereafter, the source.drain region 108 is provided with electrodes and annealed to complete the process.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, the present invention relates to a semiconductor device and a method for manufacturing the same, and in particular, to improving the reliability of the device regardless of the device structure of a polycrystalline SiM I S field effect transistor. The present invention relates to a method of manufacturing a semiconductor device suitable for thinning a channel region while maintaining the same, and a semiconductor device suitable for preventing an increase in leakage current due to thinning of a gate insulating film.

[Conventional technology]

As discussed in JP-A No. 63-107068, transistor characteristics such as a decrease in leakage current, an increase in operating current, and a decrease in the absolute value of the threshold voltage of a polycrystalline SiMIS field effect transistor have been improved. In order to improve this, it is effective to reduce the thickness of the polycrystalline Si film in the channel region. In addition, in order to reduce the resistance of the source and drain diffusion layers and increase the mutual conductance, it is necessary to
It is desirable that the film thickness of the drain region be thick. Furthermore, in order to further reduce leakage current, which is one of the major problems of polycrystalline S i M I S type field effect transistors, it is effective to relax the electric field near the drain. For this purpose, the thickness of the gate insulating film must be
The thicker the better.

[Problem to be solved by the invention]

FIG. 8 shows an example of a polycrystalline S i M I S type field effect transistor in which only the channel region 806 is thinned.

First, a single crystal Si substrate 801 is thermally oxidized to form SiOz80.
form 2. Next, after forming source and drain regions 807, polycrystalline Si that will become the channel region 806 is deposited and patterned. Next, after forming a gate insulating film 805, a gate electrode 803 is formed. This is an example in which a gate insulating film 805 and a channel region 806 are formed before a gate electrode 803 is formed. However, as shown in FIGS. 9(a) and 9(b), in the device structure in which the gate electrodes pi 903 (a) and 903 (b) are formed first, the source and drain regions 907 are connected to the channel region 906. (a) Upper or gate insulating film 90
5 (b) will be patterned on. However, if the source and drain regions 907 are patterned on the channel region 906 (a) by dry etching, the film thickness of the channel region 906 (a) cannot be controlled.

Further, when patterning is performed on the gate insulating film 905(b), there is a problem that the gate insulating film 905(b) is damaged or contaminated, resulting in deterioration of reliability.

In addition, H
In the wet etching method using a mixed solution of F and HNOa, the gate insulating film 905 (b
) had problems such as a low etching selectivity.

Therefore, in order to make the thickness of the channel region 906 thinner than the thickness of the source and drain regions 907, there is a constraint that the channel region 906 must be formed before the gate electrode 903. The range of applications for IS type transistors has been limited.

In addition, in order to further reduce leakage current, which is one of the major problems of polycrystalline SiM I S type field effect transistors, the thickness of the gate insulating films 805 and 905 is increased to reduce the electric field near the drain. It is effective to alleviate this. However, increasing the thickness of the gate insulating films 805 and 905 poses a problem in that the on-current decreases. [Means for Solving the Problems] In order to solve the above problems, it is necessary to use a method that has an etching selectivity of about 100 times or more between the insulating film and polycrystalline Si, and that causes extremely little damage to the underlying layer. , or by selectively etching only the polycrystalline Si above the gate insulating film. in particular,
Polycrystalline Si/SiOz or polycrystalline Si/SiaN+
The etching selectivity is infinite, and boron-doped S
Selective etching of polycrystalline Si using an aqueous solution containing hydrazine, which has an etching selectivity of 10 times or more for i/non-doped Si, or low-temperature drying, which has an etching selectivity of polycrystalline Si/SiOz of 100 times or more and causes extremely little damage to the underlying layer. This can be achieved by applying an etching method.

Furthermore, in order to prevent an increase in leakage current due to thinning of the gate insulating film, this can be achieved by thickening only the gate insulating film near the drain.

[Effect]

According to the present invention, regardless of the device structure of a polycrystalline SiM I S type field effect transistor, only the channel region can be thinned while maintaining the reliability of the device. This improves transistor characteristics by reducing leakage current, increasing operating current, and increasing the absolute value of threshold voltage without degrading mutual conductance. [Example] A first example of the present invention will be described below with reference to FIG. Example 1 First, after thermally oxidizing a single crystal Si substrate 101 (P-type 10Ω/aI1) to form 200 nm SiOzl02,
Polycrystalline Si of 200 nm is deposited by low pressure chemical vapor deposition method (hereinafter referred to as LPCVD method). Then 875℃
After performing phosphorus diffusion for 30 minutes, polycrystalline Si was etched using well-known lithography and dry etching techniques.
A gate electrode 103 is formed by patterning. Next, SiOz, which will become the gate insulating film 104, is processed by LPCV.
Deposit 30 nm using method D. Then, under the following conditions,
First polycrystalline Si (30nm)/Sioz (2nm)
/ Form a three-layer film of second polycrystalline Si (150 nm). First, a Si substrate 101 is inserted into a normal LPGVD device. Reduce pressure to 1 mmTorr. When the Si substrate 101 reaches a predetermined temperature, SiHa gas is introduced (pressure = 0.6 Torr) into the first polycrystal S.
Deposit 30 nm of i 105(a). first polycrystalline S
After the deposition of i105 (a) is completed, the inside of the apparatus is reset to zero.
．． Reduce pressure to 1 nmTorr. Next, introduce oxygen (pressure I Torr) into the first polycrystalline Sil05
(a) Oxidize the surface to form about 2 nm of SiOzl06. Next, 0. After reducing the pressure to 1 mTorr, SiH4 gas was introduced again (pressure = 0.6 Torr).
r) Then add the second polycrystalline Sil07 (a) to 150n
m deposits. In this example, the first polycrystalline Si 105 (a) (30 nm)/Sift 10
6 (2 nm)/second polycrystalline Sil07 (a) (150
A three-layer film of 100 nm) was formed, but the first polycrystalline Si105
(a) After the formation, the Si substrate 101 is taken out of the device, a natural oxide film is formed, and the second polycrystalline Sil0 film is formed again in the LPGVD device.
Almost the same structure was obtained by forming 7(a).

Next, 20 nm SLft109 was formed by LPCVD method.
After depositing resist 110, the portion that will become the channel region 105(a) is covered using a lithography technique. Next, B-F x is applied to the portion that will become the source and drain 108.
Ion implantation is performed at 20 KeV. In this example,
The impurity concentration of the source and drain 108 was set to 5×10 19 impurities/cm 3 . Furthermore, although BF2 was used as the dopant in this example, it is of course possible to use B (boron). Next, after removing the resist 110 and Sift 109, the natural oxide film on the surface of the second single crystal Si 107 is etched with an HF aqueous solution, and the wafer is immersed in a hydrazine etching solution. What is important here is that the second polycrystalline Si10
7. The oxygen concentration in the cleaning water after etching the natural oxide film on the surface should be 500 ppb or less. When the oxygen concentration in the cleaning water is set to 500 ppb or more, a natural oxide film of about several λ is formed again on the surface of the second polycrystalline Si 107 during wafer cleaning. In this state, the second polycrystalline Sil07
Even if etching is performed, the natural oxide film acts as a mask and the second
Is it not possible to etch polycrystalline Sil07 (a)?
Or even if it is possible, the etching will be uneven.

Therefore, it is desirable that the oxygen concentration in the wafer cleaning water be 500 PPb or less.

Here, the temperature of the hydrazine etching solution was maintained at 50° C., and etching was performed for 20 minutes.

Hydrazine etching solution has a very slow etching rate for polycrystalline Si doped with poron, and also
Since the channel region 105 (a) is not etched as shown in FIG. 1(d), the first polycrystalline Si 10
The film thickness is 5. The source and drain 108 regions are the first
The film thickness is approximately the sum of the polycrystalline Sil05 and the second polycrystalline Sil07. In addition, here, the source and drain regions 1
It is also important to set the boron concentration of 08 to 5×101δ particles/cm 3 or more, and to perform selective etching of polycrystalline Si with a hydrazine solution after boron implantation and before heat treatment.

The etching rate of polycrystalline Si with hydrazine solution depends on the boron concentration in Si, and is 5×IQ18 pieces/c
Below Ij, the difference in etching rate with non-doped Si is small and selectivity is not achieved. Therefore, the boron concentration is 5
It is preferable that the number is 10" pieces/cm3 or more. Furthermore, if heat treatment is performed before selective etching with a hydrazine solution, boron in the second polycrystalline Sil07 (b) will diffuse into the upper part of the channel region 105 (a). In addition, since the boron concentration on the surface of the second polycrystalline Sil07 (b) becomes thinner due to heat treatment, the etching rate in that area increases, making it difficult to achieve the desired film thickness. Therefore, the heat treatment for activating boron is preferably performed after hydrazine etching. In this example, after performing selective etching with a hydrazine solution, the heat treatment is performed at 900° C. in a N2 atmosphere. , 30 minutes of heat treatment was performed to activate boron.

After that, using a known technique, the source and drain regions 1 are
An electrode is provided at 08, and H2 annealing is performed at 450''C for 30 minutes to complete the formation of the semiconductor device of the present invention.

The polycrystalline Si. The M I S type transistor has source and drain regions 40 shown in FIG.
Compared to a normal polycrystalline SiM I S type transistor that does not have a thick film, the transconductance has increased approximately twice. In addition, in this example, using SiHa, the first polycrystalline Sil05 (a) and the second polycrystalline Sil0
7 (a) was formed, but S izHB, S
Good results were also obtained using isHa.

Example 2 A second embodiment of the present invention will be described using FIG. 2.

First, as in Example 1, a single crystal Si substrate 201 (P type,
10Ω・aI1), a thermal oxide film 202, a gate electrode 2
03 and a gate insulating film 204 are formed. Then,
The first polycrystalline Si207 was 100n using the LPCVD method.
Deposit 10 nm of mSiOz 209. Next, the desired region 207 (a) is covered with a resist 210 using a photolithography technique, and BF2 is ion-implanted at 80 KeV.

Resist 210, as described in Example 1, is then applied.
After removing the SiO layer 209, a non-doped region of the first polycrystalline Si 207 is removed by hydrazine etching. 207(a)
selectively etched.

Etching with hydrazine is wet etching, so it does not damage the gate insulating film. Furthermore, since the selection ratio between polycrystalline Si and Sing is infinite, the underlying gate insulating film is not etched at all, resulting in a shape as shown in FIG. 2(b).

Next, the second polycrystalline S which will become the channel region 205 (a)
Deposit i205 to a thickness of 10 nm using the LPCVD method. After that, using a known technique, the source and drain regions 208 are
Electrodes are provided on the substrate, and H2 annealing is performed at 450° C. for 30 minutes to complete the formation of the semiconductor device of the present invention. The polycrystalline SiM I S type transistor formed in this example has source and drain regions 407 shown in FIG.
The mutual conductance has increased approximately twice as much as that of a normal polycrystalline SiM I S type transistor that does not have a thick film. Furthermore, the dielectric breakdown life of the gate insulating film 204 over time was measured, and it was confirmed that the reliability of the device did not deteriorate.

Example 3 A third example of the present invention will be explained using FIG. 3. First, as in the example above, a single crystal Si substrate 301 (P type,
10Ω・c! 1) On top, a thermal oxide film 302 and a gate electrode 3
03, gate insulating film 304, and first polycrystalline Si30
5 (30 nm)/SiOz306 (2 nm)/second polycrystalline Si307 (150 nm) is formed. Then,
SiOz309 is converted into second polycrystalline Si using LPCVD method.
Deposit 10 nm on 307. Next, channel region 3
05(a) is covered with a resist 310, and BFz ions are implanted at 25 KeV into the regions that will become the source and drain 308. In this embodiment, the impurity concentration in the source and drain regions was set to 5×10 1”/cm 3 .

Next, after removing the resist 310, heat treatment is performed in an oxygen atmosphere at 900° C. to form SiOz 311 on the second polycrystalline Si 307. The film thickness of the SiOz311 described above is due to the difference in impurity concentration in the underlying layer, so the SiO2311(b) on the source and drain regions 308 is thicker than the channel region 307.
(a) Above Si()z 311 It is thicker than (a). In this embodiment, boron was used as the dopant for the source and drain type 308, but arsenic (As), . Similar results were obtained using phosphorus (P) and antimony (sb).

Furthermore, the film thickness difference of the SiOz 311 can be set to a desired film thickness difference by changing the impurity concentration of the source and drain 308 and the oxidation method. Specifically, the larger the difference in impurity concentration between the source/drain region 308 and the channel region 307 (a), and the lower the oxidation temperature, the larger the difference in the film thickness of the SiOz layer 311 becomes. Furthermore, even in an oxidizing atmosphere, the difference in film thickness of Si()z311 can be made larger by using wet oxidation than by dry oxidation. In this example, the film thickness of SiC)z311(b) on the source and drain 308 is the same as that of SiOz311 on the second polycrystalline Si doped region 307(a).
6, which was set to be approximately twice the film thickness in (a),
Until the surface of the second polycrystalline Si non-doped region 307(a) is exposed. When SiO2 311 is etched with a hydrofluoric acid aqueous solution, Sift 311 (b) remains only above the source and drain regions 308, as shown in FIG. 2(c). In this example, etching was performed until the surface of the second polycrystalline Si non-doped region 307(a) was drained of water. Next, using the Sing 311 (b) as a mask, the second polycrystalline Si non-doped region 307 (a) is dry etched. In this example, a μ wave excitation type plasma etching apparatus is used for the dry etching of the second polycrystalline Si non-doped region 307 (a), and SFe
was used as the reaction gas, and the temperature of the Si substrate 301 was set to -110°C. According to this method, an extremely thin insulating film 306 of approximately 2 nm is used as an etching stopper, and the second polycrystalline Si non-doped region 2 in the upper part of the channel region 305 (a)
07 (a) can be etched anisotropically. Although etching is possible without cooling the Si plate 301, this method is superior in that it can be etched anisotropically with a high selectivity. Thereafter, as in the first embodiment, electrodes are provided in the source and drain regions 308 using a known technique, and
C. Perform H2 annealing for 30 minutes to complete the formation of the semiconductor device of the present invention. Polycrystalline Si produced in this example
As shown in Fig. 4, the M I S type transistor is
Compared to a normal polycrystalline SiM I S type transistor in which the source and drain regions 407 are not thickened, the mutual conductance can be doubled in a row. Here, what is important in the first and third embodiments of the present invention is that the first polycrystalline Sil05,3
If the film thickness of the insulating film 106, 306 formed between 05 and the second polycrystalline Sil 07, 307 is less than slnm, which is 1 to 3 nm, it will not act as an etching stopper, so the channel region 105 (a ), 305 (
a) is also etched. Moreover, if the thickness is more than 3 nm, the first polycrystalline Sil05, 305 and the second polycrystalline Si
107 and 307 are insulated and electrical continuity cannot be established. Therefore, the insulating films 106, 306
It is desirable that the film thickness is 1 to 3 nm.

In this embodiment, the insulating films 106 and 306 are made of Si.
○2 was used, but similar results were obtained using a thermal nitride film formed by directly nitriding SiaNa or polycrystalline Si formed by the CVD method. Embodiment 4 Next, a fourth embodiment of the present invention will be described using FIG. 5.

As in Example 1, a single crystal Si substrate 501 (P type,
-, ), SiOz 502 and a gate electrode 503 are formed. Next, the first gate insulating film 5 is formed by the LPCVD method.
After depositing 30 nm of SiOz to form 04, S was deposited using well-known lithography and dry etching techniques.
i Pattern Oz504. Then, L.P.
SiO to become the second gate insulating film 505 by CVD method
Deposit Z to a thickness of 15 nm. Next, using the method described in Example 1, the channel region 506 and source region 507 (b
), after forming the drain region 507 (a), in an Nx atmosphere. Heat treatment at 900°C for 30 minutes. Next, using a known technique, electrodes are provided in the source 507(b) and drain 507(a) regions, and 450'C, 3
The invention of the semiconductor device of the present invention is completed by performing H2 annealing for 0 minutes. According to this embodiment, only the electric field near the drain region 507 (a) is relaxed, so the on-current is maintained and the O
Leakage current during FF is reduced by normal polycrystalline S
This was significantly reduced compared to the type transistor (Figure 4).

Furthermore, as shown in FIG. 6, it is known that the leakage current can be reduced by creating an offset structure between the gate electrode 606 and the drain region 607 (a) and relaxing the electric field near the drain region 607 (a). However, the leakage current of the polycrystalline Si MIS transistor with the offset structure greatly depends on the offset length. For this reason,
There is a problem in that the leakage current changes greatly due to misalignment d of the mask for forming the source and drain 607. Also, we need to secure the dimensions for the offset, so
This becomes an obstacle to increasing the degree of integration. However, the polycrystalline S i M I S created in this example
In the type transistor, the leakage current and threshold voltage hardly changed even if there was a mask misalignment d. Furthermore, since there is no need to ensure an offset length, the degree of integration has been greatly improved.

Embodiment 5 Next, an embodiment in which the present invention is applied to a memory cell of a complete CMOS type SRAM will be described with reference to FIGS. 7, 10, and 11. In this embodiment, polycrystalline Si-P channel MOS transistors 1001 and 1002 were used as load elements of inverters constituting memory cells.

First, P on the n-type Si substrate 701 (10Ω・al1)
A well region 702 and an element isolation region 703 are formed using a known technique. Next, using a thermal oxidation method, 20
After forming the gate oxide film 704 with a thickness of 100 nm, the gate electrode 707 of the drive MOS transistor l003 or
．． (a) and transfer MOS transistor 1005 or 10
A connection hole 706 is formed to connect to the diffusion layer 705 of No. 06. Next, using the LPCVD method, a 200 nm
After depositing low resistance polycrystalline Si, 707 (a), 707 (b) and 150 nm of Si○2708, gate electrodes 707 ( a). and constitutes the gate electrode 707 (b) of the transfer MOS transistors 1005 and 1006.

Next, after ion-implanting phosphorus into the low concentration regions of the source and drain, 300nm was implanted using the LPCVD method.
Deposit m Sift. Next, the SiO2 is anisotropically etched using a dry etching method to form a sidewall insulating film 709. Thereafter, arsenic (As) ions are implanted and heat treatment is performed at 900° C. for 10 minutes in an N2 atmosphere to complete the formation of the source and drain. Next, Si○, which will become an interlayer insulating film, is deposited using the LPCVD method.
After depositing 2710 to a thickness of 150 nm, gate electrodes 712 (a), 712 (b), 1101' (a),
1101 (b) and driving nMOS transistor 1
A connection hole 711 is formed to connect the gate electrodes 707 (a) of 003 and 1004. Then LPC
By VD method, 150nm polycrystalline Si and 15n
After depositing m of Si○2, boron ions were implanted. 9
Heat treatment is performed at 00°C for 10 minutes. Next, after removing SiOz, the polycrystalline Si is processed into a predetermined shape using lithography and dry etching techniques to form a polycrystalline Si-P channel MOS transistor 1001.10.
Gate electrode 7 of 02 (a) or 712 (b),
1101 (a) or 1101 (b).

Next, Si○2, which will become the gate insulating film 713, is processed by LPCV.
After depositing 20 nm from one layer using the D method, 90 nm was deposited in an N2 atmosphere.
Heat treatment is performed at 0° C. for 10 minutes. In this example,
In the above formation of SiOz 713, Si was used as a reaction gas.
l{4 and N z O were used.

Next, the drain part diffusion layers 714, 1 of the polycrystalline Si-P channel MOS}-transistors 1001 and 1002 are
Gate electrodes 712 (a), 712 (b), 11 of the inverter facing 103 (a), 1103 (a)
After forming the connection holes 716 and 1102 (a) and 1102 (b) for connecting 01 (a) and 1 of (b), the first polycrystalline (
10 nm) / Si○z (2 nm) / 2nd polycrystal (100
Form a three-layer film of nanometers (nm).

Next, after depositing 15 nm of Sing by the LPCVD method, a polycrystalline Si-P channel MOS transistor 1001
．． 1002 channel region 717, 1105 (a),
1105 Cover the part (b) with a photoresist pattern, and implant boron ions. Next, the non-doped region of the second polycrystalline Si is selectively etched using a hydrazine etching solution. Next, using well-known lithography and dry etching techniques, the three-layer film (first polycrystalline (10nm)/SiOz (2nm)/second polycrystalline (100nm)) is processed into a predetermined shape, and the source 715.
1104 (a), 1104 (b), drain 71
4. Form regions 1103(a) and 1103(b) and common power supply wirings 1106(a) and 1106(b). As shown in this example, polycrystalline Si-P channel MO
Source 715.1 of S transistor 1001.1002
104 (a), 1104 (b), drain 714.
By forming the regions 1103 (a) and 1103 (b) and the common power supply lines 1106 (a) and 1106 (b) in the same layer, the degree of integration can be greatly improved without increasing the number of manufacturing steps. Next. 100n SiOz718 by LPCVD method
After the 13PSG film 71 is deposited, a 13PSG film 71 is deposited by atmospheric pressure CVD.
9 was deposited to a thickness of 300 nm and heated at 900°C for 30 minutes in a N2 atmosphere.
Perform heat treatment for 1 minute. Next, the diffusion layer 70°5 of the transfer MOS transistors 1005 and 1006 and the first layer wiring 72
After forming a connection hole 721 for connection with 0, titanium nitride (TiN) and tungsten (W) are deposited and processed into a predetermined shape using lithography and dry etching techniques. Next, the PSG film 722 was deposited at 400 nm by atmospheric pressure CVD.
m is deposited to form a connection hole 723 for connection to the first layer wiring 720. After this, TiN724, Aα725
is vapor-deposited and processed into a predetermined shape, and this is used as the second layer wiring. After heat treatment at 450° C. for 30 minutes in an Hz atmosphere, a 1 μm thick SigNa film is deposited as a final protective film by plasma CVD and processed into a predetermined shape. Finally, heat treatment is performed at 400° C. for 30 minutes in an Nx atmosphere to complete the formation of the semiconductor device of the present invention. The standby current consumption of the memory cell formed according to this example was as low as 0.02 PA per bit. In addition, channel portions 717.1105(a), 1105 of polycrystalline SiM I S type field effect transistors
(b) Thin film effect and sources 715, 1104
(a), 1104 (b), drain 714, 110
3 (a), 1103 (b), common power supply wiring section 110
Due to the thick film effect of 6 (a) and 1106 (b), (1
) Improvement effects such as an increase in on-current, (2) an improvement in the stability of the high node potential in the memory cell, and (3) a decrease in the soft error rate were obtained. Furthermore, polycrystalline S i M I
Gate electrode 712 of S-type field effect transistor (a)
, 712(b), 1101(a), 1101 (
b), channel regions 717, 1105 (a), 11
Since the structure formed before 05(b) can be applied, the manufacturing process of the memory cell can be simplified and the yield can be improved.

In addition, in this example, the polycrystalline SiM I S type field effect transistor described in Example 1 is used as an SRAM.
was applied to the memory cell of 2000, and realized an extremely small standby current consumption of 0.02 PA/bit. Current consumption is 0
．． It was below OIPA/bit. [Effects of the Invention] According to the present invention, even if the gate electrode is formed before the channel region, it is possible to reduce the thickness of only the channel region while maintaining reliability of device and memory operation. The range of applications for polycrystalline SiM I S field effect transistors has been greatly expanded. In addition, polycrystalline Si
By thickening the gate insulating film only near the drain of an MIS field effect transistor, we were able to significantly reduce leakage current while maintaining on-current.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of the manufacturing process of Example 1 of the present invention. Second
The figure is a sectional view of the manufacturing process of Example 2 of the present invention. FIG. 3 is a sectional view of the manufacturing process of Example 3 of the present invention. Figure 4 is a cross-sectional view of the conventional structure. FIG. 5 is a cross-sectional view of the manufacturing process of Example 4 of the present invention. Figure 6 is a cross-sectional view of the conventional structure. Figure 7 shows
Cross-sectional view of the manufacturing process of Example 5 of the present invention. Figure 8 is a cross-sectional view of the conventional structure. Figure 9 is a sectional view of the conventional structure. FIG. 10 is an equivalent circuit diagram of the memory cell described in Example 4 of the present invention. FIG. 11 shows the polycrystalline S described in Example 4 of the present invention.
A layout diagram of an i M I S type field effect transistor. 101, 201, 301, 401, 501, 601, 7
01,801,901...P-type Si substrate, 102,2
02,302,311,402,502,602,70
3,802,902...thermal oxide film, 103,203,
303,403,503,603,707(a),70
7 (b), 712 (a), 712 (b), 803,
903.1101 (a), 1101 (b)... Gate electrode, 104, 204, 304, 405, 504, 5
05,605,704.7'13,805,905...
・Gate insulating film, 708, 709, 710, 718, 7
19,722... interlayer insulating film, 105,207,30
5...first polycrystalline Si. 106,306...Ultra-thin insulating film, 107,205,307...Second polycrystalline Si,
108,208,308,407,507,607,7
14,715,807,907,ILO3 ('a)
, 1103(b), 1104(a), 1104(b)
...source, drain region, 105(a), 205
(a), 305 (a), 406, 506, 606
, 717,806, 906.1105(a),
1105 (b)--channel region, 702...P
Well region, 703... Element isolation region, 721...
1st layer wiring, 724, 725... 2nd layer wiring, Figure ￥, z 躬(b) Kuzu 4 Figure y5 (＾冫Fig. To Sanwa Station Manbun 8/6 ++-ne) L Nesei 3θ7 Nezu de L I declination area (L)

Claims (1)

[Scope of Claims] 1. A semiconductor device in a polycrystalline Si MIS field effect transistor, characterized in that a gate insulating film near the drain is thicker than a gate insulating film in contact with the source. 2. A step of forming a first insulating film on the surface of the conductor or semiconductor, a step of forming a first silicon film on the first insulating film, and a step of forming a second insulating film on the first silicon film. a step of forming a second silicon film on the second insulating film; a step of doping impurities from a desired region of the second silicon film; 1. A method of manufacturing a semiconductor device, comprising at least a step of selectively etching an undoped region. 3. Forming a first insulating film on the surface of the conductor or semiconductor, forming a first silicon film on the first insulating film, and removing impurities from a desired region of the first silicon film. comprising at least the steps of doping, selectively etching undoped regions of the first silicon film, and forming a second silicon film on the first silicon film. A method for manufacturing a semiconductor device, characterized by: 4. Forming a first insulating film on the surface of the conductor or semiconductor, forming a first silicon film on the first insulating film, and forming a second insulating film on the first silicon film. a step of forming a second silicon film on the second insulating film; a step of doping impurities from a desired region of the second silicon film; a step of thermally oxidizing the surface to form an oxide film; a step of wet-etching the oxide film to selectively expose only the surface portion of the undoped region of the second silicon film; 1. A method of manufacturing a semiconductor device, comprising at least the step of dry etching an exposed portion of a silicon film. 5. The method of manufacturing a semiconductor device according to claim 2 or 4, wherein the second insulating film has a thickness of 1 to 3 nm. 6. The impurity doped into the second silicon film described in claim 2 and the first silicon film described in claim 3 contains a boron (B) element, and The method of manufacturing a semiconductor device according to claim 2 or 3, wherein the selective etching of the silicon film is performed with an aqueous solution containing hydrazine, and the underlying insulating film is used as an etching stopper. 7. Doping the Si film by ion implantation method,
and the impurity concentration of boron (B) in the silicon film is 5×1
7. The method of manufacturing a semiconductor device according to claim 6, wherein the number of semiconductor devices is 0^1^5 pieces/cm^3 or more. 8. Claim 1, characterized in that the second silicon film described in Claim 2 and the first silicon film described in Claim 3 are selectively etched before heat treatment. 6. A method for manufacturing a semiconductor device according to item 6. 9. Claims characterized in that dry etching of the second silicon film is performed by maintaining the substrate temperature below room temperature, using SF_6 as a reaction gas, and using the second insulating film as an etching stopper. 5. The method for manufacturing a semiconductor device according to item 4. 10. The first silicon film described in claims 2 and 4 and the second silicon film described in claim 3 have a film thickness of 50 nm or less. Claim 2, 3, or 4
A method for manufacturing a semiconductor device according to section 1. 11. A method for manufacturing a polycrystalline Si MIS field effect transistor, including the method for manufacturing a semiconductor device according to claims 2, 3, and 4. 12. Polycrystalline SiMI described in claim 1
Static random access memory using S-type field effect transistors as load elements. 13. A static random access memory using a polycrystalline Si MIS field effect transistor in which the thickness of the source region and drain region is larger than the thickness of the channel region as a load element. 14. A common power supply wiring for an intra-cell array of the above-mentioned static random access memory, produced using the method for manufacturing a semiconductor device according to claims 2, 3, and 4.