JPH06268225A - Semiconductor device - Google Patents

Abstract

PURPOSE:To control a parasitic transistor, and also to suppress the leakage current generating between a source and a drain by a method wherein a second conductivity type impurity layer region is extended containing the lower region of the outermost circumferential part of a semiconductor active region layer. CONSTITUTION:A pair of first conductivity type impurity diffusion regions 4 and 5, which are separated in the prescribed distance from the semiconductor active region layer, formed through an insulating film 2, a channel region pinched by the above-mentioned pair of diffusion regions 4 and 5, and a gate electrode 7, which is formed on the channel region through a gate insulating film 6, are provided on the surface of a semiconductor substrate 1. Second conductivity type impurity layer regions 15 and 16 are formed on the surface of the semiconductor substrate 1 under the region other than the semiconductor active region, and the second conductivity type impurity layer regions 15 and 16 are extended in such a manner that the lower part region of the outermost circumferential part of the semiconductor active regionlayer is included. As a result, a parasitic transistor is suppressed, and the generation of a leakage current can also be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a MOS film formed on a silicon film (SOI film) formed on an insulating film, and more particularly to a semiconductor device having improved transistor characteristics.

[0002]

2. Description of the Related Art In recent years, a MOS transistor formed on an SOI film has attracted attention as a basic element of an ultrafine device. The reason for this is that, in particular, when the SOI film is thinned so that the entire channel region is depleted in the operating state,
Due to improved characteristics such as improved punch-through resistance, reduced punch-through effect, and increased current, compared to MOS transistors fabricated on a silicon single crystal substrate (IEEE, ED-Vol.36, No.3, p493,1989).

On the other hand, from a process point of view, there is an advantage that lateral separation between elements by a selective oxidation method can be easily achieved because the SOI film thickness is thin. 5A and 5B are sectional views showing the element structure of this type of semiconductor device. 5A is a sectional view in the source / drain direction, and FIG. 5B is a sectional view immediately below the gate electrode in a direction perpendicular to the source / drain direction.

In the figure, 1 is a silicon substrate, 2 is an insulating film, 3 is an SOI film, 4 is a source diffusion layer region, 5 is a drain diffusion layer region, 6 is a gate oxide film, 7 is a gate electrode, 8 is a field oxide film. , 9 are element isolation end regions.

As a result of examining element characteristics of such an element,
The following problems were found to occur. That is, when the element isolation is performed using the selective oxidation method, the element isolation end region 9
In the above, a parasitic transistor was generated, which caused deterioration of the subthreshold coefficient (S coefficient).

As a method of suppressing the generation of such a parasitic transistor at the element isolation end, for example, a method of ion-implanting a channel stopper into a thin SOI film at the element isolation end, or a substrate (back gate) bias is used. A method of applying the voltage may be considered.

However, in the former case, as the ion implantation amount of the channel stopper is increased, the leak current between the source and the drain is increased, which causes a new problem of degrading the device performance.

In the latter method, the complementary type (CM
When the circuit is configured by OS), the back gate bias needs to be taken for each of the NMOS and the PMOS, and there is a problem that the structure becomes complicated such that an external power source is additionally required.

[0009]

As described above, in the conventional thin film SOI device, the subthreshold coefficient (S coefficient) is deteriorated or the leakage current between the source and the drain is caused by the generation of the parasitic transistor at the element isolation end. It is difficult to easily obtain the original excellent performance of the thin film SOI device due to the increase in the number of devices and the complicated structure.

The present invention has been made in order to solve the above problems, and an object of the present invention is to suppress parasitic transistors without complicating the element structure and to sufficiently prevent leakage between the source and drain. It is an object of the present invention to provide a semiconductor device that can be suppressed and can sufficiently bring out the element performance.

[0011]

In order to solve the above problems, the present invention provides a pair of first conductivity type impurities which are separated by a predetermined distance from a semiconductor active region layer formed on the surface of a semiconductor substrate with an insulating film interposed therebetween. In a semiconductor device having a diffusion region, a channel region sandwiched between the pair of diffusion regions, and a gate electrode formed on the channel region via a gate insulating film, a region outside the semiconductor active region is formed. A second-conductivity-type impurity layer region is formed on the surface of the semiconductor substrate, and at least the second-conductivity-type impurity layer region extends so as to include a lowermost outermost region of the semiconductor active region layer. That is the summary.

[0012]

According to the present invention, a high-concentration impurity layer region different from the impurity type of the source / drain diffusion region is formed on the surface of the underlying support substrate in the region outside the semiconductor active region layer in which an SOI device is manufactured, and at least this impurity is formed. The layer region extends to include the lowermost region of the outermost periphery of the semiconductor active region layer.

With this, it is not necessary to ion-implant a channel stop into the SOI film at the element isolation end, and while preventing generation of a parasitic transistor, leakage between the source and drain accompanying an increase in the ion implantation amount of the channel stop. It is possible to suppress an increase in current.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a schematic configuration of a semiconductor device according to an embodiment of the present invention. 2A to 2C and 3A to 3C are process cross-sectional views schematically showing a method for manufacturing an N-channel SOI MOS transistor according to an embodiment of the present invention.

First, oxygen ions are applied to the single crystal silicon substrate 1, for example, an acceleration voltage of 150 KeV and a dose of 0.4 × 10.
^{Implanting is performed} at ¹⁸ cm ^-2 and annealing is performed at 1300 ° C. for 6 hours to form a SiO ₂ layer 2 having a thickness of 500 Å and an SOI film 3 having a thickness of 2000 Å (FIG. 2A).

Next, an oxide film not shown is formed on the surface of the SOI film 3 with a thickness of 2000 liters, for example, and then the oxide film is removed with an ammonium fluoride aqueous solution. At this stage, the SOI film thickness is reduced to 1000 Å.

Next, a thermal oxide film 10, a silicon nitride film 11 and a polycrystalline silicon film 12 are formed on the surface of the SOI film in the order of, for example, a thickness of 500Å / 1500Å / 4000Å, and thereafter, the element is formed by a well-known lithography. The polycrystalline silicon 12 in the active region was patterned as shown in FIG.

After that, as shown in FIG. 2C, the polycrystalline silicon is entirely oxidized by the hydrogen combustion oxidation method to obtain a thickness of 800.
A thermal oxide film 13 of 0Å was formed. The lateral width of the thermal oxide film 13 formed by this oxidation is slightly larger than the pattern width of the polycrystalline silicon 12. Next, using the thermal oxide film 13 as a mask, the silicon nitride film 11 was etched and removed. Thereafter, using the oxide film 13 as a mask, boron ions 14 are ion-implanted at an acceleration voltage of 100 KeV and a dose amount of 5 × 10 ¹² cm ⁻² to form a boron impurity layer 15 on the silicon substrate.

Next, as shown in FIG. 3A, the thermal oxide film 13 is formed.
Was completely removed with an aqueous solution of ammonium fluoride. Then Fig. 3
As shown in (b), the silicon oxide film 11 was used as a mask to oxidize the entire SOI film 3 in the field region to form a field oxide film 8 by the hydrogen combustion oxidation method. The field oxide film 8 is formed so as to penetrate under the silicon nitride film 11 by oxidation.

However, as described above, since the thermal oxide film 13 is formed slightly larger, the silicon nitride film 11 is formed.
Is also greatly patterned, and the problem of dimensional conversion difference does not occur. Further, as the field oxide film 8 goes under, the boron impurity layer 15 extends laterally due to diffusion, and as a result, extends below the outermost peripheral region of the source / drain channel formation region (SOI film 3).

After that, the silicon nitride film 11 and the thermal oxide film 10 on the surface of the SOI film 3 are removed by dry etching, and then a gate oxide film 6 having a thickness of 100 Å is formed, and the gate electrode 7 is formed by a known method. A source region 4 and a drain region 5 are formed. The source region 4 and the drain region 5 were formed by phosphorus ion implantation.

After that, an MOS transistor was completed by forming an interlayer insulating film, forming a contact hole, and forming an aluminum wiring by a usual MOS transistor manufacturing method (FIG. 3C).

FIG. 4 shows the result of comparison of subthreshold characteristics between the element thus obtained and the conventional element. In the element of this example shown by the solid line in the figure, the characteristic bending due to the parasitic transistor seen in the conventional example shown by the broken line was suppressed, and the ideal characteristic was exhibited.

The manufacturing process is not limited to those shown in FIGS. 2 and 3, but can be changed as appropriate. It is also possible to replace the P type and the N type. Therefore, it is possible to form the complementary MOS transistor shown in FIG. Here, 4 and 5 are source / drain regions formed by ion implantation of boron, respectively, and 16 is a phosphorus impurity layer.

Further, various modifications can be made without departing from the scope of the present invention.

[0026]

According to the present invention, the suppression of the parasitic transistor can be suppressed without complicating the element structure and causing the leakage between the source and the drain.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of the present invention.

FIG. 2 is a process sectional view according to an embodiment of the present invention.

FIG. 3 is a process sectional view subsequent to FIG. 2;

FIG. 4 shows a semiconductor device according to the present invention and a conventional device,
The characteristic diagram which compared the relationship of drain current and gate voltage.

FIG. 5 is a sectional view of an element using a conventional technique.

[Explanation of symbols]

1 semiconductor substrate 2 insulating film (SiO ₂ layer) 3 single crystal semiconductor thin film layer (SOI film) 4 source diffusion layer region 5 drain diffusion layer region 6 gate oxide film 7 gate electrode 8 device isolation oxide film 9 device isolation edge region 10 insulation Film (SiO ₂ layer) 11 Silicon nitride film 12 Polycrystalline silicon film 13 Insulating film (SiO ₂ film) 14 Boron ion 15 Boron impurity layer 16 Phosphorus impurity layer

Claims (1)

[Claims] 1. A pair of first-conductivity-type impurity diffusion regions spaced apart by a predetermined distance from a semiconductor active region layer formed on a surface of a semiconductor substrate with an insulating film interposed therebetween, and formed between the pair of diffusion regions. A channel region and a gate electrode formed on the channel region via a gate insulating film, a second conductivity type impurity layer region is formed on the surface of the semiconductor substrate below the region outside the semiconductor active region. A semiconductor device, wherein at least the second-conductivity-type impurity layer region is formed so as to extend so as to include the lowermost outermost region of the semiconductor active region layer.