JPH10270441A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device provided with an insulating film that can reduce the reliability-related characteristic deterioration of the device due to moisture and, at the same time, does not affect the initial characteristic of the device. SOLUTION: A transistor 9 is covered with a silicon nitride film 11 formed by the LPCVD method and having a film thickness of <10 nm. Therefore, the reliability-related characteristic deterioration of the transistor 9 due to moisture can be reduced and the silicon nitride film 11 is prevented from giving an influence to the initial characteristic of the transistor 9.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly, to a method for reducing the deterioration of device reliability due to moisture or hydroxyl groups and affecting the initial characteristics of the device. The present invention relates to a semiconductor device having a non-applied film and a method of manufacturing the same.

[0002]

2. Description of the Related Art Heretofore, the following methods have been proposed as methods for reducing deterioration in device reliability due to moisture or a hydroxyl group in a semiconductor device. (1) Plasma CVD (Chemical Vapor Deposition)
TEOS (Tetra-Ethyl-Ortho-Si)
licate) film (PE (Plasma Enhanced) -TEOS film)
Cover the device with BP on the PE-TEOS film
A method of forming an SG (Boro-Phospho Silicate Glass) film and forming an insulating film on the BPSG film (K. Machida.et
al., IEEE TRANSACTIONS OF ELECTRON DEVICES.Vol41, N
o.5, May1994, pp709-714.).

(2) A method of covering a device with a silicon nitride film formed by an LPCVD (Low Pressure CVD) method (Uraoka et al., IEICE Technical Report, SDM88-42, 1988, pp13-1)
8.)

[0004]

The above method (1) focuses on preventing the diffusion of moisture or hydroxyl groups from the insulating film on the BPSG film to the device.
If the BPSG film itself is a source of moisture or hydroxyl groups, diffusion of moisture or hydroxyl groups cannot be prevented.

In the above method (2), although the effect of preventing moisture or hydroxyl groups from entering is high, the MOSFET (Metal Ox
When a silicon nitride film is formed on the ide semiconductor field effect transistor), the initial short channel effect characteristics and reliability of the MOSFET are affected. If a silicon nitride film is not formed, BT (Bias Temperatur
e) It has the effect of increasing instability.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the deterioration of the reliability of a device due to moisture or a hydroxyl group and to affect the initial characteristics of the device. It is an object of the present invention to provide a semiconductor device provided with a film that does not give a problem and a method for manufacturing the same.

[0007]

According to the first aspect of the present invention, there is provided a silicon nitride film covering a device formed on a semiconductor substrate, and the silicon nitride film has a thickness of 10 nm.
The gist is to be less than nm. The gist of the present invention is to provide an island-shaped silicon nitride film covering only a necessary portion of a device formed on a semiconductor substrate.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the device is an insulated gate FE.
The gist is that it is T. According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the device is a silicon MOSFET. According to a fifth aspect of the present invention, in the semiconductor device according to the second aspect, the device is an insulated gate FET, and essential parts of the device are a gate electrode and a gate insulating film.

According to a sixth aspect of the present invention, in the semiconductor device of the first aspect, the silicon nitride film is formed by an LPCVD method. The invention according to claim 7, wherein a step of forming a gate insulating film in a first conductive and second conductive well formed on a semiconductor substrate; and a step of forming a gate of the first conductive and second conductive well. Forming a gate electrode on the insulating film; and forming a first conductive layer and a second conductive layer including the gate electrode.
Forming a first silicon nitride film over the entire surface of the conductive well, forming a first mask over the second conductive well including the gate electrode, and using the first mask as an etching mask Patterning the first silicon nitride film into an island shape by using as a mask, and ion-implanting a second conductive impurity into the first conductive well using the first mask as an ion implantation mask. Forming source / drain regions of the insulated gate FET on the first conductive well;
Including a step of forming a film having a different etching rate from the silicon nitride film on the entire surface of the conductive well, a step of forming a second silicon nitride film on the film having a different etching rate from the silicon nitride film, and a gate electrode Forming a second mask on the first conductive well, patterning the second silicon nitride film into an island shape using the second mask as an etching mask, Forming a source / drain region of an insulated gate FET on the second conductive well by ion-implanting a first conductive impurity into the second conductive well using the mask as an ion implantation mask. That is the gist.

According to an eighth aspect of the present invention, in the method of manufacturing a semiconductor device according to the seventh aspect, an element isolation insulating film for insulating and isolating the first conductive well and the second conductive well is provided. The gist is that the first or second silicon nitride film is patterned so as to cover the well and the end of the element isolation insulating film surrounding the well.

In the embodiments of the invention described below, the “first mask” or the “second mask” described in the claims or the means for solving the problems is defined by resist patterns 56 and 59. Similarly, the “film having a different etching rate from the silicon nitride film” corresponds to the silicon oxide film 57.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows this embodiment as an NM.
An example applied to a method for manufacturing an OSFET will be described. Step 1 (see FIG. 1A); LOCOS (Local Oxidat
ion on Silicon) method, and a P-type single crystal silicon substrate 1
An element isolation insulating film 2 is formed thereon. As a result, the surface of the substrate 1 exposed from the element isolation insulating film 2 becomes an active region. Next, a gate oxide film 3 (thickness: 11 nm) is formed on the substrate 1 by using a thermal oxidation method. Subsequently, a gate electrode 4 is formed by forming a doped polysilicon film to which an N-type impurity is added on the gate oxide film 3 and patterning the doped polysilicon film. The length of the gate electrode 4 becomes the gate length. Next, using the gate electrode 4 as a mask for ion implantation, phosphorus is ion-implanted (implantation energy: 50 keV) into the surface of the substrate 1 to form the low-concentration impurity regions 5. Subsequently, a silicon oxide film is formed on the entire surface of the device formed in the above process by using the CVD method, and the silicon oxide film is etched back by using the entire-surface etch-back method. Then, a sidewall spacer 6 (width: 150 nm) is formed. Next, arsenic is ion-implanted (implantation energy: 35 keV) into the surface of the substrate 1 using the gate electrode 4 and the sidewall spacer 6 as an ion implantation mask, thereby forming a high-concentration impurity region 7. And
Annealing (processing temperature; 900 ° C.) is performed to activate the impurity regions 5 and 7. As a result, the low concentration impurity region 5
(Lightly Doped Drain) comprising a source / drain region 8 composed of
A silicon gate NMOSFET 9 having a structure is formed.

Step 2 (see FIG. 1B); TE is formed on the entire surface of the device formed in the above-described steps by using the LPCVD method.
An OS film 10 (thickness: 200 nm) is formed. Next, L
A silicon nitride film 11 (thickness: less than 10 nm) is formed on the TEOS film 10 by a PCVD method (material gas; (SiH ₂ Cl ₂ + NH ₃ ) -based gas; formation temperature: 700 to 900 ° C.). At this time, the formation temperature is more preferably 70
0-750 ° C.

Step 3 (see FIG. 1C): A BPSG film 12 (film thickness: 5) is formed on the silicon nitride film 11 by CVD.
00 to 1000 nm). Since the BPSG film has excellent flatness, the device surface can be flattened. Next, a silicon oxide film 13 (film thickness: 100 nm) is formed on the BPSG film 12 by using the CVD method. Subsequently, a contact hole 14 is formed in each of the films 10 to 13. Then, a metal film is formed on the entire surface of the device including the inside of the contact hole 14, and the metal film is patterned to form the source / drain electrodes 15.

FIG. 2 shows an example in which this embodiment is applied to a method for manufacturing a PMOSFET. In this example, the same components as those in the method of manufacturing the NMOSFET shown in FIG. 1 are denoted by the same reference numerals, and the description of the method of manufacturing is omitted. Step 1 (see FIG. 2A); N-type single-crystal silicon substrate 2
An element isolation insulating film 2 is formed on 1. As a result, the surface of the substrate 21 exposed from the element isolation insulating film 2 becomes an active region. Next, the gate oxide film 3 is formed on the substrate 21 by using a thermal oxidation method. Subsequently, a gate electrode 4 is formed on the gate oxide film 3. Next, using the gate electrode 4 as a mask for ion implantation, boron fluoride (B
F ₂ ) is ion-implanted (implantation energy: 50 keV) to form the impurity region 22. Subsequently, sidewall spacers 6 are formed on both side walls of the gate electrode 4. Then, annealing (processing temperature; 900 ° C.) is performed to activate the impurity regions 22. As a result, the impurity region 2
2 comprising a source / drain region 23 composed of
Silicon gate PMOSF with SD (Single Drain) structure
ET24 is formed.

Step 2 (see FIG. 2B): A TEOS film 10 and a silicon nitride film 11 are sequentially formed on the entire surface of the device formed in the above steps. Step 3 (see FIG. 2 (c)); B on the silicon nitride film 11
A PSG film 12 is formed, and a silicon oxide film 13 is formed on the BPSG film 12. Subsequently, a contact hole 14 is formed, and a source / drain electrode 15 is formed.

FIG. 3 shows that the PMOSFE is formed by using the BT stress method (BT stress condition: 200 ° C., 5 V, 2 hours).
The result of having investigated the BT instability of T24 is shown. When the silicon nitride film 11 (SiN) is not formed, the threshold voltage (Vt) of the PMOSFET 24 shifts due to the BT stress. Then, by depositing the silicon nitride film 11, the shift of the threshold voltage due to the BT stress is suppressed,
It can be seen that there is no influence on BT instability.
The NMOSFET 9 has a silicon nitride film 11
Has no effect on BT instability.

By the way, B in the PMOSFET 24
The mechanism of the T instability is considered as shown in equations [1] and [2]. A dangling bond is formed at the interface between the substrate 21 and the gate oxide film 3 as shown in Expression [1]. ≡Sis−H → ≡Sis. + H (1) In the gate oxide film 3 near the interface, a dangling bond is formed as shown in the equation [2].

[0019] ≡Sio-O-Sio≡ + H → ≡Sio-OH + ≡Sio · ≡Sio · → Sio + + e ... [2] here, "Sis" semiconductor (N-type single crystal silicon substrate 21) "Sio" represents silicon present in the silicon oxide film (gate oxide film 3).

As shown in the equation (2), a positive charge (Sio ⁺ ) is generated near the gate edge (both ends of the gate oxide film 3) under the influence of moisture or a hydroxyl group. PMOSFET
By forming the silicon nitride film 11 on the gate electrode 24, it is possible to prevent the generation of positive charges near the gate edge due to the influence of the moisture or the hydroxyl group. FIG. 4 shows the result of examining the initial short channel effect characteristics of the NMOSFET 9. When the silicon nitride film 11 is deposited to a thickness of 10 nm or more, the NMOSFET 9
In the above, the initial threshold voltage (Vt) increases in a long channel region where the gate length (Gate Length) increases. That is, if the thickness of the silicon nitride film 11 is less than 10 nm, the initial short channel effect characteristics are not affected. Note that the PMOSFET 24 has no effect on the initial short channel effect characteristics due to the silicon nitride film 11.

FIG. 5 shows that the interface state density (Dit; Interface) between the substrate 1 and the gate oxide film 3 in the NMOSFET 9 is shown in FIG.
3 shows the results of examining the gate length dependency of ace trap density). It can be seen that the dependence of the interface state density on the gate length depends on the case where the silicon nitride film 11 has a thickness of 20 nm and not on 7 nm. That is, if the thickness of the silicon nitride film 11 is less than 10 nm, the dependence of the interface state density on the gate length is eliminated.

FIG. 6 shows an interface state density (D) in the NMOSFET 9 using the CV (Capacitance Voltage) method.
It shows the result of examining the energy level of (it). When the thickness of the silicon nitride film 11 is 20 nm, E _F −E _i = 0 to
It can be seen that the energy level of 0.2 eV, that is, the interface state density on the side of the conduction band is increased. When the thickness of the silicon nitride film 11 is 7 nm, the interface state density does not increase. Here, “E _F ” represents the energy level of the Fermi level, and “E _i ” represents the reference of the energy level of the semiconductor (that is, the energy level at the center of the forbidden band of single crystal silicon).

FIG. 7 shows the results of device simulation of the initial short channel effect characteristics of the NMOSFET 9 using a two-dimensional device simulator. Here, N
The simulation is performed on the assumption that the increase in the interface state density in the MOSFET 9 is caused by the occurrence of the acceptor type interface state. It can be seen that the measured values and the simulated values shown in FIG.

The following can be understood from FIGS. (1) When the silicon nitride film 11 is deposited to a thickness of 10 nm or more,
The initial threshold voltage of the NMOSFET 9 increases in the long channel region. This is due to the generation of acceptor-type interface states. The cause is that the silicon nitride film 1
The influence of mechanical stress due to No. 1 is considered. That is, since the silicon nitride film 11 has a large stress, the NMO
Mechanical stress is applied to the SFET 9 to lower the bond strength of the Si-O bond near the interface between the substrate 1 and the gate oxide film 3, thereby forming a trap. The trap generates an acceptor-type interface state.

Further, since the silicon nitride film 11 has low permeability not only for moisture and hydroxyl groups but also for hydrogen, it is considered that the amount of hydrogen termination of dangling bonds is reduced and the initial short channel effect characteristics are adversely affected. . (2) When the silicon nitride film 11 is thinned to 7 nm, N
No increase in the threshold voltage of the MOSFET 9 is observed.

It is considered that this is because the thinning of the silicon nitride film 11 reduces the stress of the silicon nitride film 11 and reduces the mechanical stress. It is also considered that the reduction in the thickness of the silicon nitride film 11 increases the permeability of hydrogen and increases the amount of hydrogen termination of dangling bonds. (3) Even if the silicon nitride film 11 is thinned to 7 nm,
In the MOSFET 24, no shift in the threshold voltage due to the BT stress is observed.

As described above, in this embodiment, the LPC
Each FE is formed by the silicon nitride film 11 formed by the VD method.
T9 and 24 are covered, and the thickness of the silicon nitride film 11 is reduced to less than 10 nm. This makes it possible to reduce the deterioration of the reliability of the FETs 9 and 24 due to the moisture or the hydroxyl group, and to prevent the silicon nitride film 11 from affecting the initial characteristics of the FETs 9 and 24. Can be.

The range of the thickness of the silicon nitride film 11 is suitably less than 10 nm, preferably 3 nm or more and less than 10 nm, particularly preferably 3 nm or more and less than 5 nm. When the thickness of the silicon nitride film 11 is less than 3 nm, there is no influence on the NMOSFET 9,
With respect to the PMOSFET 24, there is a possibility that the reliability of the PMOSFET 24 may be affected. In addition, the silicon nitride film 1
1 becomes 10 nm or more, the PMOSFET 24
Although there is no influence on the NMOSFET 9, there is a possibility that the NMOSFET 9 may affect the initial characteristics.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the same components as those in the first embodiment have the same reference numerals, and a description thereof will be omitted. FIG. 8 shows an example in which the present embodiment is applied to an NMOSFET manufacturing method. FIG. 9 shows an example in which the present embodiment is applied to a method for manufacturing a PMOSFET.

8 and 9, FIG. 1 and FIG.
1 in that the island-shaped silicon nitride film 11 is formed only on each of the FETs 9 and 24 (that is, on the active region). That is, after the silicon nitride film 11 is formed on the entire surface of the device, the silicon nitride film 11 is
Is patterned into a desired shape. Even if you do this,
Since there is no change in the fact that the silicon nitride film 11 can cover the FETs 9 and 24, the same operation and effect as in the first embodiment can be obtained.

In the present embodiment, there is no particular condition for the thickness of the silicon nitride film 11, and the thickness is 10 nm.
You can do more than that. The present inventor has confirmed that the above effects can be obtained even when the thickness of the silicon nitride film 11 is set to 30 nm. This is because the area of the silicon nitride film 11 is reduced by forming the island-shaped silicon nitride film 11 only on each of the FETs 9 and 24, and the stress thereof can be reduced. Further, hydrogen having a higher diffusion coefficient than water or a hydroxyl group flows from the end of the silicon nitride film 11 and is supplied to the lower side of the gate electrode 4, so that the amount of hydrogen termination of dangling bonds increases. is there.

Further, an island-shaped silicon nitride film 11 was formed so that a part of the silicon nitride film 11 covered not only the FETs 9 and 24 (on the active region) but also the end of the element isolation insulating film 2. In this case, the same operation and effect as described above can be obtained. (Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. In this embodiment,
The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

FIG. 10 shows an example in which this embodiment is applied to a method for manufacturing an NMOSFET. FIG. 11 shows an example in which the present embodiment is applied to a method for manufacturing a PMOSFET.
10 and FIG. 11 are different from the first embodiment shown in FIG. 1 and FIG. 2 in that the TEOS film 10 is omitted and silicon is formed on the source / drain regions 8, 23, the gate electrode 4, and the sidewall spacer 6. The only difference is that the nitride film 11 is directly formed. Even in this case, the fact that the respective FETs 9 and 24 can be covered by the silicon nitride film 11 is not changed, so that the same operation and effect as in the first embodiment can be obtained.

(Fourth Embodiment) Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the same components as those in the second embodiment and the third embodiment are denoted by the same reference numerals, and description thereof will be omitted. FIG. 12 shows an example in which the present embodiment is applied to an NMOSFET manufacturing method. FIG. 13 shows this embodiment as P
An example applied to a method for manufacturing a MOSFET will be described.

This embodiment is a combination of the second and third embodiments. That is, in the present embodiment, as in the second embodiment, the island-shaped silicon nitride film 11 is formed only on each of the FETs 9 and 24 (on the active region). In the present embodiment, as in the third embodiment, T
The EOS film 10 is omitted, and the source / drain regions 8, 2
3, a silicon nitride film 11 is directly formed on the gate electrode 4, and the sidewall spacer 6. With this configuration, the same operation and effect as those of the second embodiment and the third embodiment can be obtained. Note that, also in the present embodiment, there is no particular condition regarding the thickness of the silicon nitride film 11, and the thickness may be 10 nm or more.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings. In the present embodiment, the same components as those in the fourth embodiment have the same reference numerals, and the description thereof will be omitted. Step 1 (see FIG. 14A); single-crystal silicon substrate 51
Is doped with a P-type impurity to form a P well 52. Further, an N well 53 is formed by doping the substrate 51 with an N-type impurity. Next, using the LOCOS method, each well 52,
The element isolation insulating film 2 is formed on 53. As a result, the surfaces of the wells 52 and 53 exposed from the element isolation insulating film 2 become active regions. Subsequently, using a thermal oxidation method, each well 5
A gate oxide film 3 is formed on 2 and 53. Then, a gate electrode 4 is formed by forming a doped polysilicon film to which an N-type impurity is added on the gate oxide film 3 and patterning the doped polysilicon film. next,
After covering the N well 53 with a resist pattern (not shown), phosphorus is ion-implanted into the surface of the P well 52 using the gate electrode 4 on the P well 52 as an ion implantation mask. Then, a low concentration N-type impurity region 5 is formed. Subsequently, after covering the P well 52 with a resist pattern (not shown), the gate electrode 4 on the N well 53 is used as an ion implantation mask to form the N well 5.
A low concentration P-type impurity region 54 is formed on the N well 53 by ion-implanting boron fluoride into the surface of the substrate 3.
Then, a silicon oxide film is formed on the entire surface of the device formed in the above step by using the CVD method, and the silicon oxide film is etched back by using the whole-surface etch-back method. A side wall spacer 6 is formed.

Step 2 (see FIG. 14B); LPCVD
A silicon nitride film 55 (film thickness: 20) is formed on the entire surface of the device formed by the above-described process by using a method (material gas; (SiH ₂ Cl ₂ + NH ₃ ) -based gas; formation temperature; 700 to 900 ° C.).
nm). Step 3 (see FIG. 15A); N
The end of the element isolation insulating film 2 surrounding the well 53 and the N well 5
A resist pattern 56 is formed so as to cover Step 3. Next, a dry etching method (etching gas; CF ₄ +) using the resist pattern 56 as an etching mask
By H ₂ ), the P well 52 and the silicon nitride film 55 on the element isolation insulating film 2 surrounding the P well 52 are patterned and removed. Subsequently, by using the resist pattern 56 as an ion implantation mask, arsenic is ion-implanted into the surface of the P well 52 to form a high concentration N-type impurity region 7 on the P well 52. As a result, a silicon gate NMOSFET 9 having an LDD structure and having a source / drain region 8 composed of a low-concentration impurity region 5 and a high-concentration impurity region 7 is formed.

Step 4 (see FIG. 15B); LPCVD
Using a method, a silicon oxide film 57 (thickness: 10 nm) is formed on the entire surface of the device formed in the above steps. Next, a silicon nitride film 58 (film thickness: 20 n) is formed on the silicon oxide film 57 under the same forming conditions as the silicon nitride film 55.
m). Subsequently, a resist pattern 59 is formed so as to cover the edge of the element isolation insulating film 2 surrounding the P well 52 and the P well 52.

Step 5 (see FIG. 16A): N is obtained by a dry etching method (etching gas; CF ₄ + H ₂ ) using the resist pattern 59 as an etching mask.
Element isolation insulating film 2 surrounding well 53 and N well 53
Is patterned and removed. Subsequently, using the resist pattern 59 as an ion implantation mask, boron fluoride is ion-implanted into the surface of the N well 53 to form a high-concentration P-type impurity region 60 on the N well 53. Then, annealing is performed to activate each of the impurity regions 54 and 60. As a result, a silicon gate PMOSFET 62 having an LDD structure and having a source / drain region 61 composed of a low concentration impurity region 54 and a high concentration impurity region 60 is formed.

Step 6 (see FIG. 16B): BPS is applied to the entire surface of the device formed in the above-described steps by using the CVD method.
A G film 12 is formed. Next, using the CVD method, BPSG
A silicon oxide film 13 is formed on the film 12. Subsequently, the contact holes 1 are formed in the respective films 55, 57, 58, 12, 13.
4 is formed. Then, a metal film is formed on the entire surface of the device including the inside of the contact hole 14, and the metal film is patterned to form the source / drain electrodes 15. Here, by connecting the gate and the drain of each of the FETs 9 and 62 by the source / drain electrode 15, connecting the source of the PMOSFET 9 to the high-potential-side power supply, and connecting the source of the NMOSFET 9 to the low-potential-side power supply, CMOS composed of FETs 9 and 62
The inverter is completed.

As described above, according to the present embodiment, the following operations and effects can be obtained. [1] On the PMOSFET 62 (on the active region) and the PMO
An island-shaped silicon nitride film 55 is formed so as to cover the end of the element isolation insulating film 2 surrounding the N well 53 where the SFET 62 is formed. Therefore, since the PMOSFET 62 is covered by the island-shaped silicon nitride film 55,
Functions and effects similar to those of the fourth embodiment can be obtained.

In this embodiment, there is no particular condition for the thickness of the silicon nitride film 55, and the thickness is 10 nm.
You can do more than that. The present inventor has confirmed that the above effects can be obtained even when the thickness of the silicon nitride film 55 is set to 30 nm. This is because the formation of the island-shaped silicon nitride film 55 reduces the area of the silicon nitride film 55 and can reduce its stress, so that the mechanical stress applied to the PMOSFET 62 is reduced. Further, hydrogen having a higher diffusion coefficient than water or a hydroxyl group wraps around from the end of the silicon nitride film 55 and is supplied to the lower side of the gate electrode 4, so that the amount of hydrogen termination of dangling bonds increases. is there.

[2] On NMOSFET 9 (on active region)
An island-shaped silicon nitride film 58 is formed to cover the end of the element isolation insulating film 2 surrounding the P well 52 in which the NMOSFET 9 is formed. Therefore, since the NMOSFET 9 is covered by the island-shaped silicon nitride film 58, the same operation and effect as in the fourth embodiment can be obtained.

In this embodiment, there is no particular condition for the thickness of the silicon nitride film 58, and the thickness is 10 nm.
You can do more than that. The present inventor has confirmed that the above effects can be obtained even when the thickness of the silicon nitride film 58 is set to 30 nm. This is because the formation of the island-shaped silicon nitride film 58 reduces the area of the silicon nitride film 58 and reduces its stress, thereby reducing the mechanical stress applied to the NMOSFET 9. Further, hydrogen having a higher diffusion coefficient than water or a hydroxyl group wraps around from the end of the silicon nitride film 58 and is supplied to the lower side of the gate electrode 4, so that the amount of hydrogen termination of dangling bonds increases. is there.

In the present embodiment, the thickness of the silicon oxide film 57 is not particularly limited.
m or more. [3] In the above step 3, after the silicon nitride film 55 is patterned into an island shape using the resist pattern 56 as an etching mask, a high-concentration N-type impurity region of the NMOSFET 9 is formed using the resist pattern 56 as an ion implantation mask. 7 are formed. That is, NMOSF
A resist pattern 56 serving as an ion implantation mask for forming a high concentration N-type impurity region 7 of ET 9 is used as an etching mask for patterning the silicon nitride film 55 into an island shape. Therefore, when patterning the silicon nitride film 55 in an island shape, it is not necessary to add a new photolithography process, and it is possible to prevent the manufacturing process from becoming complicated.

[4] In the steps 4 and 5, after the silicon nitride film 58 is patterned into an island shape using the resist pattern 59 as an etching mask, the resist pattern 59 is used as a mask for ion implantation.
A high-concentration P-type impurity region 60 of the MOSFET 62 is formed. That is, the resist pattern 59 as an ion implantation mask for forming the high-concentration P-type impurity region 60 of the PMOSFET 62 is used as an etching mask for patterning the silicon nitride film 58 into an island shape. Therefore, when patterning the silicon nitride film 58 into an island shape, it is not necessary to add a new photolithography process, and it is possible to prevent the manufacturing process from becoming complicated.

[5] The etching rates of the silicon nitride film 58 and the silicon oxide film 57 are significantly different. Therefore, when patterning the silicon nitride film 58 in step 5, the silicon oxide film 57 functions as an etching stopper. Therefore, the silicon nitride film 55 on the N well 53 and the element isolation insulating film 2 surrounding the N well 53
Can be prevented from being removed, and the operation and effect of the above [1] can be reliably obtained.

(Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described with reference to the drawings. Note that, in the present embodiment, the same components as those in the fifth embodiment have the same reference numerals, and description thereof will be omitted. Step 1 (FIG. 14)
(A)) and step 2 (see FIG. 14 (b));
This is the same as Step 1 and Step 2 of the embodiment.

Step 3 (see FIG. 17A); P well 5
A resist pattern 59 is formed so as to cover an end portion of the element isolation insulating film 2 surrounding P2 and the P well 52. Next, using the resist pattern 59 as an etching mask,
Element isolation insulating film 2 surrounding well 53 and N well 53
Is patterned and removed. Subsequently, using the resist pattern 59 as an ion implantation mask, boron fluoride is ion-implanted into the surface of the N well 53 to form a high-concentration P-type impurity region 60 on the N well 53. Then, annealing is performed to activate the impurity regions 54 and 60, and the PMOSFET 62 is activated.
To form

Step 4 (see FIG. 17B): A silicon oxide film 57 and a silicon nitride film 58 are sequentially formed on the entire surface of the device formed in the above steps. Then, N well 5
A resist pattern 56 is formed so as to cover an end portion of the element isolation insulating film 2 surrounding the N 3 and the N well 53. Step 5 (see FIG. 18A); using the resist pattern 56 as an etching mask,
The silicon nitride film 58 on the element isolation insulating film 2 surrounding the well 52 is removed by patterning. Subsequently, by using the resist pattern 56 as an ion implantation mask, arsenic is ion-implanted into the surface of the P well 52 to form a high concentration N-type impurity region 7 on the P well 52. Then, annealing is performed to activate the impurity regions 5 and 7,
An NMOSFET 9 is formed.

Step 6 (see FIG. 18B): The same as step 6 of the fifth embodiment. As described above, according to the present embodiment, the following operations and effects can be obtained. (1) In the fifth embodiment, the NMOSFET 62 is formed after the PMOSFET 9 is formed. On the other hand, in the present embodiment, the PMOSFET 9 is formed after the NMOSFET 62 is formed.

(2) In this embodiment, the PMOSFET 6
2 and an N well 53 on which a PMOSFET 62 is formed.
Island-shaped silicon nitride film 58 is formed so as to cover the end of element isolation insulating film 2 surrounding the silicon nitride film 58. Also, NMOS
An island-shaped silicon nitride film 55 is formed so as to cover the FET 9 and the end of the element isolation insulating film 2 surrounding the P well 52 in which the NMOSFET 9 is formed. That is, the PMOSFET 62 is covered by the island-shaped silicon nitride film 58, and the NMO is covered by the island-shaped silicon nitride film 55.
SFET 9 is covered. Therefore, according to the present embodiment, the same operations and effects as those of the fifth embodiment can be obtained.

The above embodiments may be modified as described below, and the same operation and effect can be obtained in such a case. (1) The silicon nitride films 11, 55, 58 formed on the entire back surface of each of the substrates 1, 21, 51 are left. LPCV
When the silicon nitride films 11, 55, 58 are formed using the method D, the silicon nitride films 11, 55, 58 are also formed on the entire back surface of each of the substrates 1, 21, 51. By leaving the silicon nitride films 11, 55, 58 formed on the entire back surface of each of the substrates 1, 21, 51, the substrates 1, 21, 51
Of the present invention can be prevented from invading moisture or hydroxyl groups from the back surface of the substrate, and the effect of each embodiment can be further enhanced.

(2) T formed by LPCVD
The EOS film 10 has a low moisture or hydroxyl content,
Other insulating films with low moisture or hydroxyl permeability (eg,
LPCVD method, plasma CVD method, ECR plasma CV
D, etc.). (3) The BPSG film 12 is replaced with another insulating film having excellent flatness (for example, a SOG (Spin On Glass) film, a TEOS film formed by an ozone CVD method, or the like).

(4) The NMOSFET 9 has an SD structure instead of an LDD structure. Also, the PMOSFET 62 is connected to the LD
An SD structure is used instead of a D structure. (5) The silicon oxide film 57 is replaced with an appropriate film having a different etching rate from the silicon nitride film. (6) Not only silicon gate MOSFETs 9, 24 and 62 but also MIS (Metal Insulator Semiconductor)
) Applies to FETs in general. That is, the gate oxide film 3
Is replaced with an appropriate insulating film other than the silicon oxide film (such as a silicon nitride film, a film having a stacked structure of a silicon nitride film and a silicon oxide film).

(7) Silicon gate MOSFETs 9, 2
Insulated gate FET (IGFE)
T: Insulated Gate FET) That is,
The gate electrode 4 is formed of an appropriate conductive material other than doped polysilicon (various metals such as aluminum and high melting point metal, metal silicide, and the like). Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below along with their effects.

(A) The semiconductor device according to any one of claims 1 to 6, wherein a silicon nitride film is formed on the entire back surface of the semiconductor substrate on which devices are formed. With this configuration, it is possible to prevent moisture or hydroxyl groups from entering from the back surface of the semiconductor substrate.

(B) The semiconductor device according to any one of claims 1 to 6, further comprising an insulating film having low moisture or hydroxyl group permeability between said silicon nitride film and said device. In this case, since the moisture or the hydroxyl group is blocked by the insulating film, the diffusion of the moisture or the hydroxyl group into the device can be further reduced.

(C) The semiconductor device according to any one of claims 1 to 6, wherein the silicon nitride film is formed directly on the device. Even in this case, the same operation and effect as the invention described in any one of the first to fifth aspects can be obtained. By the way, in this specification, the members according to the configuration of the present invention are defined as follows.

(A) The semiconductor substrate includes not only a single crystal silicon substrate but also a well, a polycrystalline silicon thin film, an amorphous silicon thin film, an SOI (Silicon On Insulator) substrate and the like. (B) Insulated Gate FET (IGFET)
FET means not only MOSFET but also MIS (Metal
Insulator Silicon) FET, silicon gate MOSF
ET, silicide gate MOSFET, silicon MOS
It also includes an FET and the like.

[0061]

According to the first to sixth aspects of the present invention, a silicon nitride film which does not affect the initial characteristics of the device while reducing the deterioration of the characteristics of the device due to moisture or hydroxyl groups can be reduced. A semiconductor device having the same can be provided.

According to the first aspect of the invention, by reducing the thickness of the silicon nitride film, the stress can be reduced, and the mechanical stress applied to the device can be reduced. Further, by reducing the thickness of the silicon nitride film, the permeability of hydrogen is increased, and the amount of hydrogen termination of dangling bonds can be increased. According to the second aspect of the present invention, since the silicon nitride film is formed in an island shape, the area of the silicon nitride film is reduced, so that the stress can be reduced, and the mechanical stress applied to the device can be reduced. Can be reduced. In addition, hydrogen having a higher diffusion coefficient than water or a hydroxyl group is supplied to the device from the end of the silicon nitride film, so that the amount of hydrogen termination of dangling bonds can be increased.

According to any one of the third to fifth aspects of the present invention, the BT stability and the initial short channel effect characteristics of the insulated gate FET are not affected, and the reliability of the device due to moisture or a hydroxyl group is not affected. It is possible to reduce the characteristic deterioration of the performance. According to the invention described in claim 6,
A silicon nitride film with low moisture or hydroxyl group permeability can be obtained.

According to the invention as set forth in claim 7 or claim 8, the silicon nitride film which does not affect the initial characteristics of the device while reducing the deterioration of the characteristics of the device due to moisture or hydroxyl group is reduced. A method for manufacturing a semiconductor device having the same can be provided. According to the seventh aspect, the semiconductor device according to the second aspect can be manufactured. Further, an ion implantation mask for forming source / drain regions is used as an etching mask for patterning the silicon nitride film into an island shape. Therefore, when patterning the silicon nitride film into an island shape, it is not necessary to add a new photolithography process, and it is possible to prevent the manufacturing process from becoming complicated.

According to the eighth aspect of the present invention, the silicon nitride film can be patterned in an island shape after each well is insulated and separated.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view for explaining a manufacturing process according to a first embodiment.

FIG. 2 is a schematic cross-sectional view for explaining a manufacturing process of the first embodiment.

FIG. 3 is a characteristic diagram for explaining the operation of each embodiment.

FIG. 4 is a characteristic diagram for explaining the operation of each embodiment.

FIG. 5 is a characteristic diagram for explaining the operation of each embodiment.

FIG. 6 is a characteristic diagram for explaining the operation of each embodiment.

FIG. 7 is a characteristic diagram for explaining the operation of each embodiment.

FIG. 8 is a schematic cross-sectional view for explaining a manufacturing process of the second embodiment.

FIG. 9 is a schematic cross-sectional view for explaining a manufacturing process of the second embodiment.

FIG. 10 is a schematic cross-sectional view for explaining a manufacturing process according to a third embodiment.

FIG. 11 is a schematic cross-sectional view for explaining a manufacturing process according to a third embodiment.

FIG. 12 is a schematic cross-sectional view for explaining a manufacturing process according to a fourth embodiment.

FIG. 13 is a schematic cross-sectional view for explaining a manufacturing step of the fourth embodiment.

FIG. 14 is a schematic cross-sectional view for explaining the manufacturing process of the fifth embodiment.

FIG. 15 is a schematic cross-sectional view for explaining the manufacturing process of the fifth embodiment.

FIG. 16 is a schematic cross-sectional view for explaining the manufacturing process of the fifth embodiment.

FIG. 17 is a schematic cross-sectional view for explaining the manufacturing process of the sixth embodiment.

FIG. 18 is a schematic cross-sectional view for explaining the manufacturing process of the sixth embodiment.

[Explanation of symbols]

1, 21, 51: single-crystal silicon substrate 2: element isolation insulating film 3: gate oxide film 4: gate electrode 8, 23, 61 source / drain regions 9, 24, 62 MOSFET 11, 55, 58 silicon nitride Film 52: P well 53: N well 56, 59: Resist pattern as first or second mask 57: Silicon oxide film as a film having an etching rate different from that of silicon nitride film

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Atsuhiro Nishida 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Hiroyuki Aoe 2-5-2 Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd. (72) Inventor Kinshi Matsushita 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (8)

[Claims] 1. A semiconductor device comprising a silicon nitride film covering a device formed on a semiconductor substrate, wherein the thickness of the silicon nitride film is less than 10 nm. 2. A semiconductor device comprising an island-shaped silicon nitride film covering only a necessary portion of a device formed on a semiconductor substrate. 3. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the device is an insulated gate FET. 4. The semiconductor device according to claim 1, wherein
A semiconductor device, wherein the device is a silicon MOSFET. 5. The semiconductor device according to claim 2, wherein
A semiconductor device, wherein the device is an insulated gate FET, and a necessary part of the device is at least a gate electrode and a gate insulating film. 6. The semiconductor device according to claim 1, wherein said silicon nitride film is formed by an LPCVD method. 7. A step of forming a gate insulating film in a first conductive and second conductive well formed on a semiconductor substrate; and forming a gate insulating film on the first conductive and second conductive well. A step of forming a gate electrode, a step of forming a first silicon nitride film on the entire surface of the first conductive and second conductive wells including the gate electrode, and a step of forming a second silicon well film including the gate electrode. Forming a first mask thereon, patterning the first silicon nitride film into an island shape using the first mask as an etching mask, using the first mask as an ion implantation mask, Forming a source / drain region of the insulated gate FET on the first conductive well by ion-implanting a second conductive impurity into the first conductive well; A step of forming a film having a different etching rate from the silicon nitride film on the entire surface of the conductive and second conductive wells; a step of forming a second silicon nitride film on the film having a different etching rate from the silicon nitride film; Forming a second mask on the first conductive well including the gate electrode; patterning the second silicon nitride film into an island shape using the second mask as an etching mask; Using the second mask as a mask for ion implantation, the source / drain regions of the insulated gate FET are formed on the second conductive well by ion-implanting the first conductive impurity into the second conductive well. And a method for manufacturing a semiconductor device. 8. The method for manufacturing a semiconductor device according to claim 7, further comprising a step of forming an element isolation insulating film for insulating and separating the first conductive well and the second conductive well. 1
Alternatively, a method for manufacturing a semiconductor device in which the second silicon nitride film is patterned to cover a well and an end of an element isolation insulating film surrounding the well.