JPH06163890A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To secure a sufficiently high isolation breakdown strength between semiconductor elements and suppress the occurrence of leakage currents at the end section of a field insulating film in a finely patterned MOS semiconductor device. CONSTITUTION:A stable isolation breakdown strength is secured between semiconductor elements by forming a channel stopper area 26 in a self-alignment manner in such a way that, after forming side walls 19 for constructing an LDD structure and a source and drain region 20 and 21, the edge sections of element separating regions 14 are made to regress by etching back the entire region of one main surface of a semiconductor substrate 10 and each region is doped with an impurity of a conductivity type opposite to that of the impurity contained in the source and drain regions 20 and 21. Then the impurity in the element separating areas is activated by heat-treating the substrate 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a MOS type semiconductor device which is suitable for miniaturization and which can sufficiently secure isolation withstand voltage between semiconductor elements and suppress leak current. .

[0002]

2. Description of the Related Art Conventionally, in order to improve the element isolation withstand voltage of a MOS type semiconductor device and suppress the leakage current,
As shown in FIG. 5, a channel stopper region 26 is formed up to the element isolation region 14 on the silicon semiconductor substrate 10,
Impurities for channel control are introduced to both ends in the width direction of the gate electrode 16 on the gate oxide film 15 to eliminate the weak inversion region at the gate end, and the N ⁺ source / drain region 21 of the N-channel transistor region 18 is replaced with an element isolation region. A structure separated from the end of 14 (for example,
Alternatively, as shown in FIG. 6, the impurity is introduced into the end portion of the element isolation region 14 at the time of introducing the impurity for the channel control, and the element isolation region 14 is formed.
For example, there is one in which the impurity concentration is uniform at the end (for example, JP-A-62-188273).

[0003]

However, in this type of semiconductor device, since the source / drain impurities are not introduced in a self-aligned manner, the junction breakdown voltage is not stable, or the source / drain impurities are introduced at the gate. There was a drawback that the concentration of impurities other than at the ends changed, and eventually the isolation breakdown voltage between elements could not be stabilized.

Particularly, regarding the miniaturization expected in the future,
Impurities introduced as channel stoppers leak out to the transistor side in the subsequent heat treatment, making it impossible to perform high-concentration ion implantation, and it has become difficult to secure a breakdown voltage between elements.

An object of the present invention is to provide a method of manufacturing a semiconductor device which ensures a sufficient isolation breakdown voltage between semiconductor elements and suppresses a leak current at the end of the element isolation region.

[0006]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises an etch-back step, a doping step, and a heat treatment step. An element region provided, an element isolation region separating each of the element regions, a gate region dividing the element isolation region into a source region and a drain region, and an LDD provided for the purpose of relaxing an electric field of the drain region. (Li
ghtly Doped Drain) region and the LD
MO having side wall for forming D structure
In the method of manufacturing an S-type semiconductor device, the etch back step includes forming sidewalls and forming source / drain regions, and then etching back the entire one main surface of the semiconductor substrate to form an edge portion of the field insulating film. To retreat
The doping step is to dope an impurity having a conductivity type opposite to that of the impurities forming the source / drain regions, and the heat treatment step is to heat the semiconductor substrate to activate the impurities in the element region.

[0007]

After the sidewalls for forming the LDD structure are formed and the source / drain regions are formed, the entire main surface of the semiconductor substrate is etched back to have a conductivity type opposite to that of the impurities forming the source / drain regions. The impurities of
The semiconductor substrate is heat-treated to activate the impurities in the element region, so that the channel stopper region is formed in a self-aligned manner to secure a stable breakdown voltage between elements.

[0008]

Embodiments of the present invention will now be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing a semiconductor device according to Embodiment 1 of the present invention, and FIGS. 2 and 3 are process sectional views showing a manufacturing method according to Embodiment 1 of the present invention in the order of steps. It is a figure.

(1) As shown in FIG. 2A, the entire surface of the P ^- silicon substrate 10 is oxidized by about 5000 angstroms by using a thermal oxidation method, and the thermal oxide film 11 is formed by using an ordinary photolithography technique. After patterning, the N well 12 is formed using the ion implantation technique.

[0011] (2) Next, as shown in FIG. 2 (b), after removing the thermal oxide film 11 on the surface of the silicon substrate 10, further by thermal oxidation, P ^- the entire surface of the silicon substrate 105
The silicon nitride film 13 having an oxidation resistance of 1 is formed by oxidation by about 100 Å and further by chemical vapor deposition.
Deposit 500 Å.

(3) Subsequently, as shown in FIG. 2B, the silicon nitride film 1 is formed by using the photolithography technique.
3 is patterned, a portion to be a field insulating region is opened, and ion implantation for a channel stopper is performed. Then, the entire surface of the silicon substrate 10 is selectively oxidized in an H ₂ —O ₂ atmosphere to form an element isolation region 14. To do.

(4) Next, as shown in FIG. 2C, after removing the silicon nitride film 13 and the thermal oxide film 11 used as the oxidation resistant mask and forming a gate oxide film 15, a channel control film is formed. Ion implantation is performed to form the gate electrode 16.

(5) Through the above steps, as shown in FIG. 2C, P-channel and N-channel MOS transistor regions 17 and 18 are formed, and further, the P-channel side is B (poron) and the N-channel side. Ion-implants impurities of P (phosphorus), and LDD (Lightly Dop)
ed Drain) regions 24 and 25 are formed.

(6) Next, as shown in FIG. 3D, an oxide film of 2000 angstrom is formed on the entire surface of the silicon substrate 10 by chemical vapor deposition, and then the entire main surface is etched back. Sidewalls 19 are formed, and BF ₂ (boron boron) is introduced on the P-channel side and As (arsenic) is introduced on the N-channel side by ion implantation as in the LDD region to form source / drain regions 20 and 21. .

(7) Then, as shown in FIG. 3D, the entire main surface of the silicon substrate 10 is further etched back to retreat the edge of the element isolation region 14. The amount of retreat varies depending on the etching back time and conditions, but is generally 0.
It is preferably about 3 μm.

(8) Next, as shown in FIG. 3E, an impurity of a conductivity type opposite to the impurity introduced into the source / drain regions 20 and 21 of both the P and N transistors is ion-deposited on the entire surface of the transistor region. Drive in. This step also serves the purpose of suppressing the short channel effect of the fine transistor.
(Phosphorus) is implanted at 50 KeV, and the N-channel transistor is implanted with B (boron) at 100 KeV. Both doses are 1E13 cm ^-2 . From this process, the sauce
Outside the drain region, regions 22 and 23 of the conductivity type opposite to those of the source / drain are formed.
A channel stopper region 26 is formed in the self-alignment manner at the end of the.

(9) Next, heat treatment is performed at 900 ° C. for about 10 minutes in an N ₂ atmosphere to activate the introduced impurities.

As shown in FIG. 1, a silicon substrate 10 including a transistor region is used in the subsequent steps by using a usual technique.
An insulating film is deposited on the entire surface of the semiconductor device, and the semiconductor device is completed through a wiring process.

(Embodiment 2) FIG. 4 is a sectional view showing a semiconductor device according to Embodiment 2 of the present invention. In this embodiment, the short channel effect is prevented and the ion implantation for improving the isolation breakdown voltage between elements is performed with an inclination of 30 ° to further improve the characteristics.

According to this embodiment, it is possible to secure the breakdown voltage between elements without performing ion implantation of the channel stopper which is performed when forming the element isolation region.

[0022]

As described above, according to the present invention,
After forming the drain region, the entire main surface of the semiconductor substrate is etched back to recede the end of the element isolation region, and an impurity having a conductivity type opposite to that of the impurities forming the source / drain regions is doped to form a semiconductor substrate. Since the impurities in the element region are activated by heat treatment, it is possible to form the impurity region for element isolation in a self-aligned manner, and secure stable element isolation withstand voltage even in a miniaturized semiconductor device. be able to.

Further, in the present invention, since the source / drain junction is not formed at the end of the element isolation region, junction leakage due to stress such as selective oxidation, which has been a problem in the prior art, can be suppressed.

Although the present invention increases the junction capacitance in the source / drain regions as compared with the prior art, the increase in junction capacitance can be minimized by optimizing the ion implantation. In addition, there is a surplus effect even if the junction capacitance is slightly increased.

[Brief description of drawings]

FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing method of the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing the manufacturing method of the first embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a semiconductor device according to a second embodiment of the invention.

FIG. 5 is a cross-sectional view showing a semiconductor device according to Conventional Example 1.

FIG. 6 is a cross-sectional view showing a semiconductor device according to Conventional Example 2.

[Explanation of symbols]

10 Silicon Semiconductor Substrate 11 Silicon Thermal Oxide Film 12 N Well 13 Silicon Nitride Film 14 Element Isolation Region 15 Gate Oxide Film 16 Gate Electrode 17 P-Channel Transistor Region 18 N-Channel Transistor Region 19 LDD Sidewall 20 P ⁺ Source / Drain Region 21 N ⁺ source / drain region 22 P channel side short channel effect suppression and channel stopper region 23 N channel side short channel effect suppression and channel stopper region 24 P channel side LDD region 25 N channel side LDD region 26 Channel stopper region

Claims (1)

[Claims] 1. An element region provided on a semiconductor substrate of one conductivity type, comprising an etchback step, a doping step, and a heat treatment step, an element isolation region for separating each of the element regions, and the element. A gate region that divides the isolation region into a source region and a drain region, and an LDD (Lightly Doped Dr) provided for the purpose of relaxing the electric field of the drain region.
a)) and a sidewall for forming the LDD structure, the method comprising: forming a sidewall, forming a source / drain region, and then forming a semiconductor. The entire principal surface of the substrate is etched back to retreat the edge of the field insulating film, and the doping process is to dope the impurity of the conductivity type opposite to that of the impurities forming the source / drain regions. The method of manufacturing a semiconductor device, wherein the heat treatment step heats the semiconductor substrate to activate impurities in the element region.