JPH10303418A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent changes in element characteristics, by depositing a tungsten silicide layer on a non-single crystal silicon layer, then carrying out heat treatment at a temperature higher than the processing temperature of the subsequent manufacturing steps, thus patterning the non-single crystal silicon layer and the tungsten silicide layer, and forming a gate electrode. SOLUTION: A p-type silicon substrate 11 is selectively oxidized to form a field oxide film 12 for element isolation, and thermal oxidation is carried out to form a gate oxide film 13. Then, a polycrystalline silicon layer 14 is grown and a WSi layer 15 is grown. The WSi layer 15 is crystallized and transformed to a crystallized WSi layer 16. The polycrystalline silicon layer 14 and the crystallized WSi layer 16 are patterned, thus forming gate electrodes constituted by a polycrystalline silicon gate electrode 18 and a WSi gate electrode 19. Heat treatment is carried out to form a through film 20 to be a damage prevention film in ion implantation. Thus, the patterned WSi gate electrode 19 can be prevented from contracting.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing an insulated gate semiconductor device using a WSi / polycrystalline silicon two-layer structure gate electrode.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been required to operate at higher speeds, and the gate length of the gate electrode has been further reduced in order to meet the demand. The finished shape becomes important.

Here, the manufacturing process of a conventional MOSFET will be described with reference to FIGS. Referring to FIG. 4A, first, a p-type silicon substrate 31 is selectively oxidized using a nitride film pattern (not shown) as a mask to form a thick field oxide film 32 for element isolation, and then the nitride film pattern is removed. The gate oxide film 33 is formed by thermal oxidation.

Next, a polycrystalline silicon layer 34 is formed by low pressure chemical vapor deposition (LPCVD) using SiH _4.
Is grown and then LPC using SiH ₄ / WF ₆ system
The WSi layer 35 is formed by the VD method.

Referring to FIG. 4B, after P (phosphorus) ions are implanted to lower the resistance of the polycrystalline silicon layer 34, WS
In order to prevent oxidation of the i-layer 35 and out diffusion of the implanted P, high-temperature CVD at a temperature of 800 ° C.
An oxide film 36 is formed by a method.

Referring to FIG. 4C, a gate electrode composed of a polysilicon gate electrode 37 and a WSi gate electrode 38 is formed by patterning the polysilicon layer 34 and the WSi layer 35. By performing a heat treatment in a dry O ₂ atmosphere, a through film 39 having a thickness of about 50 ° serving as a damage prevention film at the time of ion implantation is formed. In this step, although not shown, a thin oxide film is also formed on the side wall of the gate electrode.

Next, as shown in FIG. 5D, P ions 40 are implanted using the gate electrode and the field oxide film 32 as a mask to form an LDD.
A shallow low-concentration n-type region 41 for forming a (Lightly Doped Drain) region is formed.

Next, an SiO ₂ film is deposited on the entire surface, and then RIE is performed.
By performing anisotropic etching by the (reactive ion etching) method, a sidewall 4 is formed on the side of the gate electrode.
Then, P ions 43 are implanted using the sidewalls 42, the gate electrode, and the field oxide film 32 as a mask, thereby forming a deep and high-concentration n ^+.
Form source / drain regions 44 are formed.

Hereinafter, although omitted, after the heat treatment is performed to activate the implanted P ions, an interlayer insulating film or the like is provided, and then the source / drain electrode is contacted through a contact hole provided in the interlayer insulating film. The MOSFET is completed by providing the gate and the gate extraction electrode and the like.

[0010]

However, the conventional MOS
In the FET manufacturing process, the completed MOSFE
Since there is a problem that the characteristics of T vary and the characteristics as designed cannot be obtained, this problem will be described with reference to FIG.

Referring to FIGS. 6A and 6B, in a thermal oxidation step for forming a through film 39 for preventing damage at the time of ion implantation, the WSi gate electrode 38 contracts (shrinks) and heat treatment is performed. The sidewall of the WSi gate electrode 38, which was vertically vertical before, becomes tapered, and when the sidewall 42 is formed for such a gate electrode, the shape of the sidewall 42 is different from the design. As a result, the shape and length of the LDD region, that is, the n-type region 41 immediately below the side wall 42 changes, which affects the device characteristics.

This is because immediately after the growth (as-depo
Sit) WSi layer 35 is in an amorphous state,
It is considered that although polycrystallization occurs somewhat in the process of forming the oxide film 36 at 00 ° C., polycrystallization proceeds in the higher temperature thermal oxidation process at 900 to 950 ° C., and shrinks due to a decrease in deposition due to polycrystallization.

If annealing for activating implanted ions is performed for each ion implantation, the WSi gate electrode 38 contracts even after annealing after the formation of the n-type region 41 serving as an LDD region. Side wall 4
2 will be affected.

Accordingly, it is an object of the present invention to prevent a change in device characteristics due to contraction of a WSi gate electrode.

[0015]

FIG. 1 is an explanatory view of the principle configuration of the present invention. Referring to FIG. 1, means for solving the problems in the present invention will be described. See FIG. 1 (1) In the present invention, in a method for manufacturing a semiconductor device, after a tungsten silicide layer 5 is deposited on a non-single-crystal silicon layer 4, a heat treatment at a temperature higher than a processing temperature in a subsequent manufacturing process is performed. And a step of patterning the non-single-crystal silicon layer 4 and the tungsten silicide layer 5 to form a gate electrode.

As described above, after the tungsten silicide layer 5 is deposited, a heat treatment at a temperature higher than the processing temperature in the subsequent manufacturing steps is performed, so that the tungsten silicide layer 5 is sufficiently polycrystallized before patterning. Since the tungsten silicide layer 6 can be used, the gate electrode does not shrink due to a heat treatment associated with a subsequent manufacturing process, for example, a heat treatment process such as a process of forming a through film and a process of activating implanted ions. An insulated gate semiconductor device having the above characteristics can be manufactured.

(2) The present invention is characterized in that, in the above (1), the non-single-crystal silicon layer 4 is either a polycrystalline silicon layer or an amorphous silicon layer.

As described above, the non-single-crystal silicon layer 4 serving as the underlayer of the tungsten silicide layer 5 may be a polycrystalline silicon layer or an amorphous silicon layer. Just do it.

(3) Further, according to the present invention, in the above (1) or (2), the tungsten silicide layer 5 is formed by a low pressure chemical vapor deposition method using tungsten hexafluoride and monosilane. Features.

As described above, a low pressure chemical vapor deposition method using tungsten hexafluoride (WF ₆ ) and monosilane (SiH ₄ ) is preferable as the film forming step of the tungsten silicide layer 5.

(4) In the present invention, in any one of the above (1) to (3), a sidewall is formed on a side wall of the gate electrode, and impurities are introduced into the semiconductor substrate 1 using the sidewall as a mask. It is characterized by having a process.

As described above, since the heat treatment for crystallization is performed before the step of patterning the gate electrode, the shape of the gate electrode is not deformed by the heat treatment accompanying the manufacturing process.
Even if a side wall is provided on the side wall of the gate electrode and an ion is implanted, an LDD region having a stable shape can be formed.

(5) The present invention is characterized in that in any one of the above (1) to (4), the heat treatment is performed in a nitrogen atmosphere.

When the heat treatment for crystallization of the tungsten silicide layer 5 is performed in a nitrogen atmosphere, a single-wafer lamp heating device or the like is not required, and a conventional diffusion furnace used in the conventional manufacturing process is not required. Crystallization can be performed using a heat treatment furnace.

(6) The present invention is characterized in that in any one of the above (1) to (4), the heat treatment is performed in a vacuum.

When the heat treatment for crystallization of the tungsten silicide layer 5 is performed in a vacuum, there is no need to worry about oxidation or nitridation of the tungsten silicide layer 5 at all, and lamp annealing (RTA) ) Enables high-speed processing.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Here, an embodiment of the present invention will be described with reference to FIGS. Referring to FIG. 2A, first, a p-type silicon substrate 11 is selectively oxidized using a nitride film pattern (not shown) as a mask to form a thick field oxide film 12 for element isolation, and then the nitride film pattern is removed. 7-9 thickness by thermal oxidation
A gate oxide film 13 of nm is formed.

Next, after growing a polycrystalline silicon layer 14 having a thickness of 50 to 150 nm, for example, 120 nm at 620 ° C. by LPCVD using SiH ₄ , LPCVD using SiH ₄ / WF ₆ is used. Grows a WSi layer 15 having a thickness of 50 to 150 nm, for example, 100 nm at 360 ° C. In this case, the crystalline state of the WSi layer 15 immediately after the film formation is amorphous.

Next, as shown in FIG. 2B, in a nitrogen atmosphere at 700 to 1200 ° C.
For example, heat treatment is performed at 1000 ° C. for 10 to 100 minutes, for example, 30 minutes to crystallize the WSi layer 15 and convert it to a crystallized WSi layer 16.

Next, as shown in FIG. 2C, 70 k is applied to reduce the resistance of the polycrystalline silicon layer 14.
After implanting 4 × 10 ¹⁵ cm ⁻² P ions at an acceleration energy of eV, crystallization WS in a subsequent oxidation step is performed.
In order to prevent oxidation of the i-layer 16 and out diffusion of the implanted P, high-temperature CVD at a temperature of 800 ° C.
An oxide film 17 having a thickness of 100 nm is deposited by the method.

Next, as shown in FIG. 3D, polycrystalline silicon is
Patterning layer 14 and crystallized WSi layer 16
The polysilicon gate electrode 18 and the WSi gate
A gate electrode having a two-layer structure including the gate electrode 19 was formed.
Later, dry O _Two850-950 in the atmosphere
Heat treatment at 10 ° C., for example, 900 ° C. for 10 to 15 minutes
By this, it becomes a damage prevention film at the time of ion implantation
A through film 20 having a thickness of about 50 ° is formed. Note that this
In the process, although not shown, on the side wall of the gate electrode
A thin oxide film is also formed.

In this 900 ° C. thermal oxidation step, 1000 ° C. higher than 900 ° C. in the previous heat treatment step.
In this case, the WSi layer 15 is sufficiently crystallized to be converted into the crystallized WSi layer 16, so that the patterned WSi gate electrode 19 does not shrink.

Next, referring to FIG. 3E, using the gate electrode and the field oxide film 12 as a mask, P ions 21 are applied at 10 to 30 keV, for example, 2 keV.
At an acceleration energy of 0 keV, 3 × 10 ^{13 to} 5 × 10 ¹³
An n-type region 22 having a shallow low concentration for forming an LDD region is formed by ion-implanting a cm ⁻² , for example, 4 × 10 ¹³ cm ⁻² .

Next, after depositing an SiO ₂ film on the entire surface, RIE is performed.
By performing anisotropic etching by the (reactive ion etching) method, a sidewall 2 is formed on the side of the gate electrode.
Then, using the side wall 23, the gate electrode, and the field oxide film 12 as a mask, As
By implanting the ions 24 by 9 × 10 ¹⁴ to 2 × 10 ¹⁵ cm ⁻² , for example, 1 × 10 ¹⁵ cm ⁻² at an acceleration energy of 20 to 40 keV, for example, 30 keV, a deep and high concentration n ^{A +} type source / drain region 25 is formed.

In the step of forming the side wall 23, the WSi gate electrode 19 is not shrunk, so that the side surface is almost vertical. Therefore, the side wall 23 having the designed shape can be formed. The length and shape of the LDD region immediately below the wall 23 can be formed accurately and with good reproducibility.

After that, though omitted, a heat treatment is performed in the same manner as in the prior art to activate the implanted P ions and As ions, then an interlayer insulating film and the like are provided, and then a contact hole provided in the interlayer insulating film is formed. By providing source / drain electrodes, gate lead electrodes, and the like, the MOSFET is completed.

As described above, in the embodiment of the present invention, since the crystallization annealing at a high temperature is performed before the patterning of the gate electrode, the gate electrode may contract due to the heat treatment accompanying the subsequent manufacturing process. Therefore, a MOSFET having stable element characteristics can be formed with good reproducibility.

The embodiments of the present invention have been described above. However, the present invention is not limited to the above-described conditions, and various modifications are possible. For example, polycrystalline silicon serving as a base gate electrode Layer 14 may be replaced by an amorphous silicon layer.

In that case, SiH ₄ or Si ₂ H ₆
Is used, and in the case of SiH ₄ ,
A 50 nm thick amorphous silicon layer may be deposited by growing at 0 ° C. or 450 ° C. in the case of Si ₂ H ₆ , and in that case, the thickness of the WSi layer 15 Is set to 150 nm.

In this case, the implantation conditions of P ions for lowering the resistance of the amorphous silicon layer were set to 6 × 10 ¹⁵ cm ⁻² at an acceleration energy of 40 keV, and the thickness of the oxide film formed by the high temperature CVD method was 45 nm. I do.

As described above, when the amorphous silicon layer is used as the base gate layer, the amorphous silicon is also crystallized into a polycrystalline silicon layer in the crystallization annealing step, and the final gate electrode structure becomes As in the embodiment, a two-layer structure of WSi / polycrystalline silicon is obtained.

In the description of the embodiment of the present invention,
Sets the WSi layer 15 to SiH_Four/ WF ₆Grown by the system
DOS (dichlorosilane) / WF₆Use the system
May be grown at 550 ° C.
The crystal state immediately after (as-deposit) becomes polycrystalline.
ing.

Also in this case, if the crystallization annealing is not performed, the WSi gate electrode contracts and becomes tapered in the step of forming the through film. Therefore, it is necessary to perform the crystallization annealing similarly. WS
The crystal grains of the i-layer become huge.

In the description of the embodiment of the present invention, a normal diffusion furnace or a heat treatment furnace used in a conventional manufacturing process can be used, and no new equipment is required. In this case, the load-in / load-out temperature needs to be as low as 600 ° C. in order to prevent nitridation of the WSi layer 15 and oxidation due to entrainment of the air during load-in. Therefore, since it takes time to raise / lower the temperature, the crystallization annealing may be performed in a vacuum.

In this case, a vacuum pump system for obtaining a high degree of vacuum is required, and a single-wafer lamp heat treatment apparatus is newly required. However, since the treatment is performed in a vacuum, oxidation or nitridation is required. There is an advantage that the problem does not occur at all.

Further, in the above embodiment, WS
W in the gate electrode having a two-layer structure of i / polycrystalline silicon
Although the problem of shrinkage of the Si layer is a problem, the present invention is not limited to such a two-layer structure, and a WSi layer formed by vapor phase growth is used as an electrode or a wiring layer. It is also applicable in cases where it is accompanied.

At present, other refractory metal silicide layers, for example, a cobalt silicide layer, a titanium silicide layer, or a molybdenum silicide layer are generally formed by depositing Co, Ti, or Mo by a sputtering method. Thereafter, there is no problem of shrinkage of the silicide electrode because the silicide is formed by RTA (rapid thermal annealing). An annealing step will be applied.

[0048]

According to the present invention, the crystallization annealing at a high temperature is performed before the patterning of the gate electrode, so that the WSi gate electrode does not shrink due to the heat treatment accompanying the subsequent manufacturing process and is stable. MO of device characteristics
An SFET can be formed with good reproducibility, which greatly contributes to higher performance and higher integration of a semiconductor device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a basic configuration of the present invention.

FIG. 2 is an explanatory diagram of a manufacturing process partway through an embodiment of the present invention.

FIG. 3 is an explanatory view of a manufacturing process of the embodiment of the present invention after FIG. 2;

FIG. 4 is an explanatory diagram of a manufacturing process of a conventional MOSFET halfway.

FIG. 5 is an explanatory diagram of a manufacturing process of the conventional MOSFET after FIG. 4;

FIG. 6 is an explanatory diagram of a problem in a conventional MOSFET manufacturing process.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 field insulating film 3 gate insulating film 4 non-single-crystal silicon layer 5 tungsten silicide layer 6 crystallized tungsten silicide layer 11 p-type silicon substrate 12 field oxide film 13 gate oxide film 14 polycrystalline silicon layer 15 WSi layer 16 crystal WSi layer 17 oxide film 18 polycrystalline silicon gate electrode 19 WSi gate electrode 20 through film 21 P ion 22 n-type region 23 sidewall 24 As ion 25 n ⁺ type source / drain region 31 p-type silicon substrate 32 field oxide film 33 Gate oxide film 34 Polycrystalline silicon layer 35 WSi layer 36 Oxide film 37 Polycrystalline silicon gate electrode 38 WSi gate electrode 39 Through film 40 P ion 41 n-type region 42 Side wall 43 P ion 44 n ⁺ source / drain Region 45 Oxide film

Claims (6)

[Claims] After a tungsten silicide layer is deposited on a non-single-crystal silicon layer, a heat treatment is performed at a temperature higher than a processing temperature in a subsequent manufacturing process, and then the non-single-crystal silicon layer and the tungsten silicide layer are A method for manufacturing a semiconductor device, comprising a step of forming a gate electrode by patterning. 2. The method according to claim 1, wherein said non-single-crystal silicon layer is one of a polycrystalline silicon layer and an amorphous silicon layer. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the tungsten silicide layer is formed by a low pressure chemical vapor deposition method using tungsten hexafluoride and monosilane. 4. The method according to claim 1, further comprising the step of forming a side wall on a side wall of the gate electrode, and introducing an impurity into the semiconductor substrate using the side wall as a mask. 13. The method for manufacturing a semiconductor device according to the above item. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in a nitrogen atmosphere. 6. The method of manufacturing a semiconductor device according to claim 1, wherein the heat treatment is performed in a vacuum.