JPH0810765B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a gate electrode having a polycide structure.

[0002]

2. Description of the Related Art Conventionally, phosphorus-doped polysilicon doped with phosphorus (P) as an impurity has been used as a gate electrode of a MOS field effect transistor. on the other hand,
With the trend toward miniaturization and high speed of semiconductor devices, there has been a demand for lower resistance of gate electrodes. In response to such demands, refractory metal polycide gate electrodes in which refractory metal silicide is laminated on polysilicon have been put into practical use.

FIG. 4 is a flow chart of a manufacturing process of a MOS type field effect transistor having a polycide gate electrode structure using W (tungsten) silicide as a refractory silicide, and FIGS. FIG. 6 is a process cross-sectional view showing the state of the manufacturing process in the order of processes.
A field oxide film 2 for separating elements is formed on a p-type silicon substrate 1 by a normal LOCOS method or the like, and then a film is formed on a silicon substrate in an active region surrounded by the field oxide film 2 by a dry thermal oxidation method. A gate oxide film 3 having a thickness of 15 nm is formed [(a) of FIG. 5]. Next, a non-doped polysilicon film 4b having a film thickness of 100 nm is grown by a low pressure CVD method using monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) as a source gas [(b) of FIG. 5].

Subsequently, phosphorus is introduced into the non-doped polysilicon film 4b by the ion implantation method or the thermal diffusion method to form the phosphorus-doped polysilicon film 4. For example,
When the thermal diffusion method is used, heat treatment is performed using POCl ₃ as a diffusion source, and phosphorus is introduced so that the phosphorus concentration is about 1 × 10 ²⁰ / cm ³ . Next, the W silicide film 5 is grown to a thickness of about 150 nm by the sputtering method or the CVD method [(c) of FIG. 5].

Next, the W silicide film 5 and the phosphorus-doped polysilicon film 4 are patterned by applying a usual photolithography method and a dry etching method to form a gate electrode, and arsenic (As) is used as a mask. Ions are implanted and a heat treatment for activating the dopant is performed to form the n ⁺ type diffusion layers 6 to be the source / drain regions [(d) of FIG. 5].

Further, Ti is used as a refractory metal silicide.
When (titanium) silicide is used, Ti passes through polysilicon and reaches the gate oxide film during the heat treatment for dopant activation, lowers the breakdown voltage of the gate oxide film, and causes a leak current between the gate electrode and the silicon substrate. To increase.
In order to avoid this, it is possible to interpose an amorphous carbon layer 8 between the Ti silicide film 7 and the phosphorus-doped polysilicon film 4 as shown in FIG.
It is disclosed in Japanese Patent No. 283116.

[0007]

In recent years, as semiconductor devices have been miniaturized and their performance has been improved, the number of manufacturing steps tends to gradually increase, so that the demand for reduction in man-hours is increasing. From such a background, instead of the conventional method of introducing impurities after forming a polysilicon film, a doping gas such as phosphine (PH ₃ ) is caused to flow in a low pressure CVD apparatus during film formation to form a doped polysilicon film. Things are coming to be done.

On the other hand, due to the increase in the diameter of silicon wafers, it has become difficult to form a uniform impurity concentration over the entire surface of the wafer by the conventional method, and in order to ensure the in-plane uniformity of the impurities. It has become necessary to grow silicon at low temperatures. Thus, when silicon CVD is performed in a low temperature range (600 ° C. or lower), the crystallinity of growing silicon becomes amorphous rather than polycrystal. That is, when silicon is grown at a low temperature while flowing a doping gas, a phosphorus-doped amorphous silicon film is obtained.

When this phosphorus-doped amorphous silicon film is used as the lower electrode of the refractory metal silicide electrode in place of the conventional phosphorus-doped polysilicon film, the problem that the breakdown voltage of the gate oxide film increases increases. As a result of detailed investigation of the cause of this breakdown voltage failure by the present inventor, it became clear that damage is introduced into the gate oxide film by the activation heat treatment of the implanted impurities for forming the source / drain regions. That is, stress occurs when the structure of phosphorus-doped amorphous silicon changes from an amorphous state to a polycrystal during activation heat treatment, and at this time, this stress is relaxed because the upper layer is covered with a strong refractory metal silicide. However, it was found that damage could be introduced into the gate oxide film.

As described above, in the breakdown voltage of the gate oxide film in the refractory metal polycide electrode using Ti silicide, as described above, Ti in the silicide film passes through the polysilicon and reaches the gate oxide film. The structure proposed in Japanese Patent Application Laid-Open No. 63-283166 aims to prevent the diffusion of Ti by the amorphous carbon layer in order to cope with this point. However, in the case of a polycide electrode structure in which phosphorus-doped amorphous silicon is arranged under the Ti silicide, even if an amorphous carbon layer is provided between them, the stress generated when the amorphous silicon is polycrystallized cannot be relaxed. Therefore, the breakdown voltage deterioration resulting from this cannot be suppressed.

Therefore, the object of the present invention is to prevent stress from acting on the gate oxide film during the polycrystallization process when forming the polysilicon of the polycide structure electrode using amorphous silicon as a starting material. Is to This prevents damage from being introduced into the gate oxide film and suppresses its deterioration.

[0012]

In order to achieve the above object, according to the present invention, a step of forming a non-single-crystal silicon film doped with impurities through a gate insulating film on a semiconductor substrate and a heat treatment are performed. A step of polycrystallizing or increasing the grain size of the non-single-crystal silicon film, and a step of forming a refractory metal silicide film on the formed polycrystal silicon film;
Patterning the refractory silicide film and the polycrystalline silicon film to form a gate electrode; and introducing impurities into the surface region of the semiconductor substrate using the gate electrode as a mask to form source / drain regions. A method of manufacturing a semiconductor device is provided.

The step of polycrystallizing or increasing the grain size of the non-single crystal silicon film by heat treatment is preferably performed at a temperature higher than the maximum temperature of the heat treatment step performed on the wafer thereafter. Further, the step of forming a non-single-crystal silicon film doped with impurities is performed at a relatively low temperature, and the impurities are doped at the same time when the film is formed.

[0014]

According to the present invention, after phosphorus-doped amorphous silicon (or small-grain phosphorus-doped polysilicon) film is formed, heat treatment is immediately performed to polycrystallize (or increase grain size). . At this time, since the silicide film is not formed on the amorphous silicon, the stress on the gate oxide film is suppressed, and as a result, the breakdown voltage of the gate oxide film is prevented from occurring. Since the heat treatment is performed at a temperature higher than the maximum temperature of the heat treatment to be performed thereafter, the crystal structure will not change in the subsequent process. Therefore, even if a polycide-structured gate electrode is formed using the phosphorus-doped polysilicon film formed as described above, and heat treatment is performed after arsenic ion implantation, no stress acts on the gate oxide film and the breakdown voltage thereof is reduced. Is avoided.

[0015]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a flow chart showing a manufacturing process according to an embodiment of the present invention in the order of processes, and FIG.
(D) is a process cross-sectional view showing the state of the manufacturing process in the order of processes. First, a well-known L is formed on a p-type silicon substrate 1 containing boron as an impurity and having a specific resistance of 10 Ω · cm.
A field oxide film 2 for separating active regions from each other is formed by using the OCOS method.

Then, thermal oxidation is performed on the active region defined by the field oxide film 2 in a dry oxygen atmosphere at 900 ° C. to form a gate oxide film 3 having a film thickness of 15 nm. Then, the growth temperature is 550 ° C. and the pressure is 0.1T.
orr, monosilane (SiH ₄ ) or disilane (Si
The ₂ H ₆₎ as a raw material gas, the film thickness 100nm by a low pressure CVD method using phosphine (PH ₃₎ and doping gas
The phosphorus-doped amorphous silicon film 4a is grown (at a growth temperature of 600 ° C. or lower, the obtained silicon film is in an amorphous state) [(a) of FIG. 2].

Next, heat treatment is performed in a nitrogen atmosphere in an electric resistance furnace. The heat treatment at this time is performed at a temperature equal to or higher than the highest temperature in the process that the semiconductor device will receive in the future. Since the heat treatment after the gate electrode formation in the current MOS field effect transistor is usually 950 ° C. or lower, here, for example, the heat treatment is performed at 950 ° C. for 30 minutes. By this heat treatment, the phosphorus-doped amorphous silicon film 4a is converted into the phosphorus-doped polysilicon film 4 [(b) of FIG. 2].

Next, by reverse sputtering with argon gas or wet etching using a hydrofluoric acid-based chemical,
The thin silicon oxide film on the phosphorus-doped polysilicon film 4 formed by the heat treatment is removed, followed by W and Si.
W silicide by sputtering using an alloy target of (WSi _{x: x} = 2~3) growing a film 5 to a thickness of 150 nm [in FIG. 2 (c)].

Next, the W silicide film 5 and the phosphorus-doped polysilicon film 4 are patterned by photolithography and dry etching to form a gate electrode. Then, arsenic is ion-implanted using the formed gate electrode as a mask, and the arsenic is ion-implanted at 950 ° C. for 3 hours in a nitrogen atmosphere.
An activation process for 0 minutes is performed to form the n ⁺ type diffusion layers 6 to be the source / drain regions [(d) of FIG. 2]. After that, the manufacturing of the semiconductor device of this embodiment is completed through the steps of forming an interlayer insulating film, wiring, and forming a passivation film.

FIG. 3 shows a histogram of the gate breakdown voltage of the semiconductor device thus formed and a conventional method (a W silicide film is formed on a phosphorus-doped amorphous silicon film and an activation process after As ion implantation is performed. And a withstand voltage histogram of the semiconductor device by crystallization). In the conventional method, the defect at the breakdown gate electric field of ˜5 MV / cm is 16%, whereas in the case of the present embodiment, it is 0%, and the defect at the breakdown gate electric field is 8 MV / cm or less. Is about 30% in the conventional example, whereas it is 10% in the case of the present embodiment. This defect rate is similar to that when a gate electrode is formed of polysilicon.

Next, another embodiment of the present invention will be described. In the previous embodiment, the phosphorus-doped amorphous silicon film 4a was polycrystallized in the electric resistance furnace, but in this embodiment, after the phosphorus-doped amorphous silicon film 4a is formed, the low pressure CVD apparatus is continued. Heat treatment is performed inside. That is, as shown in FIG. 2A, the growth temperature is 550 ° C., the pressure is 0.1 Torr, monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used as a source gas, and phosphine (PH ₃ ) is doped. After the phosphorus-doped amorphous silicon film 4a is grown to a thickness of 100 nm by the low pressure CVD method using gas,
The supply of the raw material gas and the doping gas is stopped, nitrogen gas is introduced into the low pressure CVD apparatus instead, the temperature is raised to 950 ° C. under the temperature rising condition of 10 ° C./min, and the state is maintained for 30 minutes. As shown in FIG. 2B, the phosphorus-doped amorphous silicon film 4a is converted into the phosphorus-doped polysilicon film 4. According to this embodiment, it is not necessary to prepare an electric resistance furnace for heat treatment, and it is possible to manufacture a semiconductor device with less equipment.

The preferred embodiment has been described above.
The present invention is not limited to these embodiments, and various changes can be made within the scope of the present invention described in the claims. For example, instead of W silicide, M
Other refractory metal silicides such as o (molybdenum), Pt (platinum), and Ti (titanium) can be used, and an oxide sidewall is formed on the sidewall of the gate electrode to form a MOS transistor. LDD (Lightly
Doped Drain) structure may be used.

[0023]

As described above, according to the method of manufacturing a semiconductor device of the present invention, phosphorus-doped amorphous silicon is grown, and heat treatment is performed at a temperature higher than the maximum temperature of the heat treatment that the semiconductor device receives later. Phosphorus-doped
Since the amorphous silicon film is converted into the phosphorus-doped polysilicon film and the refractory metal silicide film is formed on the polysilicon film to form the gate electrode of the polycide structure, according to the present invention, It is possible to prevent stress from being applied to the gate oxide film in the step of polycrystallizing the amorphous silicon and the subsequent heat treatment step. Therefore, according to the present invention, the gate electrode is not damaged and the breakdown voltage can be prevented from lowering.

Therefore, according to the present invention, it is possible to adopt a method of forming a silicon film which can reduce the impurity introduction step by one step and can secure the in-plane uniformity of the impurity, and the polycide electrode is formed by using the silicon film. Since it can be formed, it is possible to provide a highly reliable MOS type semiconductor device with less variation in characteristics, excellent high speed, and fewer steps.

[Brief description of drawings]

FIG. 1 is a flowchart showing a manufacturing process according to an embodiment of the present invention.

2A to 2C are process cross-sectional views for explaining a manufacturing process of an example of the present invention.

FIG. 3 is a histogram for explaining the effect of the embodiment of the present invention.

FIG. 4 is a flowchart showing a manufacturing process of a conventional example.

FIG. 5 is a process sectional view of a conventional example.

FIG. 6 is a sectional view of another conventional example.

[Explanation of symbols]

1 p-type silicon substrate 2 field oxide film 3 gate oxide film 4 phosphorus-doped polysilicon film 4a phosphorus-doped amorphous silicon film 4b non-doped polysilicon film 5 W silicide film 6 n ⁺ type diffusion layer 7 Ti silicide film 8 amorphous carbon layer

Claims (3)

[Claims] 1. A step of forming an impurity-doped non-single-crystal silicon film on a semiconductor substrate through a gate insulating film, and a heat treatment to polycrystallize or increase the grain size of the non-single-crystal silicon film. A step of forming a refractory metal silicide film on the formed polycrystalline silicon film, a step of patterning the refractory silicide film and the polycrystalline silicon film to form a gate electrode, and the gate electrode Forming a source / drain region by introducing impurities into the surface region of the semiconductor substrate using the mask as a mask. 2. The step of polycrystallizing or increasing the grain size of the non-single-crystal silicon film by heat treatment is performed at a temperature higher than the maximum temperature of the heat treatment step performed on the wafer thereafter. The method of manufacturing a semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein the step of forming an impurity-doped non-single-crystal silicon film is performed at a relatively low temperature, and the impurities are doped at the same time when the film is formed. Manufacturing method.