JP2830705B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a capacitance portion.

[0002]

2. Description of the Related Art In a semiconductor device such as a DRAM, it is necessary to provide a capacitance portion such as a stacked capacitor or a trench capacitor. Among them, the stacked capacitor is
Usually, it is formed as follows. That is, after growing a polysilicon film on a semiconductor substrate via an insulating film, an impurity such as phosphorus is introduced into the polysilicon film. Next, using a photoresist film, the polysilicon film is patterned by a plasma etching technique or the like to form a lower electrode. Next, the surface of the lower electrode is covered with a dielectric film made of an oxide film, a nitride film, or the like, and then, an upper electrode is formed using the same method as the method for forming the lower electrode.

[0003] When the device is miniaturized as in a 64 Mbit DRAM, the area occupied by the capacitance portion is also reduced accordingly. It has become difficult to secure the required capacity with the adoption. Therefore, as a means for effectively increasing the electrode area without increasing the area occupied by the capacitance portion, there have been proposed some techniques for providing irregularities on the surface of the lower electrode.

Japanese Patent Application Laid-Open No. 3-272165 (first conventional example) discloses that when silicon is grown at a transition temperature at which a deposited film changes from an amorphous phase to a polysilicon phase, irregularities due to silicon grain growth are formed. There is disclosed a technique that utilizes the increase in surface area that occurs on the silicon surface. FIG. 6 is a process sectional view in the case of forming a capacitance portion using this conventional technique. First, a silicon oxide film 2 is formed on a silicon substrate 1, a contact hole is formed by using a normal lithography technique and a dry etching technique, and then a polysilicon film is formed by a CVD (chemical vapor deposition) method. 8 is grown to a thickness of 200 to 500 nm. Next, a silicon oxide film 9 is grown to a thickness of 100 to 300 nm by a CVD method or the like, and then a polysilicon film 10 is grown to a thickness of 50 to 200 nm by a CVD method or the like (FIG. 6A).

Then, patterning is performed in the shape of a lower electrode by using a usual lithography technique and a dry etching technique. Further, SiH ₄ + He (SiH ₄ 20
%, He 80%) and a pressure of 1 Torr.
r, a polysilicon film 11 is grown under the condition of a growth temperature of 550 ° C., and a silicon film having a surface area approximately twice as large as that of normal polysilicon is formed (FIG. 6B). Next, an impurity such as phosphorus is introduced into the polysilicon film 11 using a thermal diffusion method or the like, and etch back is performed by a normal dry etching method to form a lower electrode (FIG. 6C). After the capacitor insulating film 6 is formed, a polysilicon film 7 is formed by a normal method, impurities such as phosphorus are introduced, and patterning of the upper electrode is performed using a normal lithography technique and a dry etching technique. [FIG. 6 (d)].

Japanese Unexamined Patent Publication No. 4-196435 (second conventional example) proposes a method of forming irregularities on the surface by annealing amorphous silicon in a vacuum or in a non-oxidizing atmosphere. According to the above publication,
When the amorphous silicon is crystallized by annealing under the above conditions, irregularities are formed on the surface of the silicon film due to crystallization from the surface and silicon migration on the surface.

Japanese Unexamined Patent Publication (Kokai) No. 3-139882 (third conventional example) proposes a method of etching a polysilicon film surface with heated phosphoric acid to form irregularities. This conventional example will be described with reference to FIG.
First, a silicon oxide film 2 is formed on a silicon substrate 1, a contact hole is formed, and then a tungsten silicide film 12 and a polysilicon film 13 are formed. Next, an impurity such as phosphorus is introduced into the polysilicon film 13, and then these two-layer films are patterned into a shape of a lower electrode by using a normal photolithography technique and a dry etching technique (FIG. 7A). ].

Next, by immersing in a phosphoric acid solution heated to about 170 ° C. for 10 to 20 minutes, the crystal grain boundaries of polysilicon are etched to form a porous silicon film 14 having an uneven surface. [FIG. 7 (b)]. At this time, the tungsten silicide film functions as a stopper for phosphoric acid etching. Subsequently, a capacitance insulating film 6 and a polysilicon film 7 are formed, and a capacitance portion is formed by using a normal photolithography technique and a dry etching technique (FIG. 7C).

[0009]

Each of the above-mentioned conventional examples has the following problems. First, in the first conventional example, among the transition temperatures at which the film formation changes from the amorphous phase to the polysilicon phase, the formation of irregularities on the surface is in a very narrow temperature range. When the processing is performed many times, there is a problem that the degree of surface irregularities changes due to particles and the like. Therefore,
In this conventional method, it is difficult to stably increase the surface area with good reproducibility, and is inferior in mass productivity. In addition, the method of the second conventional example also has a large difference in the degree of unevenness depending on the film formation conditions and the annealing conditions of the amorphous silicon, so that it is difficult to adopt the method in mass production. The increase in the surface area obtained by the above two methods is at most about twice as large as that of the ordinary method, so that the effect is not so large, and the effect is insufficient for application to a semiconductor device of 64 MDRAM or later. there were.

In the third conventional example in which the polysilicon film is treated with phosphoric acid, the etching is performed along the grain of the polysilicon. However, in the case of ordinary polysilicon, the grain is about 0.05 to 0.1 nm. For this reason, when this grain boundary is etched with phosphoric acid, it becomes fine irregularities, so that a large increase in capacity cannot be expected, and there is a problem that the withstand voltage of the capacitor insulating film is deteriorated and reliability is reduced.

[0011]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention relates to a method of manufacturing a semiconductor device having a capacitor portion composed of a lower electrode, a dielectric film and an upper electrode on a semiconductor substrate. Forming a silicon film for the lower electrode at a transition temperature at which the crystalline state of the deposited film changes from an amorphous phase to a polycrystalline phase; and performing a heat treatment at a temperature higher than the transition temperature to polycrystallize the silicon film. a step, the polycrystalline silicon film, such as phosphoric acid multilingual
Treating with crystalline silicon etching solution .

[0012]

According to the present invention, the silicon film for the lower electrode is
The film is formed in a transition temperature range in which the crystalline state changes from an amorphous phase to a polycrystalline phase. Under these film forming conditions, a silicon film in which crystal nuclei are scattered in amorphous silicon can be obtained. The degree to which crystal nuclei are included is determined by the growth temperature of silicon. That is, a silicon film having a high amorphous property can be obtained at a low film forming temperature, and the silicon film becomes closer to polysilicon as the film forming temperature increases.

This silicon film is heated at 800 to 900 ° C. for 10 minutes.
When the heat treatment is performed for about 30 minutes, a polysilicon film having a large grain size can be obtained. Since the crystallization at this time starts from the crystal nuclei in the amorphous silicon, the grain size of the obtained polysilicon largely depends on the film formation temperature of the silicon film. When this polysilicon film is etched with an etchant such as phosphoric acid, the etching proceeds along the grain boundary, so that a silicon film having large irregularities is obtained. Since the silicon film has large irregularities, a capacitor having a large capacitance can be realized when a capacitor is formed using the silicon film. And since the irregularities formed in this silicon film are determined by the grain size, the grain size can be controlled by the silicon film forming conditions. Therefore, according to the present invention, the increase in the surface area of the silicon film is stably realized with good reproducibility can do.

[0014]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a process cross-sectional view showing the state of a semiconductor device in each process step in order for explaining a first embodiment of the present invention. First, as shown in FIG. 1A, a silicon oxide film 2 is formed on a silicon substrate 1, and a contact hole is formed in the silicon oxide film 2 using a normal photolithography technique and a dry etching technique. An amorphous phase and a crystalline phase are formed using a normal LP-CVD (low-pressure CVD) method under the conditions of SiH ₄ gas and PH ₃ gas at a pressure of 0.2 to 1.0 Torr and a growth temperature of 550 to 600 ° C. Mixed silicon film 3
Is formed to a thickness of 200 to 600 nm. At this time, the concentration of P (phosphorus) in silicon is 1 × 10 ²⁰ to 1 × 10 ²¹ a.
toms / cm ³ .

Next, a heat treatment at 800 to 900 ° C. is performed in a nitrogen atmosphere for 10 to 30 minutes to completely crystallize the silicon film 3 and convert it to a polysilicon film 4. Subsequently, the polysilicon film 4 is patterned into a shape of a lower electrode by using a usual photolithography technique and a dry etching technique (FIG. 1B). Then, 150-1
The polysilicon 4 is made porous by immersing it in a concentrated phosphoric acid solution at 70 ° C. for 10 to 90 minutes to form a porous silicon film 5 having an uneven surface (FIG. 1C).

Next, a silicon nitride film (not shown) is formed by a normal LP-CVD method, and then heat-treated in an oxidizing atmosphere to form a silicon oxide film (not shown) on the surface of the silicon nitride film. ) To form a capacitance insulating film 6 made of a silicon nitride film and a silicon oxide film. Next, the polysilicon film 7 is formed to a thickness of 100 to 3 by a normal LP-CVD method.
After a film is formed to a thickness of 00 nm and impurities such as phosphorus are introduced, patterning is performed using an ordinary photolithography technique and a dry etching technique to form an upper electrode [FIG.
(D)].

When the capacitance portion is formed as described above, the capacitance value is about three times as large as the capacitance when the conventional polysilicon is used as the electrode as it is. In the present invention, a silicon film in which an amorphous phase and a crystalline phase are mixed is formed. FIG. 2 shows the relationship between the growth temperature and the capacity ratio. Transition temperature range between amorphous phase and crystalline phase (550-600
C.), the capacity of the capacity part is about three times as large. Also, FIG.
An SEM photograph of about 30,000-fold magnification of the surface after phosphoric acid treatment of polysilicon formed at 0 ° C. is shown. Grain size is 5
0-100 nm, grain boundary about 5-10 n
Since the surface roughness is not so large at about m, the increase in capacity is small. On the other hand, in the case where the method according to the present invention is followed, for example, an SEM photograph of about 30,000 times that of a silicon film formed at 580 ° C. is shown in FIG. The size of the grain is 100 to 500 nm, the size of the grain boundary is about 50 to 200 nm, and the degree of unevenness is large,
The increase in capacity is large. When the growth temperature of silicon is further lowered (500 ° C.), the size of the grains increases to 500 to 1000 nm, so that the grain boundary per area decreases and the surface area decreases when the pattern of the lower electrode becomes 2 μm or less. The problem arises that the increase in the density becomes non-uniform. As described above, the transition temperature region between the amorphous phase and the crystalline phase described in the present invention is most appropriate as the silicon growth temperature region.

The breakdown voltage distribution of the capacitor insulating film of the capacitor portion formed in this embodiment and the breakdown voltage distribution of the capacitor insulating film of the capacitor portion formed by immersing a polysilicon film formed by a normal film forming method in phosphoric acid. 4A and 4B are respectively shown in FIG. In the case of the present embodiment, a good breakdown voltage distribution can be obtained. However, in the case of the conventional example, a so-called A mode (short circuit failure mode) accident or a B mode (dielectric breakdown at a low voltage) is obtained. Failure mode), and the quality of the capacitor insulating film is degraded. This is because the unevenness of the surface is very fine (see FIG. 3 (a)), the capacitor insulating film is not formed uniformly to the depth of the grain boundary, or the electric field is generated in the capacitor insulating film partly formed thin. It is considered that the breakdown voltage distribution is deteriorated due to concentration. As described above, by using the present invention, a capacitor having excellent withstand voltage and high reliability can be formed.

In the manufacturing method according to the present invention, the degree of mixing of the amorphous phase and the crystalline phase of silicon depends on the growth conditions (particularly, temperature) of silicon. As can be seen from Fig. 2, the allowable temperature range is wide,
Further, when film formation is continued a large number of times as in the conventional example, there is no problem that the degree of unevenness of the surface changes due to particles or the like. As described above, the present invention can form unevenness on the surface with higher reproducibility than the conventional example, and thus is extremely effective as a mass production technique.

FIG. 5 is a process sectional view for explaining a second embodiment of the present invention. First, as in the case of the first embodiment, a silicon oxide film 2 is formed on a silicon substrate 1, and the silicon oxide film 2 is selectively etched using a normal photolithography technique and a dry etching technique. Then, a contact hole is formed. Next, SiH
_The silicon film 3a in which the amorphous phase and the crystalline phase were mixed was formed to a thickness of 200 using a normal LP-CVD method under the conditions of ₄ gases, a pressure of 0.2 to 1.0 Torr, and a growth temperature of 550 to 600 ° C. ６００600 nm [FIG.
(A)]. Next, phosphorus diffusion is performed at about 850 ° C. to introduce phosphorus into the silicon film 3a and completely crystallize the silicon film 3a to form a polysilicon film 4 (FIG. 5B).

Next, the polysilicon film 4 is patterned into the shape of a lower electrode by using a usual photolithography technique and a dry etching technique.
The polysilicon 4 is made porous by immersing it in a concentrated phosphoric acid solution at 0 ° C. for 10 to 90 minutes to form a porous silicon film 5 having an uneven surface (FIG. 5C). Next, a capacitor insulating film 6 and a polysilicon film 7 for an upper electrode are formed in the same manner as in the first embodiment (FIG. 5D).

The capacitance value of the capacitance section using this embodiment is also the first value.
As in the case of the embodiment, the value is about three times as large as that in the case where a normal polysilicon film is used. Good results were also obtained with respect to the breakdown voltage distribution and the reliability as in the case of the first embodiment.

In this embodiment, the silicon film 3a in which the amorphous phase and the crystal phase are mixed is changed to the polysilicon film 4 while introducing phosphorus by phosphorus diffusion. Then, a heat treatment is performed at 700 to 900 ° C. to crystallize and convert to polysilicon, and then phosphorus diffusion may be performed. In the first and second embodiments, the case where phosphorus is introduced as an impurity into silicon has been described. However, another impurity such as arsenic (As) may be used.
Further, the example of the growth temperature of silicon in which an amorphous phase and a crystal phase are mixed has been described at 550 to 600 ° C. However, if the silicon film is formed under other conditions, the temperature need not be limited to this range. In the first and second embodiments, the increase in the capacitance value is about three times. However, by increasing the thickness of the silicon film and lengthening the time of the phosphoric acid treatment, the unevenness of the surface is increased. And therefore the surface area is 3
Since the number is twice or more, it can sufficiently cope with a semiconductor device of 64 MDRAM or later.

[0024]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, a silicon film for a lower electrode is formed at the transition temperature between the amorphous phase and the crystalline phase of silicon, and the silicon film is formed at a temperature higher than the transition temperature. According to the present invention, a silicon film having a large surface irregularity can be formed because the grain boundary is increased by the heat treatment and the grain boundary is increased, followed by treatment with phosphoric acid. As a result, the capacitance value of the capacitance portion formed by using this silicon film is about three times as large as that in a case where normal polysilicon is used as it is for the electrode. In addition, the increase in the grain size increases the withstand voltage of the capacitor insulating film, thereby increasing reliability. Also, as compared with the prior art, the allowable growth temperature range of silicon is wider, and unevenness on the silicon surface can be formed with high reproducibility even when a large number of films are formed, so that a production method with high mass productivity can be provided. is there.

[Brief description of the drawings]

FIG. 1 is a process cross-sectional view for explaining a first embodiment of the present invention.

FIG. 2 is a graph showing the relationship between the growth temperature of silicon and the capacity ratio.

FIG. 3 is a scanning electron micrograph showing a particle structure of a silicon surface according to a conventional example and the present invention.

FIG. 4 is a breakdown voltage distribution diagram of a capacitor formed according to the present invention and a conventional example.

FIG. 5 is a process sectional view for explaining a second embodiment of the present invention.

FIG. 6 is a process cross-sectional view for explaining a first conventional example.

FIG. 7 is a process sectional view for explaining a third conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Silicon oxide film 3, 3a Silicon film in which amorphous phase and crystalline phase were mixed 4, 7, 8, 10, 11, 13 Polysilicon film 5, 14 Porous silicon film 6 Capacitive insulating film 9 Silicon oxide film 12 Tungsten silicide film

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Claims (6)

(57) [Claims] In a method of manufacturing a semiconductor device having a capacitor portion including a lower electrode, a dielectric film, and an upper electrode on a semiconductor substrate, a transition temperature at which a crystalline state of a deposited film changes from an amorphous phase to a polycrystalline phase. Forming a silicon film for a lower electrode by heat treatment at a temperature higher than the transition temperature to polycrystallize the silicon film; and etching the polycrystallized silicon film with polycrystalline silicon.
A method of manufacturing the semiconductor device, the method comprising: 2. The method according to claim 1, wherein an impurity is introduced into the silicon film during the step of forming the silicon film.
The manufacturing method of the semiconductor device described in the above. 3. After the formation of the silicon film, a polycrystalline silicon
2. The method according to claim 1, wherein an impurity is introduced into the silicon film before performing a process using a solution for etching the silicon film. 4. The method according to claim 3, wherein an impurity is introduced into the silicon film during a heat treatment step for polycrystallizing the silicon film. 5. The method according to claim 1, wherein a heat treatment temperature for polycrystallizing the silicon film is 700 ° C. or more and 900 ° C. or less. 6. An etching solution for treating the polycrystallized silicon film is phosphoric acid.
The manufacturing method of the semiconductor device described in the above.