JPH0620990A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPH0620990A
JPH0620990A JP17633292A JP17633292A JPH0620990A JP H0620990 A JPH0620990 A JP H0620990A JP 17633292 A JP17633292 A JP 17633292A JP 17633292 A JP17633292 A JP 17633292A JP H0620990 A JPH0620990 A JP H0620990A
Authority
JP
Japan
Prior art keywords
growing
capacitor
core
crystal
surface area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP17633292A
Other languages
Japanese (ja)
Inventor
Toshiyuki Hirota
俊幸 廣田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP17633292A priority Critical patent/JPH0620990A/en
Publication of JPH0620990A publication Critical patent/JPH0620990A/en
Withdrawn legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a capacitor with the increased bottom electrode surface area by growing a silicon crystal grains by vapor growth using a crystal growing core formed on the surface of the base as the forming core. CONSTITUTION:An element separating silicon oxide film 2 is formed on a silicon substrate 1, is exposed to the mixed atmosphere of NH3 gas and HCl gas at a temperatuer of 600-650 deg.C under a pressure of 0.1-1.0Torr for the surface roughening and nitride adsorption and a crystal growing core 3 is formed. Then, a polycrystalline silicon film 4 which is to serve as a bottom electrode is formed by the low pressure vapor growth, which uses SiH4 gas, at a growing temperature of 600-650 deg.C under a growing pressure of 0.1-1.0Torr using the crystal growing core 3 as the core. The crystal grains are grown nonuniformly and the surface roughness is promoted. Thus, the surface area of a capacitor is increased.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にキャパシタの下部電極の形成方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a lower electrode of a capacitor.

【0002】[0002]

【従来の技術】半導体装置の製造工程におけるキャパシ
タの形成方法を図2を用いて説明する。
2. Description of the Related Art A method of forming a capacitor in a semiconductor device manufacturing process will be described with reference to FIG.

【0003】まず図2(a)に示すように、シリコン基
板1上に選択酸化法により素子分離の酸化シリコン膜2
を形成する。次で下部電極となる柱状の多結晶シリコン
膜14をSiH4 ガス等から、成長温度600〜650
℃、成長圧力0.1〜1.0Torrの条件下で減圧気
相成長法によって400〜600nmの厚さに成長す
る。
First, as shown in FIG. 2A, a silicon oxide film 2 for element isolation is formed on a silicon substrate 1 by a selective oxidation method.
To form. Next, the columnar polycrystalline silicon film 14 to be the lower electrode is grown from SiH 4 gas or the like at a growth temperature of 600 to 650.
C. and a growth pressure of 0.1 to 1.0 Torr are grown to a thickness of 400 to 600 nm by the reduced pressure vapor deposition method.

【0004】次に図2(b)に示すように、リン等の不
純物のドーピングを行うと、熱履歴により結晶粒の成長
した多結晶シリコン膜14となる。
Next, as shown in FIG. 2B, when impurities such as phosphorus are doped, a polycrystalline silicon film 14 having crystal grains grown by thermal history is formed.

【0005】次に図2(c)に示すように、多結晶シリ
コン膜14をパターニングし下部電極14Aを形成す
る。
Next, as shown in FIG. 2C, the polycrystalline silicon film 14 is patterned to form a lower electrode 14A.

【0006】次に図2(d)に示すように、容量絶縁膜
5を堆積し、さらに上部電極6を形成するために多結晶
シリコン膜を下部電極形成と同様な条件下で減圧気相成
長法によって100〜200nm成長した後、不純物導
入を行い、リソグラフィー技術によってパターニングし
ていた。
Next, as shown in FIG. 2 (d), a capacitive insulating film 5 is deposited, and a polycrystalline silicon film for forming an upper electrode 6 is further formed under reduced pressure vapor deposition under the same conditions as those for forming the lower electrode. After growing 100 to 200 nm by the method, impurities were introduced and patterning was performed by the lithography technique.

【0007】[0007]

【発明が解決しようとする課題】半導体装置の微細化に
伴い、キャパシタの占有面積も次第に縮小されつつあ
る。しかしキャパシタの容量値はキャパシタ表面積に比
例するので、回路上必要とされる容量値を確保するため
にはキャパシタの占有面積(投影面積)を増やす事無
く、キャパシタ表面積を増やすことが必要である。
With the miniaturization of semiconductor devices, the area occupied by capacitors is gradually being reduced. However, since the capacitance value of the capacitor is proportional to the capacitor surface area, it is necessary to increase the capacitor surface area without increasing the occupied area (projected area) of the capacitor in order to secure the capacitance value required for the circuit.

【0008】従来技術では下部電極の厚さを厚くして、
上面だけでなく電極の側面をも利用することでキャパシ
タ表面積を増やしている。これは簡便で効果の高い手法
であるが、さらに高い容量値を得るために、下部電極の
厚さを厚くしすぎると、今度は段差が大きくなりすぎて
平坦性が劣化し、後工程に悪影響をおよぼすという問題
点が有る。
In the prior art, the thickness of the lower electrode is increased,
The surface area of the capacitor is increased by utilizing not only the upper surface but also the side surface of the electrode. This is a simple and highly effective method, but if the thickness of the lower electrode is made too thick in order to obtain a higher capacitance value, the step will become too large this time and the flatness will deteriorate, adversely affecting the post-process. There is a problem that it affects.

【0009】そこでシリコン膜の表面マイグレーション
によって形成される結晶粒の凹凸によってキャパシタ表
面積を増やす方法が、例えばエム サカオ(M.Sak
ao)等により インターナショナル エレクトロン
デバイセス ミーティングテクニカル ダイジェスト
(International ElectronDe
vices Meeting TECHNICAL D
IGEST)655頁(1990年)に報告されてい
る。しかし表面マイグレーションを起こさせるために
は、非晶質−結晶転移条件下で成膜しなければならず、
成長温度、成長圧力、ガス流量、成長膜厚等のプロセス
変数の制御が厳しい等の制約を持っている。
Therefore, a method of increasing the surface area of the capacitor by the unevenness of the crystal grains formed by the surface migration of the silicon film is disclosed in, for example, M. Sak.
ao) International Electron
Devices Meeting Technical Digest (International ElectronDe
Vices Meeting TECHNICAL D
IGEST) page 655 (1990). However, in order to cause surface migration, it is necessary to form a film under the conditions of amorphous-crystal transition,
There are restrictions such as strict control of process variables such as growth temperature, growth pressure, gas flow rate and growth film thickness.

【0010】本発明の目的は、下地の表面に比較的暖い
成膜条件で結晶粒の凹凸を形成し、下部電極の表面積を
増やしたキャパシタの形成方法を提供することにある。
An object of the present invention is to provide a method for forming a capacitor in which the surface area of a lower electrode is increased by forming irregularities of crystal grains on the surface of a base under relatively warm film forming conditions.

【0011】[0011]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、キャパシタ形成領域における下地表面に結晶
成長核を形成する工程と、この結晶成長核を形成核とし
てシリンコン結晶粒を気相成長法により成長する工程と
を含む工程によってなされる。
A method of manufacturing a semiconductor device according to the present invention comprises a step of forming crystal growth nuclei on a surface of a base in a capacitor formation region, and vapor growth of syrincon crystal grains using the crystal growth nuclei as formation nuclei. And a step of growing by a method.

【0012】[0012]

【作用】結晶成長核の形成を意図的に行うことで、不均
一核生成を起こし、シリコン結晶粒は不均一な異常成長
を起こす。これを利用して、下部電極表面の凹凸を助長
し、キャパシタ表面積を増やす。
Operation: By intentionally forming crystal growth nuclei, non-uniform nucleation occurs, and silicon crystal grains cause non-uniform abnormal growth. By utilizing this, unevenness on the surface of the lower electrode is promoted and the surface area of the capacitor is increased.

【0013】[0013]

【実施例】次に本発明の実施例について図面を参照して
説明する。図1は本発明の第1の実施例を説明するため
の半導体チップの断面図である。
Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

【0014】まず図1(a)に示すように、シリコン基
板1上に選択酸化法により素子分離の酸化シリコン膜2
を形成する。次に温度600〜650℃、圧力0.1〜
1.0Torrの条件下でNH3 ガスとHC1ガスの混
合雰囲気中に曝し、表面を荒すと共に窒化物を吸着させ
て結晶成長核3を形成する。
First, as shown in FIG. 1A, a silicon oxide film 2 for element isolation is formed on a silicon substrate 1 by a selective oxidation method.
To form. Next, the temperature is 600-650 ° C, the pressure is 0.1-
The crystal growth nuclei 3 are formed by exposing to a mixed atmosphere of NH 3 gas and HC1 gas under the condition of 1.0 Torr to roughen the surface and adsorb nitride.

【0015】次に図1(b)に示すように、結晶成長核
3を核にして、SiH4 ガスを用いる減圧気相成長法に
より、成長温度600〜650℃、成長圧力0.1〜
1.0Torrの条件下で、下部電極となる多結晶シリ
コン膜4を成長する。このとき結晶粒は不均一に成長し
(高さ400〜600nm)、表面の凹凸が激しくな
る。これによってキャパシタ表面積を増やすことが可能
となる。
Next, as shown in FIG. 1B, a growth temperature of 600 to 650 ° C. and a growth pressure of 0.1 to 5 are obtained by a reduced pressure vapor phase growth method using SiH 4 gas with the crystal growth nucleus 3 as a nucleus.
Under the condition of 1.0 Torr, the polycrystalline silicon film 4 to be the lower electrode is grown. At this time, the crystal grains grow nonuniformly (height 400 to 600 nm), and surface irregularities become severe. This makes it possible to increase the capacitor surface area.

【0016】次に図1(c)に示すように、拡散により
多結晶シリコン膜4にリン等の不純物の導入を行い、次
で図1(d)に示すように、リソグラフィー技術によっ
てパターニングし、下部電極4を形成する。
Next, as shown in FIG. 1C, impurities such as phosphorus are introduced into the polycrystalline silicon film 4 by diffusion, and then, as shown in FIG. 1D, patterning is performed by a lithography technique. The lower electrode 4 is formed.

【0017】この第1の実施例の方法によれば、下部電
極4Aの表面の凹凸を激しくできるので、従来の方法に
比べてキャパシタの電極の表面積を2.0〜3.0倍程
度に増やすことが可能になった。さらに結晶成長核の形
成と成長は堆積した多結晶シリコン上にも可能であるた
め、本実施例の方法を複数回繰り返すことによって3.
5〜4.0倍まで電極の表面積の増加が可能である。
According to the method of the first embodiment, the unevenness of the surface of the lower electrode 4A can be increased, so that the surface area of the electrode of the capacitor is increased by 2.0 to 3.0 times as compared with the conventional method. It has become possible. Furthermore, since crystal growth nuclei can be formed and grown on the deposited polycrystalline silicon, it is possible to repeat the method of this embodiment a plurality of times to 3.
It is possible to increase the surface area of the electrode by a factor of 5 to 4.0.

【0018】なお上記第1の実施例ではNH3 ガスとH
Clガスにより結晶成長核3を形成したが、水素プラズ
マによる表面処理を行い、結晶成長核を形成してもよ
い。すなわち第2の実施例としては、図1(a)におい
て、水素プラズマ処理によって酸化膜表面にシリコンの
ダングリングボンドを形成し、これを結晶成長核として
シリコンの結晶粒を異常成長させる。
In the first embodiment, NH 3 gas and H
Although the crystal growth nuclei 3 are formed with Cl gas, the crystal growth nuclei may be formed by performing surface treatment with hydrogen plasma. That is, as a second embodiment, in FIG. 1A, a dangling bond of silicon is formed on the surface of the oxide film by hydrogen plasma treatment, and using this as a crystal growth nucleus, crystal grains of silicon are abnormally grown.

【0019】これによって第1の実施例よりも激しい凹
凸のある電極表面が形成され、第1の実施例よりもさら
に約1.3倍ほど電極表面積を増やすことができる。ま
た下地にシリコンをイオン注入して結晶成長核を形成し
ても同様の効果がある。
As a result, an electrode surface having more severe irregularities than that of the first embodiment is formed, and the electrode surface area can be increased by about 1.3 times that of the first embodiment. The same effect can be obtained by forming a crystal growth nucleus by ion-implanting silicon into the base.

【0020】上記実施例では、シリコンの結晶粒を異常
成長した後に、パターニングを行い下部電極を形成した
場合について説明したが、あらかじめ多結晶シリコン膜
の下部電極を形成後に、シリコンの結晶粒を異常成長さ
せ、エッチバックにより下部電極を形成し、下部電極側
壁の表面積を増加させることもできる。また上記実施例
ではシリコン基板に接続する下部電極形成の場合につい
て説明したが、ビット線の上に層間絶縁膜を介してキャ
パシタの下部電極を形成する場合にも本発明を適用でき
る。
In the above-described embodiment, the case where the lower electrode is formed by patterning after the abnormal growth of the silicon crystal grain is described. However, after the lower electrode of the polycrystalline silicon film is formed in advance, the silicon crystal grain is abnormally formed. It is also possible to increase the surface area of the side wall of the lower electrode by growing it and forming the lower electrode by etching back. Further, in the above embodiment, the case of forming the lower electrode connected to the silicon substrate has been described, but the present invention can be applied to the case of forming the lower electrode of the capacitor on the bit line via the interlayer insulating film.

【0021】[0021]

【発明の効果】以上説明してきたように本発明によれ
ば、キャパシタの占有面積を増やすことなく、キャパシ
タの電極の表面積を従来よりも増やすことができるとい
う効果がある。さらに結晶成長核の形成と成長を複数回
繰り返すことによって従来の約5倍まで電極の表面積を
増加させることが可能である。
As described above, according to the present invention, the surface area of the electrode of the capacitor can be increased more than before without increasing the occupied area of the capacitor. Further, by repeating the formation and growth of crystal growth nuclei a plurality of times, it is possible to increase the surface area of the electrode to about 5 times that of the conventional case.

【0022】また、シリコン膜の表面マイグレーション
によって形成される結晶粒の凹凸を用いる方法とは異な
り、比較的緩い条件下で再現性よく容易に結晶粒の凹凸
を、キャパシタ形成領域の下地表面に形成することがで
きる。
Further, unlike the method of using the unevenness of the crystal grains formed by the surface migration of the silicon film, the unevenness of the crystal grains can be easily formed with good reproducibility under relatively mild conditions on the underlying surface of the capacitor formation region. can do.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1の実施例を説明するための半導体
チップの断面図。
FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

【図2】従来の半導体装置の製造方法を説明するための
半導体チップの断面図。
FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 酸化シリコン膜 3 結晶成長核 4,14 多結晶シリコン膜 4A,14A 下部電極 5 容量絶縁膜 6 上部電極 1 Silicon Substrate 2 Silicon Oxide Film 3 Crystal Growth Nuclei 4,14 Polycrystalline Silicon Film 4A, 14A Lower Electrode 5 Capacitance Insulating Film 6 Upper Electrode

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上のキャパシタ形成領域にお
ける下地表面に結晶成長核を形成する工程と、この結晶
成長核を核としてシリコン結晶粒を気相成長法により成
長させる工程とを含むことを特徴とする半導体装置の製
造方法。
1. A method comprising: a step of forming crystal growth nuclei on a base surface in a capacitor formation region on a semiconductor substrate; and a step of growing silicon crystal grains by using the crystal growth nuclei as nuclei by a vapor phase epitaxy method. And a method for manufacturing a semiconductor device.
JP17633292A 1992-07-03 1992-07-03 Production of semiconductor device Withdrawn JPH0620990A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17633292A JPH0620990A (en) 1992-07-03 1992-07-03 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17633292A JPH0620990A (en) 1992-07-03 1992-07-03 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0620990A true JPH0620990A (en) 1994-01-28

Family

ID=16011744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17633292A Withdrawn JPH0620990A (en) 1992-07-03 1992-07-03 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0620990A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0707344A3 (en) * 1994-09-19 1996-08-28 Hitachi Ltd Semiconductor device using a polysilicium thin film and production thereof
KR20010068610A (en) * 2000-01-07 2001-07-23 박종섭 Fabricating method of capacitor
KR100315016B1 (en) * 1998-06-30 2002-08-28 주식회사 하이닉스반도체 Method for forming charge storage electrode of DRAM device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0707344A3 (en) * 1994-09-19 1996-08-28 Hitachi Ltd Semiconductor device using a polysilicium thin film and production thereof
US5670793A (en) * 1994-09-19 1997-09-23 Hitachi, Ltd. Semiconductor device having a polycrystalline silicon film with crystal grains having a uniform orientation
US6187100B1 (en) 1994-09-19 2001-02-13 Hitachi, Ltd. Semiconductor device and production thereof
KR100315016B1 (en) * 1998-06-30 2002-08-28 주식회사 하이닉스반도체 Method for forming charge storage electrode of DRAM device
KR20010068610A (en) * 2000-01-07 2001-07-23 박종섭 Fabricating method of capacitor

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Effective date: 19991005