JPH06177372A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a low-resistance gate electrode on a thin gate insulating film without deteriorating the dielectric breakdown voltage of a semiconductor device. CONSTITUTION:A method of manufacturing a semiconductor device has a process for forming a gate insulating film (a gate oxide film) 3 on a semiconductor (Si) substrate 1, a process, wherein the substrate 1 formed with the film 3 is exposed to a silane-containing atmosphere and a temperature ranging from a temperature for forming an amorphous silicon layer to a temperature for forming a polycrystalline silicon layer is continuously heated up on the film 3 to form the layers 4 and 5, and a process, wherein the layers 4 and 5 are etched to form a gate electrode 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a gate electrode. In recent years, semiconductor devices have become more highly integrated and miniaturized, and even in MOS, the gate insulating film tends to be thinner due to the demand for electrical characteristics. In a commonly used polycrystalline Si gate electrode, the withstand voltage is deteriorated when the gate insulating film becomes thin, and therefore, a material and a manufacturing method that replace it are required.

[0002]

2. Description of the Related Art Conventional gate electrode materials for MOS have been mainly composed of polysilicon alone or a laminated structure of polysilicon and silicide for the purpose of low resistance, but the gate insulating film has a thickness of 200Å from 64M DRAM level. In the following, the application of amorphous silicon has been studied recently due to the problem of withstand voltage.

Amorphous Si allows the film surface at the interface with the gate insulating film to be formed smoothly, but when this is used as the gate electrode,
There is a problem that the contact resistance with, for example, a polycrystalline Si wiring formed thereon is high.

[0004]

In view of the above problems, the present invention applies amorphous Si to the gate electrode to prevent the breakdown voltage of the gate insulating film from being deteriorated, and moreover, the contact resistance with the wiring for drawing out the gate electrode. It also provides a way to lower.

[0005]

1 (a) to 1 (e) are sectional views in order of steps showing an embodiment, and FIG. 2 is a view showing an example of a temperature raising program.

[0006] The above-mentioned problems are as follows: a step of forming the gate insulating film 3 on the semiconductor substrate 1; and a step of exposing the semiconductor substrate 1 having the gate insulating film 3 to an atmosphere containing silane so that the gate insulating film 3 is not exposed. A step of continuously raising the temperature from the temperature of forming crystalline silicon to the temperature of forming polycrystalline silicon to form the amorphous silicon layer 4 and the polycrystalline silicon layer 5, and the amorphous silicon layer 4 and the polycrystalline silicon layer 5. And a step of forming the gate electrode 7 by etching the crystalline silicon layer 5.

[0007]

In the present invention, since the amorphous silicon 4 is first grown on the gate insulating film 3, the interface with the gate insulating film 3 is smooth and the withstand voltage does not deteriorate. Subsequently, since the polycrystalline silicon layer 5 is continuously formed on the amorphous silicon layer 4, the wiring for pulling out the gate electrode comes into contact with the polycrystalline silicon layer 5, and the contact resistance can be lowered. .

Further, according to the present invention, the gate insulating film 3
The amorphous silicon layer 4 to the polycrystalline silicon layer 5 are exposed by exposing the semiconductor substrate 1 on which the film has been formed to an atmosphere containing silane to increase the temperature without changing the pressure and supply amount of silane.
Since it can be continuously transferred to, the conditions under which gas flows are constant, and the generation of dust is avoided.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 (a) to 1 (e) are sectional views in order of steps showing an embodiment, and FIG. 2 is a view showing an example of a temperature raising program. Examples will be described below with reference to these drawings.

Referring to FIG. 1A, a field oxide film 2 for partitioning an element is formed on a Si substrate 1. The Si substrate 1 is thermally oxidized to form a gate oxide film 3 having a thickness of 150 Å, for example.

1 (b) and FIG. 2 The Si substrate 1 having the gate oxide film 3 formed thereon is placed in a reaction tube and evacuated, and then chemical vapor deposition (CVD) is performed on the entire surface.
A Si film is deposited by the method. An example of the temperature raising program is shown in FIG. The temperature is raised from 350 ° C. to 520 ° C. over, for example, 60 minutes, and the temperature is maintained for 15 minutes, and then silane (SiH ₄ ) is supplied into the reaction tube. The conditions are, for example, a pressure of 0.2 Torr and a gas flow rate of 300 sccm. Amorphous Si is deposited on the gate oxide film 3 to form an amorphous Si layer 4. After maintaining that state for 5 minutes, for example, leave the silane supply conditions unchanged,
For example, the temperature is raised to 620 ° C. over 10 minutes and the temperature is maintained for 5 minutes. At this stage, polycrystalline Si is deposited on the amorphous Si layer 4 to form a polycrystalline Si layer 5. After that, the supply of silane is stopped and the temperature of the Si substrate 1 is lowered.

In this way, a Si layer having a total thickness of the amorphous Si layer 4 and the polycrystalline Si layer 5 of 1000 to 1500Å was formed. The boundary between the amorphous Si layer 4 and the polycrystalline Si layer 5 is not intermittent, but gradually changes continuously from the amorphous Si layer 4 to the polycrystalline Si layer 5.

See FIG. 1 (c). Then, an amorphous Si layer 4 and the polycrystalline Si layer 5 in order to reduce the resistance of, for example, 800 ℃, PClO of 5 Torr _3, O
_The Si substrate 1 is exposed to a mixed atmosphere of ₂ for 50 minutes, for example, and phosphorus (P) is diffused in the polycrystalline Si layer 5 and the amorphous Si layer 4 to form a P-doped polycrystalline Si layer 5a and a P-doped amorphous Si layer. Form 5b.

See FIG. 1 (d). A CVD oxide film 6 having a thickness of, for example, 500 Å is formed on the P-doped polycrystalline Si layer 5a by the CVD method.

See FIG. 1 (e). The CVD oxide film 6 and P are formed using the mask for forming the gate electrode.
By etching the doped polycrystalline Si layer 5a and the P-doped amorphous Si layer 5b, the P-doped polycrystalline Si layer 5a and the P-doped amorphous S layer 5a are etched.
The gate electrode 7 composed of the i layer 5b is formed. After that, although not shown, the source / drain are formed by a known method. After forming the interlayer insulating film, wiring is performed using, for example, polycrystalline Si.

Gate oxide film 3 and P-doped amorphous Si layer 5b
The interface of is smooth. Therefore, the dielectric strength of the gate oxide film 3 does not deteriorate. The gate electrode is, for example, polycrystalline Si
Connected to the wiring. Since the polycrystalline Si wiring has a low resistance,
For example, phosphorus (P) is doped as an impurity. The out-diffusion of impurities from polycrystalline Si is smaller than the out-diffusion of impurities from amorphous Si. It is desirable to place polycrystalline Si.

The contact resistance between polycrystalline Si and polycrystalline Si is smaller than that between polycrystalline Si and amorphous Si. From this point as well, the upper portion of the gate electrode should be polycrystalline Si. Is desirable.

It should be noted that from the deposition of the amorphous Si layer 4 to the polycrystalline S
The change to the deposition of the i-layer 5 can be performed only by raising the temperature without changing the silane supply condition. There is no soaring, and no dust accumulates on the substrate surface.

Further, the process is simplified and the process time is shortened.

[0020]

As described above, according to the present invention,
The interface between the gate insulating film and the gate electrode is smooth, and the breakdown voltage does not deteriorate. The resistance of the gate electrode is reduced, and the contact resistance between the gate electrode and the wiring above it is also reduced. Furthermore, the process is simplified and the process time is shortened.

The present invention contributes to high integration and miniaturization of semiconductor devices.

[Brief description of drawings]

1A to 1E are cross-sectional views in order of the processes, showing an embodiment.

FIG. 2 is a diagram showing an example of a temperature raising program.

[Explanation of symbols]

 1 is a semiconductor substrate, Si substrate 2 is a field insulating film, field oxide film 3 is a gate insulating film, gate oxide film 4 is an amorphous Si layer 5 is a polycrystalline Si layer 4a is P-doped amorphous Quality Si layer 5a is P-doped polycrystalline Si layer 6 is CVD oxide film 7 is gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/62 G 7376-4M 21/336

Claims (1)

[Claims] 1. A step of forming a gate insulating film (3) on a semiconductor substrate (1), exposing the semiconductor substrate (1) having the gate insulating film (3) to an atmosphere containing silane, Amorphous silicon layer (4) and polycrystalline silicon layer (5) are formed by continuously raising the temperature from the temperature at which amorphous silicon is formed on the insulating film (3) to the temperature at which polycrystalline silicon is formed. A method for manufacturing a semiconductor device, comprising: a step; and a step of etching the amorphous silicon layer (4) and the polycrystalline silicon layer (5) to form a gate electrode (7).