JP2699625B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a capacitor.

[Conventional technology]

2. Description of the Related Art Conventionally, a semiconductor device provided with a capacitance portion composed of a lower electrode made of polysilicon, a capacitance insulating film, and an upper electrode has been manufactured as follows. A polysilicon layer is grown from a gas containing silane (SiH ₄ ) on a semiconductor substrate,
Impurities such as phosphorus and arsenic are introduced into this polysilicon layer by diffusion or ion implantation, heat treatment is performed at about 900 ° C. to activate the impurities, and then patterning is performed by etching using a photoresist to form a lower electrode. To form
A silicon oxide film or a silicon nitride film as a capacitor insulating film is formed thereon. Next, a polysilicon layer is grown again on the capacitor insulating film, and an impurity such as phosphorus is diffused and patterned to form an upper electrode.

[Problems to be solved by the invention]

In the conventional method for manufacturing a semiconductor device described above, the polysilicon layer of the lower electrode is formed at 600 to 650 ° C. using a silane-based gas.
Therefore, there is a problem that unevenness on the surface of the polysilicon layer of the lower electrode becomes large, and the leakage current characteristics and reliability of the capacitor insulating film formed on the lower electrode are deteriorated.

At a low temperature of 550 ° C. or lower, a silane gas is used to grow an amorphous silicon layer and to perform a heat treatment to obtain a polysilicon layer with small surface irregularities. Since the speed is as low as 10 ° / min or less, it is not practical for mass production of semiconductor devices.

According to the above-described conventional method for manufacturing a capacitor, a polysilicon layer is grown from a gas system containing silane and an impurity such as phosphorus (P) is introduced to form a lower electrode. _An amorphous silicon layer is grown from a gas system containing 2H ₆ ), and then phosphorus is introduced into the amorphous silicon layer by ion implantation, followed by heat treatment to crystallize the amorphous silicon layer. There is a difference that the lower electrode is formed after the polysilicon layer is formed.

[Means for solving the problem]

The method for manufacturing a semiconductor device according to the present invention includes the steps of:
Growing an amorphous silicon layer by a method D, introducing an impurity into the amorphous silicon layer by an ion implantation method, and heat-treating the amorphous silicon layer to form the amorphous silicon layer. Crystallizing the polycrystalline silicon into a polysilicon layer and activating the impurities, and patterning the polysilicon layer to form an electrode.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIGS. 1A to 1G are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is an amorphous silicon layer, 31 is an amorphous silicon layer into which phosphorus (P) is ion-implanted, 32 is a polysilicon layer containing P, 33 is The lower electrode, 4 is a capacitance insulating film, and 5 is an upper electrode.

First, as shown in FIG. 1A, a silicon oxide film 2 is formed on a silicon substrate 1 by oxidation or the like.

Next, as shown in FIG. 1 (b), disilane (Si ₂ H ₆ )
Amorphous silicon layer 3 by the CVD method using a gas system containing
Grow 2000-8000mm thick. Examples of growth conditions in this case are a growth temperature of 500 to 550 ° C., a pressure of 0.1 to 1 Torr, a flow rate of disilane of 100 to 1000 cc / min, and a growth rate of 50 to 100 ° / min.

Next, as shown in FIG. 1C, P is introduced into the amorphous silicon layer 3 by an ion implantation method. P to be ion-implanted is about 10 ¹⁷ to 10 ²¹ cm ^{-3 in} the amorphous silicon layer.

Next, as shown in FIG.
A heat treatment at a temperature of about 900 ° C. is performed for 5 minutes to 1 hour to crystallize the amorphous silicon layer 31 containing P and to form a polysilicon layer 32 containing P.
To form At this time, the specific resistance of the polysilicon 32 containing P is 10 ^-4 to 10 ^-1 Ω-cm.

Next, as shown in FIG. 1E, etching is performed using a photoresist, and the polysilicon layer 32 containing P is patterned to form a lower electrode 33.

Next, as shown in FIG. 1F, a capacitance insulating film 4 such as a silicon nitride film or a silicon oxide film is formed on the lower electrode 33.

Further, as shown in FIG. 1 (g), a polysilicon layer is grown thereon, and after P is diffused, patterning is performed to form an upper electrode 5, thereby completing a capacitor section.

The capacitance portion is formed by using the silicon nitride film as the capacitance insulating film, and the breakdown voltage distribution of the capacitance insulating film at the time of the current density J = 10 ⁻⁵ A / cm ² is the second.
Shown in the figure. The horizontal axis in FIG. 2 is the electric field strength (MV / cm) applied to the capacitive insulating film, and the vertical axis is the failure rate, that is, the breakdown rate (%), compared to the conventional example shown in FIG. do it,
According to this embodiment, it is found that the breakdown voltage is improved by about 1 MV / cm. In addition, the low electric field strength (~ 3M
V / cm). This is because when the polysilicon layer of the lower electrode is formed as in the embodiment, the irregularities on the surface of the polysilicon layer are very small as compared with the conventional polysilicon layer, and the weak spots and pins on the capacitive insulating film due to the irregularities are formed. It is thought that the hole disappeared.

As described above, according to the first embodiment, it is possible to manufacture a semiconductor device having a capacitance portion with excellent withstand voltage distribution and improved reliability. Further, since the growth rate of the amorphous silicon layer using disilane is 50 to 100 ° / min, the growth rate of the conventional polysilicon layer is almost the same, and there is no practical problem.

4A to 4H are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention. In the second embodiment, the heat treatment for crystallizing the amorphous silicon layer into which P is ion-implanted is performed in two stages.

First, as shown in FIG. 4A, a groove is formed on a silicon substrate 1, and a silicon oxide film 2 is formed and patterned inside the groove.

Next, as shown in FIG. 4B, an amorphous silicon layer 3 is formed on the entire surface by a CVD method using a gas system containing disilane.
Grow to a thickness of ~ 2000mm. An example of growth conditions in this case is
Growth temperature 500 ~ 550 ℃, pressure 0.1 ~ 1Torr, disilane flow rate 100
At ~ 1000cc / min, the growth rate is 50-100〜 / min.

Next, as shown in FIG. 4C, P is introduced into the amorphous silicon layer 3 by an ion implantation method. P for ion implantation
Is about 10 ¹⁷ to 10 ¹⁹ cm ^{−3 in} the amorphous silicon layer.

Next, as shown in FIG. 4D, heat treatment is performed at 600 to 650 ° C. for 2 to 12 hours to crystallize the P-containing amorphous silicon layer 31 to form a P-containing polysilicon layer 32. further,
As shown in FIG. 4 (e), 800-900 ° C. in a nitrogen atmosphere
Is performed for 5 minutes to 1 hour to activate P. At this time, the specific resistance of the polysilicon layer 32 containing P is 10 ^-4 to 10 ^-1 Ω.
−cm.

Next, as shown in FIG. 4F, etching is performed using a photoresist, and the polysilicon layer 32 containing P is patterned to form a lower electrode 33.

Next, as shown in FIG. 4 (g), a capacitance insulating film 4 such as a silicon nitride film or a silicon oxide film is formed on the lower electrode 33. Next, as shown in FIG. 4 (h), a polysilicon layer is grown on the entire surface, and after P is diffused, patterning is performed to form an upper electrode 5.

As in the second embodiment, when the heat treatment for crystallizing the P-containing amorphous silicon layer is performed at a low temperature (600 to 700 ° C.), the crystal grains of the crystallized P-containing polysilicon layer are reduced. The size becomes several μm, larger crystal grains are obtained as compared with the first embodiment, and irregularities on the lower electrode surface are further reduced. The capacitance insulating film of the second embodiment also has a good breakdown voltage distribution and good reliability as in the first embodiment.

In the above embodiment, a case where a silicon nitride film or a silicon oxide film is used as the capacitor insulating film has been described. However, a multilayer film of a silicon nitride film and a silicon oxide film may be used, or a metal having a high dielectric constant such as tantalum oxide may be used. An oxide film may be used, and the effect remains unchanged. Although the polysilicon layer is used as the upper electrode, a silicide electrode such as tungsten silicide, a polycide electrode combining polysilicon and silicide, a refractory metal electrode such as tungsten and molybdenum, and a combination of these electrodes are used. Is also free. Further, the upper electrode may be formed of amorphous silicon in the same manner as the lower electrode. Further, the case where P is used as an impurity to be introduced into the amorphous silicon layer has been described, but As or B may be used.

〔The invention's effect〕

As described above, the present invention grows amorphous silicon by a CVD method using a gas system containing disilane, then puts impurities such as phosphorus into the amorphous silicon by ion implantation, and further performs heat treatment. By forming the lower electrode made of polysilicon by crystallization, the unevenness on the surface of the lower electrode becomes small and smooth. Therefore, a capacitor insulating film without weak spots, pinholes, and the like can be formed, and a semiconductor device having a capacitor portion with good withstand voltage distribution and high reliability can be obtained.

[Brief description of the drawings]

1 (a) to 1 (g) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention, and FIGS. 2 and 3 show withstand voltage distributions of a capacitor insulating film according to the embodiment and a conventional example. Figure showing
4A to 4H are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention. 1 ... silicon substrate, 2 ... silicon oxide film, 3 ... amorphous silicon layer, 31 ... amorphous silicon layer containing P, 32
... P-containing polysilicon layer, 33... Lower electrode, 4.
Capacitance insulating film, 5 ... upper electrode.

Claims (1)

(57) [Claims] A step of growing an amorphous silicon layer on a semiconductor substrate by a CVD method; a step of introducing an impurity into the amorphous silicon layer by an ion implantation method; A semiconductor device comprising: a step of heat-treating a layer to crystallize the amorphous to form a polysilicon layer and activate the impurities; and a step of patterning the polysilicon layer to form an electrode. Manufacturing method.