JPH04101454A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance high reliability by growing amorphous silicon based on a CVD process which uses a gas group including disilane, ion-implanting impuri ties, such as silicon into amorphous silicon, crystallizing through heat treatment, and, forming an electrode made of polysilicon. CONSTITUTION:After a silicon oxide film 2 is formed on a silicon substrate 1, an amorphous silicon layer 3 is arranged to grow based on an CVD process which uses disilane. After P is introduced into the amorphous silicon layer based on an ion implantation process, heat treatment is carried out in a nitrogen atmosphere, an amorphous silicon layer 31, which contains P, is crystallized so that a polysilicon layer 32 with P may be formed. Then, the layer is etched with a photoresist where the polysilicon layer 32 is patterned, thereby forming a lower electrode 33. After the formation of the electrode 33, a capacity insula tion film 4, such as a silicon nitride film or a silicon oxide film is formed there on. The polysilicon layer is adapted to further grow thereon. After P is diffused, the layer is patterned so as to form an upper electrode 5. This construction makes it possible to enhance the pressure distribution and manufacture a capac ity section whose reliability is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a capacitor.

[Conventional technology]

Conventionally, a semiconductor device including a capacitor section including a lower electrode made of polysilicon, a capacitor insulating film, and an upper electrode has been manufactured as follows. Silane (
A polysilicon layer is grown from a scum system containing SiH4), impurities such as phosphorus and arsenic are introduced into this polysilicon layer by diffusion or ion implantation, and heat treatment is performed at approximately 900°C to activate the impurities. Next, patterning is performed by etching using a photoresist to form a lower electrode, and a silicon oxide film or silicon nitride film as a capacitor insulating film is formed thereon. Next, a polysilicon layer is grown again on this capacitive insulating film, and patterned by diffusing impurities such as phosphorus to form an upper electrode.

[Problem to be solved by the invention]

In the conventional semiconductor device manufacturing method described above, the polysilicon layer of the lower electrode is heated to 600 to 65% by using a silane-based gas.
Since the polysilicon layer of the lower electrode is formed at a growth temperature of 0 degrees Celsius, the surface irregularities of the polysilicon layer become large, which deteriorates the leak current characteristics and reliability of the capacitive insulating film formed on the lower electrode. There is.

In addition, by using Silancus and growing an amorphous silicon layer at a low temperature of 550°C or less and performing heat treatment,
Although it is possible to obtain a polysilicon layer with small surface irregularities, the growth rate of the amorphous silicon layer in this case is very slow at less than 10 people/min, so it is not practical for use in mass production of semiconductor devices.

In the conventional manufacturing method of the capacitor section described above, a polysilicon layer is grown from a scum system containing silane, and an impurity such as phosphorus (P) is introduced to form a lower electrode.
An amorphous silicon layer is grown from a scum system containing disilane (Si2H6), then phosphorus is introduced into the amorphous silicon layer by ion implantation, and then heat treatment is performed to crystallize the amorphous silicon layer. The difference is that the lower electrode is formed after the polysilicon layer is formed by chemical conversion.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes a step of growing an amorphous silicon layer on a semiconductor substrate by a CVD method using disilane, and a step of introducing impurities into the amorphous silicon layer by an ion implantation method. , a step of heat-treating the amorphous silicon layer containing impurities to crystallize it into a polysilicon layer, and a step of patterning the polysilicon layer to form an electrode.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(g) are cross-sectional views of a semiconductor chip for explaining a first embodiment of the present invention.

In the figure, 1 is a silicon substrate, 2 is a silicon oxide film, 3 is an amorphous silicon layer, 31 is an amorphous silicon layer into which phosphorus (P) is ion-implanted, 32 is a polysilicon layer containing P, and 33 is a polysilicon layer containing P. 4 is a lower electrode, 4 is a capacitive insulating film, and 5 is an upper electrode.

First, as shown in FIG. 1(a), a silicon oxide film 2 is formed on a silicon substrate 1 by oxidation or the like.

Next, as shown in Figure 1(b), disilane (Si2H6
) The amorphous silicon layer 3 is grown to a thickness of 2000 to 8000 Å by a CVD method using a gas system containing . Examples of growth conditions in this case are a growth temperature of 500 to 550°C and a pressure of 0.
The growth rate is 50-100 people/min with a 4-1 Torr disilane flow rate of 100-1000 cc/min.

Next, as shown in FIG. 1(c), P
is introduced into the amorphous silicon layer 3. P for ion implantation
The concentration in the amorphous silicon layer is about 1017 to 10 cm-'.

Next, as shown in FIG. 1(d), 800
Heat treatment at ~900° C. is performed for 5 minutes to 1 hour to crystallize the P-containing amorphous silicon layer 3 to form a P-containing polysilicon layer 32. At this time, polysilicon 32 containing P
The resistivity of is 10-4 to 10 Ω-cm.

Next is the 14th? ] As shown in (e), etching is performed using a photoresist to form a polysilicon layer 32 containing P.
The lower electrode 33 is formed by patterning.

Next, as shown in FIG. 1(f), a capacitor insulating film 4 such as a silicon nitride film or a silicon oxide film is formed on the lower electrode 33.

Further, as shown in FIG. 1(g), a polysilicon layer is grown on this layer, P is diffused and patterned to form an upper electrode 5 and complete the capacitor section.

FIG. 2 shows the breakdown voltage distribution of the capacitive insulating film when the capacitive part is formed using a silicon nitride film as the capacitive insulating film and the current density is J = 10-5 A/cm2. The horizontal axis in Figure 2 is the electric field strength (MV/cm) applied to the capacitive insulating film,
The vertical axis shows the failure rate, that is, the percentage of broken parts (%).
Compared to the conventional example shown in the figure, when this example is used, approximately 1
, MV/cm, it can be seen that the breakdown voltage is improved. In addition, the low electric field strength seen in the conventional example (~3 MV
/cm) is no longer observed.

This is because when the polysilicon layer of the lower electrode is formed as in the example, the unevenness on the surface of the polysilicon layer is very small compared to the conventional polysilicon layer, and the unevenness causes weak spots and pins in the capacitor insulating film. This is thought to be due to the lack of holes.

In this way, according to the first embodiment, there is a gap in the breakdown voltage distribution.
In addition, a semiconductor device including a capacitor portion with improved reliability can be manufactured. Furthermore, since the growth rate of an amorphous silicon layer using disilane is 50 to 100 people/min, the growth rate of a conventional polysilicon layer is approximately the same, and there is no practical problem.

FIGS. 4(a) to 4(h) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.

In the embodiment of Mizui 2, heat treatment for crystallizing an amorphous silicon layer into which P ions are implanted is performed in two stages.

First, as shown in FIG. 4(a), a groove is formed on a silicon substrate 1, and a silicon oxide film 2 is formed inside the groove and patterned.

Next, as shown in FIG. 4 (one), an amorphous silicon layer 3 is grown over the entire surface to a thickness of 300 to 2,000 layers by CVD using a gas system containing disilane. Examples of growth conditions in this case are a growth temperature of 500 to 550°C and a pressure of 0.1 to 1
To r r, disilane flow rate 100~], 0OOcc/
minutes, and the growth rate is 50-100 people/minute.

Next, as shown in FIG. 4(C), P
is placed in the amorphous silicon layer 3. The concentration of P to be ion-implanted in the amorphous silicon layer is about 1017 to 1019 cm-3.

Next, as shown in FIG. 4(d), heat treatment is performed at 600 to 650°C for 2 to 12 hours, and the P-containing amorphous silicon layer 3
A polysilicon layer 32 containing P1 is crystallized. Furthermore, as shown in FIG. 4(e), heat treatment at 800 to 900'C in a nitrogen atmosphere was performed for 5 minutes to 1 hour.
Activate. At this time, polysilicon layer 32 containing P
The specific resistance is 10-4 to 10-1 Ω-cm.

Next, as shown in FIG. 4(f), etching is performed using a photoresist to pattern the P-containing polysilicon 7132 to form the lower electrode 33.

Next, as shown in FIG. 4(g), a capacitor insulating film 4 such as a silicon nitride film or a silicon oxide film is formed on the lower electrode 33. Next, as shown in FIG. 4(h), a polysilicon layer is grown over the entire surface, and after P is diffused, patterning is performed to form the upper electrode 5.

As in the example of Mizui 2, the heat treatment to crystallize the amorphous silicon layer containing P is carried out at a low temperature (600 to 700°C).
), the size of the crystal grains in the polysilicon layer containing crystallized P becomes several μm, and larger crystal grains are obtained compared to the first example, and the unevenness on the surface of the lower electrode is further reduced. . Similarly to the first embodiment, the capacitive insulating film of the second embodiment has good breakdown voltage distribution and good reliability.

In addition, in the above embodiment, the case where a silicon nitride film or a silicon oxide film is used as the capacitive insulating film is explained.
Using a multilayer film of silicon nitride film and silicon oxide film,
A metal oxide film with a high dielectric constant such as tantalum oxide may also be used, and the effect will not change. In addition, although a polysilicon layer was used as the upper electrode, silicide electrodes such as tungsten silicide, polycide electrodes that combine polysilicon and silicide, high-melting point metal electrodes such as tungsten and molybdenum, and combinations of these electrodes may also be used. You are also free to use Further, the upper electrode may also be formed from amorphous silicon like the lower electrode. Furthermore, although the case has been described in which P is used as an impurity introduced into the amorphous silicon layer, As or B may also be used.

〔Effect of the invention〕

As explained above, the present invention involves growing amorphous silicon by CVD using a gas system containing disilane, then implanting impurities such as phosphorus into the amorphous silicon by ion implantation, and then performing heat treatment. By crystallizing and forming the lower electrode made of polysilicon, the unevenness on the surface of the lower electrode becomes smaller and smoother. Therefore, it is possible to form a capacitor insulating film without weak spots or pinholes, etc., and it is possible to obtain a semiconductor device having a capacitor portion with good breakdown voltage distribution and high reliability.

[Brief explanation of the drawing]

FIGS. 1(a) to (g) are cross-sectional views of a semiconductor chip for explaining the first embodiment of the present invention, and FIGS. 2 and 3 are breakdown voltage distributions of capacitive insulating films according to the embodiment and the conventional example. A diagram showing
FIGS. 4(a) to 4(h) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Silicon oxide film, 3... Amorphous silicon layer, 31... Amorphous silicon layer containing P,
32... Polysilicon layer containing P, 33... Lower electrode, 4... Capacitive insulating film, 5... Upper electrode.

Claims (1)

[Claims] a step of growing an amorphous silicon layer on a semiconductor substrate by a CVD method using disilane; a step of introducing impurities into the amorphous silicon layer by an ion implantation method;
A method for manufacturing a semiconductor device, comprising the steps of heat-treating the amorphous silicon layer containing impurities to crystallize it into a polysilicon layer, and patterning the polysilicon layer to form an electrode.