JPH05102145A - Method for forming polysilicon wiring - Google Patents

Abstract

PURPOSE:To form polysilicon wiring by flattening the wiring from the first layer through a relatively simple process by uniformly implanting impurity ions throughout a section including a wiring pattern after injecting oxygen into the section corresponding to the wiring pattern of a polysilicon layer and forming silicon dioxide by annealing. CONSTITUTION:A wiring pattern of polysilicon is formed on a semiconductor substrate. At the time of forming the wiring pattern, polysilicon 13 is deposited on the section proposed to the wiring pattern of the substrate 11. Then, after injecting oxygen into the section corresponding to the wiring pattern by using a mask 15 formed on the section, SiO2 17 is formed by annealing. After forming the SiO2 17, the wiring pattern of the polysilicon 13 isolated by the SiO2 17 is formed by uniformly implanting impurity ions throughout an area including the wiring pattern. For example, in order to flatten the wiring layer by only removing expanded parts of the SiO2 17, selective etching is performed by using an HF gas.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a polysilicon wiring for forming a flattened wiring pattern which enables multi-layer wiring.

[0002]

2. Description of the Related Art Conventionally, wiring in an integrated circuit provides a degree of freedom in coupling semiconductor elements arranged in a substrate and enhances the degree of integration of devices, so that a planar wiring pattern width required for wiring is reduced. However, as a solution to this, multi-layering of wiring has been performed as an effective method.
For example, in a recent MOS LSI, in addition to the fact that the silicon gate structure is substantially a multi-layer wiring,
In the field of SI (gate array etc.), the double-layering of Al wiring has also been put into practical use, and polysilicon gates have been doubled into two to three layers.

The advantage of such a multi-layer wiring technique is that since each semiconductor element can be laid out without considering the space for wiring on the chip, the degree of integration and density are improved and the chip size is reduced. It is in. Further, the degree of freedom of wiring is increased, pattern design is facilitated, and wiring resistance and current capacity can be set with a margin.

On the other hand, the disadvantages are that the process is complicated, the surface irregularities are remarkable, and a new device failure mode is generated. The remarkable unevenness of the surface means that the wiring is broken at the step,
The wiring is partially thinned on the surface of the severe unevenness, which causes disconnection and migration due to current concentration. In order to solve this, it is desired that the step can be removed and the thin film can be formed and processed on a flat surface at all times.
Therefore, various flattening techniques have been devised for the purpose of forming an ideal multi-layer wiring structure having no step.

For example, as a method for forming a planarized polysilicon wiring, there is a method shown in FIG. First, a step of forming a polysilicon film 103 in a region 101 where a wiring pattern is to be formed by CVD (see FIG. 3A), and a step of ion-implanting or depositing impurities (see FIG. 3B). , A step of forming a resist film 105 having a shape corresponding to the wiring portion by diffusing phosphorus by annealing (see FIG. 3C), and a polysilicon (poly-
Si) is selectively etched, and then the doped polysilicon 103 and the resist film 105 are selectively stripped by an ashing method in a resist and oxygen plasma (see FIG. 3D), and an interlayer is formed by using CVD. Insulating film 10
7 (see FIG. 3E) and a reflow process for flattening the surface irregularities, and then the resist 1
09 (see FIG. 3F) and a step of removing the surface layers 107 and 109 by overall etching (FIG. 3).
(See (g)). This conventional wiring forming method is a method of planarizing the thin film side covering the wiring.

[0006]

However, in the method of planarizing as described above, the step for planarizing is additionally included, which complicates the process, and the interlayer insulating film is used for planarizing. Since the film thickness is adjusted, there is a problem in that each film thickness is not uniform and an insulating film defect that causes an interlayer short circuit or a leak is likely to occur.

An object of the present invention is to solve the above problems and to provide a method of forming a polysilicon wiring which can be formed by planarizing the polysilicon wiring from the first layer by a relatively simple process.

[0008]

According to the present invention, in order to solve the above problems, in forming a wiring pattern of polysilicon on a semiconductor substrate, polysilicon is deposited on the semiconductor substrate on which the wiring pattern is to be formed. And a step of masking a portion corresponding to the wiring pattern,
Insulating the silicon dioxide by the steps of injecting oxygen from above the mask and then annealing it to form silicon dioxide, and uniformly injecting impurity ions into the entire region including the wiring pattern. Provided is a method for forming a polysilicon wiring, which is characterized by forming a wiring pattern made of polysilicon.

[0009]

According to the method of the present invention, a polysilicon film to be a wiring pattern is masked in accordance with the wiring portion, oxygen ions are implanted, and annealing is performed to form a region other than the wiring portion as an insulating layer of SiO ₂ , Then, the conductivity of the wiring portion can be adjusted by uniformly implanting impurity ions over the entire region including the wiring pattern.

Therefore, since the interlayer insulating film formed after the above steps is formed on the flat surface, the thickness of the thin film is not partially thinned, and the disconnection or the fusion due to the current concentration or migration occurs. It also eliminates the possibility of occurrence of.

The polysilicon is formed by a general method. For example, the vapor phase growth is performed by the low pressure CVD method. The growth conditions at this time are not particularly limited. As the mask material, a general mask material is used.

By annealing the polysilicon film, the crystallinity is recovered and the properties of the polysilicon (SiO ₂ ) surface are improved.

The impurity ions are not particularly limited,
A commonly used n-type dopant such as phosphorus may be selected. The injection amount is, for example, 1 × 10 ¹⁹
It is preferably 1 × 10 ²¹ pieces / cm ² .

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a polysilicon wiring of the present invention will be described in detail below. 1 and 2 show steps (a) to (f) in the middle of performing the method for forming a polysilicon wiring according to the present invention. These wiring forming steps will be described in order.

(A) Polysilicon Growth Step First, a region 1 where a wiring pattern is to be formed on a wafer.
A polysilicon film 13 is formed on the surface 1. Polysilicon film 1
3 is formed with a film thickness of 450 nm by a low pressure CVD method using dichlorosilane as a reaction gas.

(B) Resist Forming Step A resist pattern 13 is formed by photolithography.

(C) Oxygen ion implantation step Using the resist pattern 15 as a mask, the polysilicon film 13 is implanted with oxygen ions. The injection amount is, for example, 1
× 10 ¹⁹ pieces / cm ² and implantation energy of 30 to
It is set to 40 keV. The resist pattern is removed by etching. Then, for diffusing oxygen, for example A
Annealing is performed at a temperature of about 900 ° C. for 1 hour in an atmosphere of r. By this step, the insulating film 17 of silicon dioxide is formed between the polysilicon films 13 to be the wiring pattern.

(D) Selective etching step Si formed by oxygen ion implantation and annealing
In order to flatten the wiring layer by removing the bulge in the O ₂ part,
A wiring layer made of polysilicon (poly-Si) and SiO _{2 is} selectively etched using HF gas. By this step, the planarization of the polysilicon wiring is extremely effectively performed.

(E) Ion Implantation or Deposition Process of Impurities Phosphorus is implanted / doped into the polysilicon film 13 in order to make the polysilicon film 13 conductive. As a method of injecting or doping phosphorus, phosphorus is doped at 850 ° C. by a bubbling method of phosphorus oxychloride.
The doping amount of phosphorus is in the range of 10 ¹⁹ to 10 ²¹ pieces / cm ² . Then, in order to diffuse impurities, 850
Anneal at a temperature of about C for 1-2 hours.

(F) Interlayer insulating film forming step An interlayer insulating film 19 such as a silicon oxide film (SiO ₂ ) or a phosphor glass film (PSG) is formed by the CVD method. As described above, the polysilicon wiring is formed. The above steps are shown in the flow chart of FIG.

Although the method for forming the polysilicon wiring of the present invention has been described in detail above, this method is not limited to the above-mentioned wiring forming example, but can be variously applied or applied. In particular, it is a useful technique as a wiring technique having a multi-layer structure because it can be planarized in a simple process.

[0022]

As can be seen from the above detailed description, in the method for forming a polysilicon wiring according to the present invention, the above-described steps can achieve the planarization at the stage before the formation of the interlayer insulating film. As described above, it is not necessary to flatten the interlayer insulating film. Therefore, the thickness of the interlayer insulating film does not become partially thin, and there is no fear of disconnection, fusing due to current concentration, migration, or the like.

[Brief description of drawings]

FIG. 1 is a schematic process drawing showing a process of forming a polysilicon wiring according to the present invention.

FIG. 2 is a flow chart showing the steps of the method of the present invention.

FIG. 3 is a schematic cross-sectional view showing a step of forming a conventional polysilicon wiring.

[Explanation of symbols]

 11 Area for Forming Wiring Pattern 13 Polysilicon Layer 15 Resist Layer 17 Silicon Dioxide 19 Interlayer Insulating Film

Claims (1)

[Claims] 1. When forming a wiring pattern made of polysilicon on a semiconductor substrate, a step of depositing polysilicon on the semiconductor substrate on which a wiring pattern is to be formed, and a step of masking a portion corresponding to the wiring pattern, Insulating the silicon dioxide by injecting oxygen from above the mask and then annealing to form silicon dioxide, and uniformly injecting impurity ions into the entire region including the wiring pattern. A method for forming a polysilicon wiring, which comprises forming a wiring pattern made of polysilicon.