JPH07176611A - Preparation of wiring in semiconductor device - Google Patents
Preparation of wiring in semiconductor deviceInfo
- Publication number
- JPH07176611A JPH07176611A JP6220062A JP22006294A JPH07176611A JP H07176611 A JPH07176611 A JP H07176611A JP 6220062 A JP6220062 A JP 6220062A JP 22006294 A JP22006294 A JP 22006294A JP H07176611 A JPH07176611 A JP H07176611A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- semiconductor device
- manufacturing
- conductive material
- metal conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 62
- 229910052755 nonmetal Inorganic materials 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 29
- 239000004020 conductor Substances 0.000 claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 239000011810 insulating material Substances 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- -1 oxygen ions Chemical class 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 4
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 3
- 239000011261 inert gas Substances 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 10
- 239000012298 atmosphere Substances 0.000 claims 1
- 229910001873 dinitrogen Inorganic materials 0.000 claims 1
- 239000007789 gas Substances 0.000 claims 1
- 239000012299 nitrogen atmosphere Substances 0.000 claims 1
- 125000006850 spacer group Chemical group 0.000 abstract description 13
- 238000009413 insulation Methods 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002843 nonmetals Chemical class 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置の配線製造方
法に関し、特に高集積化された半導体装置に導電性スペ
ーサーの発生を防止して半導体装置の収率及び信頼性を
向上させることができる半導体装置の配線製造方法に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing wiring for a semiconductor device, and more particularly, it is possible to improve the yield and reliability of the semiconductor device by preventing the formation of conductive spacers in the highly integrated semiconductor device. The present invention relates to a wiring manufacturing method for a semiconductor device.
【０００２】[0002]
【従来の技術】一般的に半導体装置のゲート電極及び、
ワードラインは製造及びエッチングが容易なポリシリコ
ンで形成し、前記ポリシリコンを用いた配線は金属配線
より電気抵抗が大きいのでこれを減少させるためＮ型不
純物を注入して用いる。また最近には前記ポリシリコン
より抵抗の少ないマイクロクリスタルシリコンの使用が
研究されている。また、通常のＤＲＡＭ（Direct Rando
m Access Memory)装置の配線構造を考察してみる。2. Description of the Related Art Generally, a gate electrode of a semiconductor device and
The word line is formed of polysilicon which is easy to manufacture and etch, and the wiring using the polysilicon has an electric resistance higher than that of a metal wiring. Therefore, N-type impurities are implanted to reduce the electric resistance. Recently, the use of microcrystalline silicon, which has a lower resistance than that of polysilicon, has been studied. In addition, normal DRAM (Direct Rando
m Access Memory) Consider the wiring structure of the device.
【０００３】先ず、通常の素子分離のためフィールド酸
化膜とシリコンでなるゲート電極等が形成されている半
導体基板上に酸化膜でなる層間絶縁膜と、金属配線のビ
ットラインが一定間隔に配列されており、前記ビットラ
イン上に平坦化層及びポリシリコンよりなるワードライ
ンが順次形成されている。前記ビット線とワード線は相
互に直交するよう配列されている。First, an interlayer insulating film made of an oxide film and a bit line of metal wiring are arranged at regular intervals on a semiconductor substrate on which a field oxide film and a gate electrode made of silicon are formed for normal device isolation. The planarization layer and the word line made of polysilicon are sequentially formed on the bit line. The bit lines and word lines are arranged so as to be orthogonal to each other.
【０００４】前記のように、シリコンよりなるゲート及
びワードラインは平坦な膜の上部だけに形成されている
のではなく、ゲートの場合には素子分離領域であるフィ
ールド酸化膜やゲート酸化膜上部又はその境界面に形成
されたり、ワードラインの場合には段差が生じた層間絶
縁膜上に形成されるので、ポリシリコン層の段差被覆お
よび、エッチングの際の段差部分でのポリシリコン層の
完全な除去が半導体装置の特性に重要な影響を及ぼす。As described above, the gate and the word line made of silicon are not formed only on the flat film, but in the case of the gate, the field oxide film or the gate oxide film, which is an element isolation region, or Since it is formed on the boundary surface, or in the case of a word line, it is formed on the interlayer insulating film having a step, so that the step coverage of the polysilicon layer and the complete polysilicon layer at the step portion during etching are completed. The removal has a significant influence on the characteristics of the semiconductor device.
【０００５】図１Ａ及び図１Ｂは従来の半導体装置の配
線製造方法を段階別に説明する半導体装置の断面図で、
大きい段差を有する下部絶縁膜上に配線が形成される場
合を示す。図１Ａを参照すれば、半導体基板（図示され
ず）上に所定高さの段差を有するよう形成した下部絶縁
膜１２を有する半導体装置が示されている。前記下部絶
縁膜１２上にはポリシリコン層１４が均一な厚さを有す
るよう形成される。前記ポリシリコン１４の上部には前
記段差が生じた部分のシリコン層１４が露出するよう感
光膜パターン１６を形成する。1A and 1B are cross-sectional views of a semiconductor device for explaining a conventional method for manufacturing a wiring of a semiconductor device step by step.
A case where wiring is formed on a lower insulating film having a large step is shown. Referring to FIG. 1A, there is shown a semiconductor device having a lower insulating film 12 formed on a semiconductor substrate (not shown) so as to have a step having a predetermined height. A polysilicon layer 14 is formed on the lower insulating layer 12 to have a uniform thickness. A photoresist pattern 16 is formed on the polysilicon 14 to expose the silicon layer 14 in the step portion.
【０００６】前記感光膜パターン１６により露出してい
る前記ポリシリコン層１４は異方性乾式エッチング方法
により除去され、図１Ｂに示したようにポリシリコンよ
りなる配線パターンを形成する。The polysilicon layer 14 exposed by the photosensitive film pattern 16 is removed by an anisotropic dry etching method to form a wiring pattern made of polysilicon as shown in FIG. 1B.
【０００７】しかし、前記ポリシリコン層１４を分離さ
せるため用いた前記異方性エッチング方法は、その特性
上前記下部絶縁膜１２の段差面部（Profile)にポリシリ
コンスペーサー１８を残存させる。前記ポリシリコンス
ペーサー１８の残存防止のため、前記異方性乾式エッチ
ング方法の代わりに等方性湿式エッチング方法を用いる
ことができる。しかし、前記等方性湿式エッチング方法
はエッチングの際に臨界の大きさ（Critical Dimensio
n) が著しく変化することにより高集積半導体装置、例
えば６４Ｍ以上のＤＲＡＭには用いられない問題点を有
している。これとは別に、前記異方性乾式エッチング方
法は、エッチングによる臨界の大きさを変化させず感光
膜パターン１６と同一なパターンが形成できることによ
り、６４Ｍ以上のＤＲＡＭのような高集積半導体装置の
製作工程に用いられる。このような理由で、従来の半導
体装置の配線形成方法は、前記非等方性乾式エッチング
方法を用いることによりポリシリコンスペーサー１８の
生成を完全に防止することが難しいというのが実情であ
る。However, the anisotropic etching method used to separate the polysilicon layer 14 causes the polysilicon spacer 18 to remain on the step surface portion (Profile) of the lower insulating film 12 due to its characteristics. In order to prevent the polysilicon spacer 18 from remaining, an isotropic wet etching method can be used instead of the anisotropic dry etching method. However, the isotropic wet etching method has a critical size (Critical Dimensio
Since n) changes remarkably, it has a problem that it cannot be used in a highly integrated semiconductor device, for example, a DRAM of 64M or more. Separately, the anisotropic dry etching method can form a highly integrated semiconductor device such as a DRAM of 64M or more by forming the same pattern as the photosensitive film pattern 16 without changing the critical size due to etching. Used in the process. For this reason, it is difficult to completely prevent the polysilicon spacer 18 from being generated by the conventional method for forming a wiring of a semiconductor device by using the anisotropic dry etching method.
【０００８】[0008]
【発明が解決しようとする課題】前記のように、異方性
乾式エッチング方法を用いて配線パターンを形成するこ
とにより段差面部にポリシリコンスペーサーが生成し、
持続的な高集積化に伴う配線間の間隔が減少することに
より、半導体装置は配線間の短絡が頻繁に発生する問題
点を有するようになる。As described above, by forming a wiring pattern using the anisotropic dry etching method, a polysilicon spacer is formed on the step surface portion,
The semiconductor device has a problem in that a short circuit between wirings frequently occurs due to a reduction in a distance between wirings due to continuous high integration.
【０００９】また、前記ポリシリコンスペーサーは半導
体装置の高集積化に伴い、ますます大きくなる段差によ
り漸次大きく形成される。前記ポリシリコンスペーサー
が大きくなるに伴い、半導体装置は頻繁な配線間の短絡
により不良率が大きく増加する問題点を有するようにな
る。Further, the polysilicon spacer is gradually formed to have a larger step due to the higher integration of the semiconductor device. As the size of the polysilicon spacer becomes large, the semiconductor device has a problem that the defective rate increases greatly due to frequent short circuits between wirings.
【００１０】従って、本発明の目的は高集積化した半導
体装置において導電性スペーサーの発生を防止し、半導
体装置の収率及び信頼性を向上させることができる半導
体装置の配線製造方法を提供することにある。Therefore, an object of the present invention is to provide a method for manufacturing a wiring of a semiconductor device, which can prevent the generation of conductive spacers in a highly integrated semiconductor device and improve the yield and reliability of the semiconductor device. It is in.
【００１１】[0011]
【課題を解決するための手段】前記のような目的の達成
のため、本発明の半導体装置の配線製造方法は半導体基
板上に形成した下部絶縁膜の表面に非金属導電物質層を
形成する工程と、前記非金属導電物質層を部分的に絶縁
特性を有する絶縁物質に変化させ配線パターンを形成す
る工程とを含む。In order to achieve the above-mentioned object, a method of manufacturing a wiring of a semiconductor device according to the present invention comprises a step of forming a non-metal conductive material layer on the surface of a lower insulating film formed on a semiconductor substrate. And a step of partially changing the non-metallic conductive material layer to an insulating material having insulating properties to form a wiring pattern.
【００１２】[0012]
【作用】前記構成により、本発明による半導体装置の配
線製造方法は、下部絶縁膜の段差部分に形成された非金
属導電物質層を絶縁物質に変化させることにより、導電
性スペーサーの生成を防止することができる利点を提供
する。また本発明による半導体装置の配線製造方法は、
導電性スペーサーによる配線間の短絡現象を防止して半
導体装置の収率を向上させることができ、半導体装置の
信頼性を向上させることができる利点を提供する。With the above structure, the method for manufacturing a wiring of a semiconductor device according to the present invention prevents the formation of conductive spacers by changing the non-metal conductive material layer formed in the step portion of the lower insulating film into an insulating material. Provide the benefits that can be. Further, the method for manufacturing a wiring of a semiconductor device according to the present invention,
It is possible to prevent a short circuit phenomenon between wirings due to the conductive spacers, improve the yield of the semiconductor device, and provide the advantage of improving the reliability of the semiconductor device.
【００１３】[0013]
【実施例】図２Ａ及び図２Ｂは、本発明の実施例による
半導体装置の配線製造方法を段階別に説明するための半
導体装置の断面図である。図２Ａを参照すれば、所定高
さの段差を有するよう形成した下部絶縁膜２２を備えた
半導体装置が示されている。前記下部絶縁膜２２は絶縁
特性を有する酸化膜、窒化膜又はＢＰＳＧ（boro phosp
ho silicate glass)等により形成される。また前記下部
絶縁膜２２の下部には図示されていないが所定構造物、
即ちＭＯＳ電界効果トランジスタ構造のゲート、ソー
ス、ドレイン、及びビットライン等が形成されている半
導体基板が存在することになる。2A and 2B are sectional views of a semiconductor device for explaining step by step a method of manufacturing a wiring of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 2A, there is shown a semiconductor device including a lower insulating film 22 formed to have a step having a predetermined height. The lower insulating layer 22 may be an oxide layer, a nitride layer, or BPSG (boro phosp) having insulating properties.
ho silicate glass) or the like. Although not shown in the figure below the lower insulating film 22, a predetermined structure,
That is, there exists a semiconductor substrate on which a gate, a source, a drain, a bit line and the like of the MOS field effect transistor structure are formed.
【００１４】前記下部絶縁膜２２の全表面には、ポリシ
リコン又はマイクロクリスタルシリコンよりなる非金属
導電物質層２４を化学気相蒸着（chemical vapor depos
ition)方法により浸漬する。また前記非金属導電物質層
２４の上部には配線パターン用感光膜パターン２６を形
成する。前記感光膜パターン２６は前記下部絶縁層２２
の段差部分に形成された前記非金属導電物質層２４を露
出させ、また前記非金属導電物質層２４のうち、配線に
用いられる領域以外の領域に位置する前記非金属導電物
質層２４を露出させる。また前記感光膜パターン２６に
より露出した非金属導電物質層２４に酸素イオンを注入
する。この際、前記感光膜パターン２６により露出した
前記非金属導電物質２４には、前記露出した非金属導電
物質層２４すべてを酸化させるのに十分な量の酸素が注
入されるようにする。また前記酸素イオンは前記段差部
分に形成された前記非金属導電物質層２４を始めに全て
の露出した非金属導電物質層２４に均等に注入されるよ
うにする。A non-metal conductive material layer 24 made of polysilicon or microcrystalline silicon is formed on the entire surface of the lower insulating layer 22 by chemical vapor deposition.
ition) method. A photosensitive film pattern 26 for a wiring pattern is formed on the non-metal conductive material layer 24. The photoresist pattern 26 is formed on the lower insulating layer 22.
Exposing the non-metal conductive material layer 24 formed on the stepped portion of the non-metal conductive material layer 24, and exposing the non-metal conductive material layer 24 located in a region other than the region used for wiring in the non-metal conductive material layer 24. . Also, oxygen ions are implanted into the non-metal conductive material layer 24 exposed by the photosensitive film pattern 26. At this time, a sufficient amount of oxygen is injected into the non-metal conductive material 24 exposed by the photosensitive film pattern 26 to oxidize the entire exposed non-metal conductive material layer 24. Further, the oxygen ions are evenly injected into all exposed non-metal conductive material layers 24 starting from the non-metal conductive material layer 24 formed in the step portion.
【００１５】また前記感光膜パターン２６は前記酸素イ
オンの注入工程の後、図２Ｂに示したように除去され
る。また前記酸素イオンが注入された非金属導電物質層
２４は、アルゴン又は窒素等のような不活性気体を含む
熱拡散炉や高速熱処理装置により熱処理され、絶縁特性
を有する酸化膜３０に変化する。前記酸化膜３０は半導
体装置の構造物に用いられたり、又は後続工程を進める
ため下部絶縁膜２２が露出するよう除去される。After the oxygen ion implantation process, the photoresist pattern 26 is removed as shown in FIG. 2B. Further, the non-metal conductive material layer 24 into which the oxygen ions are implanted is heat-treated by a thermal diffusion furnace or a rapid thermal processing apparatus containing an inert gas such as argon or nitrogen to change into an oxide film 30 having insulating properties. The oxide layer 30 may be used for a structure of a semiconductor device or may be removed to expose the lower insulating layer 22 for performing a subsequent process.
【００１６】[0016]
【発明の効果】上述の如く、本発明による半導体装置の
配線製造方法は、下部絶縁膜の段差部分に形成された非
金属導電物質層を絶縁物質に変化させることにより、導
電性スペーサーの生成を防止することができる利点を提
供する。前記利点により、本発明による半導体装置の配
線製造方法は導電性スペーサーによる配線間の短絡現象
を防止して半導体装置の収率を向上させることができる
と共に、半導体装置の信頼性を向上させることができる
利点を提供する。As described above, in the method for manufacturing a wiring of a semiconductor device according to the present invention, the conductive spacer is generated by changing the non-metal conductive material layer formed in the stepped portion of the lower insulating film into an insulating material. It provides advantages that can be prevented. Due to the above advantages, the method for manufacturing a wiring of a semiconductor device according to the present invention can prevent a short circuit between wirings due to a conductive spacer, improve the yield of the semiconductor device, and improve the reliability of the semiconductor device. Provide the benefits that you can.
【図１】図１Ａは、従来の半導体装置のシリコン配線製
造方法を段階別に説明するための半導体装置の断面図で
ある。図１Ｂは、従来の半導体装置のシリコン配線製造
方法を段階別に説明するための半導体装置の断面図であ
る。FIG. 1A is a cross-sectional view of a semiconductor device for explaining a conventional method of manufacturing a silicon wiring of a semiconductor device step by step. FIG. 1B is a cross-sectional view of a semiconductor device for explaining a conventional method for manufacturing a silicon wiring of a semiconductor device step by step.
【図２】図２Ａは、本発明による半導体装置のシリコン
配線製造方法を段階別に説明するための半導体装置の断
面図である。図２Ｂは、本発明による半導体装置のシリ
コン配線製造方法を段階別に説明するための半導体装置
の断面図である。FIG. 2A is a cross-sectional view of a semiconductor device for explaining a method of manufacturing a silicon wiring of a semiconductor device according to the present invention step by step. FIG. 2B is a cross-sectional view of a semiconductor device for explaining a method of manufacturing a silicon wiring of a semiconductor device according to the present invention in stages.
22 下部絶縁膜 24 非金属導電物質層 26 感光膜パターン 30 酸化膜 22 Lower insulating film 24 Non-metal conductive material layer 26 Photosensitive film pattern 30 Oxide film
Claims (14)
面に非金属導電物質層を形成する工程と、 前記非金属導電物質層を部分的に絶縁特性を有する絶縁
物質に変化させ、配線パターンを形成する工程とを含む
ことを特徴とする半導体装置の配線製造方法。1. A step of forming a non-metal conductive material layer on a surface of a lower insulating film formed on a semiconductor substrate, the non-metal conductive material layer being partially changed to an insulating material having insulating properties, and a wiring pattern. And a step of forming a wiring, the method for manufacturing a wiring of a semiconductor device.
形成されたことを特徴とする請求項１記載の半導体装置
の配線製造方法。2. The method of manufacturing a wiring of a semiconductor device according to claim 1, wherein the non-metal conductive material layer is formed of polysilicon.
ポリシリコン層に配線パターン用感光膜パターンを形成
する工程と、 前記感光膜パターンにより露出した前記ポリシリコン層
に酸素イオンを注入する工程と、 前記感光膜パターンを除去する工程と、 前記酸素イオンが注入された前記ポリシリコン層の部分
が絶縁物質に変化するよう、前記ポリシリコン層を熱処
理する工程とを備えたことを特徴とする請求項２記載の
半導体装置の配線製造方法。3. The step of changing to the insulating material comprises the steps of forming a photosensitive film pattern for a wiring pattern on the polysilicon layer, and implanting oxygen ions into the polysilicon layer exposed by the photosensitive film pattern. And removing the photoresist pattern, and heat treating the polysilicon layer so that the portion of the polysilicon layer into which the oxygen ions are implanted is changed to an insulating material. Item 3. A method for manufacturing a wiring of a semiconductor device according to item 2.
処理装置で行うことを特徴とする請求項３記載の半導体
装置の配線製造方法。4. The method for manufacturing a wiring of a semiconductor device according to claim 3, wherein the heat treatment step is performed by a heat treatment apparatus containing an inert gas.
ことを特徴とする請求項４記載の半導体装置の配線製造
方法。5. The wiring manufacturing method for a semiconductor device according to claim 4, wherein the inert gas is argon gas.
理装置で行われることを特徴とする請求項３記載の半導
体製造の配線製造方法。6. The wiring manufacturing method according to claim 3, wherein the heat treatment step is performed by a heat treatment apparatus containing nitrogen gas.
スタルシリコンで形成されたことを特徴とする請求項１
記載の半導体装置の配線製造方法。7. The non-metallic conductive material layer is formed of microcrystalline silicon.
A method for manufacturing a wiring of a semiconductor device as described above.
れた下部絶縁膜の表面に非金属導電物質を形成する工程
と、 前記非金属導電物質層の上部に配線用感光膜パターンを
形成し、前記下部絶縁膜の段差部分に形成された前記非
金属導電物質層を含む非配線パターン領域を露出させる
工程と、 前記感光膜パターンにより露出した前記非金属導電物質
層に酸素イオンを注入する工程と、 前記感光膜パターンを除去する工程と、 前記酸素イオンが注入された前記非金属導電物質層の部
分が、絶縁物質パターンに変化するよう、前記非金属導
電物質層を熱処理する工程を備えたことを特徴とする半
導体装置の配線製造方法。8. A step of forming a non-metal conductive material on a surface of a lower insulating film formed to have a step on a semiconductor substrate, and forming a wiring photosensitive film pattern on the non-metal conductive material layer, Exposing a non-wiring pattern region including the non-metal conductive material layer formed in a step portion of the lower insulating film; and implanting oxygen ions into the non-metal conductive material layer exposed by the photosensitive film pattern. A heat treatment of the non-metal conductive material layer so that the portion of the non-metal conductive material layer into which the oxygen ions are implanted changes into an insulating material pattern. A method for manufacturing a wiring of a semiconductor device, comprising:
スタルシリコンで形成されたことを特徴とする請求項８
記載の半導体装置の配線製造方法。9. The non-metal conductive material layer is formed of microcrystalline silicon.
A method for manufacturing a wiring of a semiconductor device as described above.
行することを特徴とする請求項８記載の半導体装置の配
線製造方法。10. The method for manufacturing a wiring of a semiconductor device according to claim 8, wherein the heat treatment step proceeds in an inert atmosphere.
用いることを特徴とする請求項８記載の半導体装置の配
線製造方法。11. The method of manufacturing a wiring of a semiconductor device according to claim 8, wherein the heat treatment step uses a high-speed heat treatment apparatus.
ることを特徴とする請求項８記載の半導体装置の配線製
造方法。12. The method of manufacturing a wiring of a semiconductor device according to claim 8, wherein the insulating material pattern is an oxide film.
絶縁物質パターンを除去する工程を追加して備えること
を特徴とする請求項８記載の半導体装置の配線製造方
法。13. The method of manufacturing a wiring of a semiconductor device according to claim 8, further comprising a step of removing the insulating material pattern generated by the heat treatment step.
れることを特徴とする請求項８記載の半導体装置の配線
製造方法。14. The method of manufacturing a wiring of a semiconductor device according to claim 8, wherein the heat treatment step is performed in a nitrogen atmosphere.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR93018502A KR960016237B1 (en) | 1993-09-15 | 1993-09-15 | Semiconductor device silicon wire manufacturing method |
| KR93-18502 | 1993-09-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07176611A true JPH07176611A (en) | 1995-07-14 |
Family
ID=19363542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6220062A Pending JPH07176611A (en) | 1993-09-15 | 1994-09-14 | Preparation of wiring in semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH07176611A (en) |
| KR (1) | KR960016237B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62181475A (en) * | 1986-02-04 | 1987-08-08 | Mitsubishi Electric Corp | Forming method for electrode |
| JPS63177453A (en) * | 1987-01-16 | 1988-07-21 | Sony Corp | Semiconductor device |
| JPS6468948A (en) * | 1987-09-09 | 1989-03-15 | Nec Corp | Manufacture of semiconductor device |
| JPH05102145A (en) * | 1991-10-04 | 1993-04-23 | Kawasaki Steel Corp | Method for forming polysilicon wiring |
-
1993
- 1993-09-15 KR KR93018502A patent/KR960016237B1/en not_active IP Right Cessation
-
1994
- 1994-09-14 JP JP6220062A patent/JPH07176611A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62181475A (en) * | 1986-02-04 | 1987-08-08 | Mitsubishi Electric Corp | Forming method for electrode |
| JPS63177453A (en) * | 1987-01-16 | 1988-07-21 | Sony Corp | Semiconductor device |
| JPS6468948A (en) * | 1987-09-09 | 1989-03-15 | Nec Corp | Manufacture of semiconductor device |
| JPH05102145A (en) * | 1991-10-04 | 1993-04-23 | Kawasaki Steel Corp | Method for forming polysilicon wiring |
Also Published As
| Publication number | Publication date |
|---|---|
| KR960016237B1 (en) | 1996-12-07 |
| KR950009935A (en) | 1995-04-26 |
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