JPS63177453A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS63177453A JPS63177453A JP776987A JP776987A JPS63177453A JP S63177453 A JPS63177453 A JP S63177453A JP 776987 A JP776987 A JP 776987A JP 776987 A JP776987 A JP 776987A JP S63177453 A JPS63177453 A JP S63177453A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- capacitor
- polycrystalline
- wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims abstract description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 239000002245 particle Substances 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、キャパシタと配線とを有し前記キャパシタの
少なくとも一方の電極と前記配線とが半導体層によって
形成されている半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device that includes a capacitor and a wiring, and in which at least one electrode of the capacitor and the wiring are formed of a semiconductor layer. .
本発明は、上記の様な半導体装置において、半導体層の
うちの電極の部分における粒径を配線の部分における粒
径よりも小さくすることによって、高い性能を有するこ
とができる様にしたものである。The present invention is a semiconductor device as described above, in which the grain size in the electrode portion of the semiconductor layer is made smaller than the grain size in the wiring portion, thereby making it possible to have high performance. .
キャパシタを内蔵しているアナログＭＯ３−ＩＣ等が高
い性能を有するためには、そのキャパシタが高いキャパ
シタンス精度を有している必要がある。In order for an analog MO3-IC or the like having a built-in capacitor to have high performance, the capacitor must have high capacitance accuracy.
ところでこの様なアナログＭＯ９−ＩＣにおいては、Ｐ
等の不純物を含有する多結晶Ｓｉ層によってキャパシタ
の電極や配線等が形成され、ＳｉＯ□層によって誘電体
が形成されていることが多い。多結晶Ｓｉ層にＰ等の不
純物を含有させることは、多結晶Ｓｉ層を覆うＰＳＧ等
からの熱拡散によって行われている。By the way, in such an analog MO9-IC, P
In many cases, a polycrystalline Si layer containing such impurities is used to form capacitor electrodes, wiring, etc., and a SiO□ layer forms a dielectric. Impurities such as P are contained in the polycrystalline Si layer by thermal diffusion from PSG or the like covering the polycrystalline Si layer.
一方、アナログＭＯ３−ＩＣの時定数（ＣｘＲ）をでき
る限り小さくするために、不純物濃度をできる限り高く
し、且つこの状態で熱処理を行っている。不純物濃度が
高い状態で熱処理を行えば、多結晶ＳｉＮにおける粒径
が大きくなって、抵抗値が低下するためである。On the other hand, in order to make the time constant (CxR) of the analog MO3-IC as small as possible, the impurity concentration is made as high as possible, and heat treatment is performed in this state. This is because if heat treatment is performed in a state where the impurity concentration is high, the grain size in polycrystalline SiN increases and the resistance value decreases.
ところで従来のアナログＭＯ３−ＩＣにおいては、上述
の様に熱拡散によって多結晶Ｓｉ層に不純物を含有させ
ている。このために、多結晶Ｓｉ層のうちのキャパシタ
電極の部分においても配線の部分においても、共に不純
物濃度が高い。従って、電極の部分においても配線の部
分においても、共に粒径が大きい。By the way, in the conventional analog MO3-IC, impurities are contained in the polycrystalline Si layer by thermal diffusion as described above. For this reason, the impurity concentration is high in both the capacitor electrode portion and the wiring portion of the polycrystalline Si layer. Therefore, the grain size is large in both the electrode portion and the wiring portion.
しかし、多結晶Ｓｉ層における粒径が大きいということ
は、微視的に見れば、多結晶Ｓｉ層の表面の凹凸が大き
いということである。そして、キャパシタ電極のうちの
誘電体との界面の凹凸が大きいと、キャパシタのキャパ
シタンスのバラツキが大きい。However, the fact that the grain size in the polycrystalline Si layer is large means that the surface irregularities of the polycrystalline Si layer are large when viewed microscopically. If the interface between the capacitor electrode and the dielectric material has large irregularities, the capacitance of the capacitor will vary greatly.
このことは、キャパシタの誘電体となっているＳｉＯ□
層を熱酸化で形成した場合も、ＣＶＤで形成した場合も
同様である。This means that SiO□, which is the dielectric material of the capacitor,
The same applies whether the layer is formed by thermal oxidation or CVD.
従って、上述の様な従来のアナログＭＯ３−ＩＣは、キ
ャパシタのキャパシタンス精度が低く、性能が低い。そ
してこの様なことは、アナログＭＯＳ−ＩＣに限らず、
キャパシタ及び配線を有する一般の半導体装置について
も同様である。Therefore, the conventional analog MO3-IC as described above has low capacitance accuracy and low performance. And this kind of thing is not limited to analog MOS-IC.
The same applies to general semiconductor devices having capacitors and wiring.
本発明による半導体装置は、半導体層１５のうちのキャ
パシタ１１の電極１３の部分における粒径が配線１８．
１９の部分における粒径よりも小さいことを特徴として
いる。In the semiconductor device according to the present invention, the grain size in the portion of the electrode 13 of the capacitor 11 in the semiconductor layer 15 is 18.
It is characterized by being smaller than the particle size in the part No. 19.
本発明による半導体装置では、半導体層１５のうちのキ
ャパシタ電極１３の部分における粒径が、相対的に小さ
い。このために、微視的に見れば、キャパシタ電極１３
のうちの誘電体１６との界面の凹凸が小さく、キャパシ
タ１１のキャパシタンス精度が高い。In the semiconductor device according to the present invention, the grain size in the capacitor electrode 13 portion of the semiconductor layer 15 is relatively small. For this reason, microscopically, the capacitor electrode 13
The unevenness of the interface with the dielectric 16 is small, and the capacitance accuracy of the capacitor 11 is high.
また、半導体１１５のうちの配線１８．１９の部分にお
ける粒径は、相対的に大きい。このために、配線１８．
１９の抵抗値が低く、半導体装置としての時定数が小さ
い。Further, the grain size in the wiring 18 and 19 portion of the semiconductor 115 is relatively large. For this purpose, wiring 18.
The resistance value of 19 is low, and the time constant as a semiconductor device is small.
以下、アナログＭＯ３−ＩＣに適用した本発明の一実施
例を、第１図及び第２図を参照しながら説明する。An embodiment of the present invention applied to an analog MO3-IC will be described below with reference to FIGS. 1 and 2.
本実施例は、第１図に示されている様に、キャパシタ１
１とＭＯＳトランジスタ１２とを有している。キャパシ
タ１１の一方の電極１３及び他方の電極１４は、夫々多
結晶Ｓｉ層１５及びＡＩＪｉによって形成されており、
第１の誘電体１６及び第２の誘電体１７は、夫々５ｔｏ
ｚＪｉｉ及び５ｉＪ４層によって形成されている。In this embodiment, as shown in FIG.
1 and a MOS transistor 12. One electrode 13 and the other electrode 14 of the capacitor 11 are formed of a polycrystalline Si layer 15 and AIJi, respectively.
The first dielectric 16 and the second dielectric 17 each have 5 to
It is formed by zJii and 5iJ4 layers.
また、電極１３に連なっている配線１８及びＭＯＳトラ
ンジスタ１２のゲート電極１９も、多結晶Ｓｔ層１５に
よって形成されている。Further, the wiring 18 connected to the electrode 13 and the gate electrode 19 of the MOS transistor 12 are also formed of the polycrystalline St layer 15.
そして本実施例では、多結晶５ｉＪｉｉ１５のうちで配
線１８とゲート電極１９との部分における粒径が相対的
に大きくて、これらの配線１８とゲート電極１９との抵
抗値が低い。一方、電極１３の部分における粒径が相対
的に小さくて、電極１３の誘電体１５との界面の凹凸が
小さい。In this embodiment, the grain size of the polycrystal 5iJii 15 at the portion where the wiring 18 and the gate electrode 19 are located is relatively large, and the resistance value between the wiring 18 and the gate electrode 19 is low. On the other hand, the grain size in the electrode 13 portion is relatively small, and the unevenness of the interface between the electrode 13 and the dielectric 15 is small.
この様な電極１３、配線１８及びゲート電極１９を形成
するには、第２図に示す様に、Ｓｉ基板２１の表面の５
ｉＯｚ層２２上に、不純物を含有していない多結晶Ｓｉ
層１５をまず形成する。In order to form such an electrode 13, wiring 18 and gate electrode 19, as shown in FIG.
Polycrystalline Si containing no impurities is formed on the iOz layer 22.
Layer 15 is first formed.
次に、多結晶Ｓｔ層１５のうちで電極１３を形成すべき
部分のみをマスク２３で覆い、この状態で多結晶Ｓｉ層
１５中へＰイオン２４を注入する。Next, only the portion of the polycrystalline St layer 15 where the electrode 13 is to be formed is covered with a mask 23, and in this state, P ions 24 are implanted into the polycrystalline Si layer 15.
この様にすることによって、多結晶Ｓｉ層１５のうちで
電極１３を形成すべき部分に、１０１９原子／ｃｃ以下
と比較的低濃度のＰイオン２４を注入する。またその他
の部分には、１０２０原子／ｃｃ以上と比較的高濃度の
Ｐイオン２４を注入する。By doing so, P ions 24 at a relatively low concentration of 10<19> atoms/cc or less are implanted into the portion of the polycrystalline Si layer 15 where the electrode 13 is to be formed. In other parts, P ions 24 are implanted at a relatively high concentration of 1020 atoms/cc or more.
そして、この状態で熱処理を行う。すると、多結晶Ｓｉ
層１５のうちで電極１３を形成すべき部分では、比較的
低濃度のＰイオン２４しか含有されていないために、粒
径が相対的に小さい。Then, heat treatment is performed in this state. Then, polycrystalline Si
The portion of the layer 15 where the electrode 13 is to be formed contains only a relatively low concentration of P ions 24, so the particle size is relatively small.
これに対して、多結晶Ｓｉ層１５のうちで電極１３を形
成すべき部分以外の部分では、比較的高濃度のＰイオン
２４が含有されているために、粒径が相対的に大きくな
る。On the other hand, the portions of the polycrystalline Si layer 15 other than the portions where the electrodes 13 are to be formed contain P ions 24 at a relatively high concentration, so that the grain size becomes relatively large.
従って、その後に多結晶Ｓｉ層１５をパターニングすれ
ば、上述の様な電極１３、配線１８及びゲート電極１９
が得られる。Therefore, if the polycrystalline Si layer 15 is patterned after that, the electrode 13, wiring 18 and gate electrode 19 as described above can be formed.
is obtained.
本実施例では、上述の様に電極１３の誘電体１５との界
面の凹凸が小さいために、キャパシタ１１のキャパシタ
ンスのバラツキが小さいが、電極１３中のＰイオン２４
の濃度が１０１９原子／ｃｃ以下でありキャパシタ１１
のキャパシタンスの電圧依存性を無視することができる
ので、このことによってもキャパシタ１１のキャパシタ
ンスのバラツキが小さい。In this embodiment, since the unevenness of the interface between the electrode 13 and the dielectric 15 is small as described above, the variation in the capacitance of the capacitor 11 is small.
The concentration of capacitor 11 is less than or equal to 1019 atoms/cc.
Since the voltage dependence of the capacitance of the capacitor 11 can be ignored, this also reduces the variation in the capacitance of the capacitor 11.
なお、以上の本実施例では電極１３、配線１８及びゲー
ト電極１９が多結晶Ｓｔ層１５によって形成されている
が、これらが多結晶ＳｉＮ以外の半導体層によって形成
されていてもよい。In this embodiment, the electrode 13, wiring 18, and gate electrode 19 are formed of the polycrystalline St layer 15, but these may be formed of a semiconductor layer other than polycrystalline SiN.
また、上述の本実施例は本発明をアナログＭＯ３−ＩＣ
に適用したものであるが、アナログＭＯ３−ＩＣ以外の
半導体装置にも勿論本発明を適用することができる。In addition, the present embodiment described above also applies the present invention to an analog MO3-IC.
However, the present invention can of course be applied to semiconductor devices other than analog MO3-ICs.
本発明による半導体装置では、半導体装置としての時定
数が小さいにも拘らずキャパシタのキャパシタンス精度
が高いので、半導体装置が高い性能を有している。In the semiconductor device according to the present invention, the capacitance accuracy of the capacitor is high despite the small time constant of the semiconductor device, so the semiconductor device has high performance.
第１図は本発明の一実施例の側断面図、第２図は一実施
例の一つの製造工程を示す側断面図である。
なお図面に用いた符号において、
１１・−−−−−一−−−・−一−−−−−−−−キャ
パシタ１３−−−−−−−−−−・−−−−−−−一・
電極１５−−−−−−−−−−・−・・−・・多結晶Ｓ
ｉ層１６−−−−−−−−−−・−−−−−−ｍ−誘電
体１８・−−一−−−−−−−−−・・−配線１９・−
・・・・−・・−−−−−−ゲート電極である。FIG. 1 is a side sectional view of an embodiment of the present invention, and FIG. 2 is a side sectional view showing one manufacturing process of the embodiment. In addition, in the symbols used in the drawings, 11. one·
Electrode 15--------------Polycrystalline S
i-layer 16----------------------Dielectric 18------------ Wiring 19--
...---------Gate electrode.
Claims (1)
一方の電極と前記配線とが半導体層によって形成されて
いる半導体装置において、 前記半導体層のうちの前記電極の部分における粒径が前
記配線の部分における粒径よりも小さいことを特徴とす
る半導体装置。[Scope of Claims] A semiconductor device including a capacitor and a wiring, wherein at least one electrode of the capacitor and the wiring are formed of a semiconductor layer, wherein a grain size in the electrode portion of the semiconductor layer is A semiconductor device characterized in that the grain size is smaller than that in the wiring portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP776987A JPS63177453A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP776987A JPS63177453A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63177453A true JPS63177453A (en) | 1988-07-21 |
Family
ID=11674886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP776987A Pending JPS63177453A (en) | 1987-01-16 | 1987-01-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63177453A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07176611A (en) * | 1993-09-15 | 1995-07-14 | Hyundai Electron Ind Co Ltd | Preparation of wiring in semiconductor device |
| KR100233557B1 (en) * | 1996-06-29 | 1999-12-01 | 김영환 | Polyresistor of semiconductor device and its fabrication method for analog |
| JP2007096082A (en) * | 2005-09-29 | 2007-04-12 | Asahi Kasei Microsystems Kk | Semiconductor device and its manufacturing method |
-
1987
- 1987-01-16 JP JP776987A patent/JPS63177453A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07176611A (en) * | 1993-09-15 | 1995-07-14 | Hyundai Electron Ind Co Ltd | Preparation of wiring in semiconductor device |
| KR100233557B1 (en) * | 1996-06-29 | 1999-12-01 | 김영환 | Polyresistor of semiconductor device and its fabrication method for analog |
| JP2007096082A (en) * | 2005-09-29 | 2007-04-12 | Asahi Kasei Microsystems Kk | Semiconductor device and its manufacturing method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0736437B2 (en) | Method of manufacturing semiconductor memory | |
| JPS62154778A (en) | Monolithic integrated circuit and manufacture of the same | |
| JPH0577340B2 (en) | ||
| KR950004608A (en) | Programmable Anti-Fuse Element and Manufacturing Method Thereof | |
| JP2795259B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPS63177453A (en) | Semiconductor device | |
| JPS5989450A (en) | Semiconductor integrated circuit device | |
| JPH05243519A (en) | Semiconductor memory device | |
| JPS63108763A (en) | Semiconductor integrated circuit | |
| JPS6074665A (en) | Semiconductor device | |
| JPS61170057A (en) | Vertical type capacitor | |
| JPH0142147B2 (en) | ||
| JP2526536Y2 (en) | Semiconductor device | |
| JPH05235275A (en) | Integrated circuit device | |
| JP2001223334A (en) | Method for manufacturing semiconductor device and semiconductor device | |
| JPS63177454A (en) | Manufacture of semiconductor device | |
| JPS6085555A (en) | Manufacture of semiconductor device | |
| JPS62130552A (en) | Semiconductor integrated circuit device | |
| JP2532471B2 (en) | Semiconductor device | |
| KR100778878B1 (en) | Method for Forming Passive Elements in Semiconductor Device | |
| JPS61225852A (en) | Semiconductor device | |
| JPH07249742A (en) | Semiconductor device | |
| JPS6062151A (en) | Mos type semiconductor integrated circuit device and manufacture thereof | |
| JPS61255050A (en) | Semiconductor integrated circuit device | |
| JP2002158331A (en) | Semiconductor capacitive element and semiconductor integrated circuit comprising it |