JPS63108763A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To manufacture a MIS type capacitor for an LSI having large electrostatic capacitance per unit area by forming a semiconductor integrated circuit in two layer constitution of parallel connection. CONSTITUTION:A first capacitor is formed of an N<+> type semiconductor layer 2 in an N-type semiconductor substrate 1, a first insulating film 3 of silicon oxide deposited on the layer 2, and a first metallic film 4 of Al, and a second capacitor is formed of the film 4, a second insulating film 5 of silicon oxide deposited on the film 4, and a third metallic film 6 of Al, etc. The film 6 and the layer 2 are connected by a through-hole 7, the second metallic film 8, etc., and consequently these two-layered capacitors are connected in parallel. This two-layer structure and parallel connection allow an LSI MIS capacitor to have an increased capacitance per unit area.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit equipped with an MIS type capacitor having a large capacitance per unit area.

[Conventional technology]

Conventionally, capacitors formed on semiconductor substrates, especially MIS
type capacitors use a part of a - conductivity type semiconductor layer formed on a semiconductor substrate as an electrode, an insulating film is further formed on the above-mentioned one conductivity type semiconductor layer, and a metal film used as a wiring layer is formed on top of the insulating film. The structure used the electrode as the electrode.

[Problem that the invention seeks to solve]

However, with only the conventional structure described above, the capacitance per unit area is small, and when a semiconductor integrated circuit including a capacitor is manufactured, the capacitor occupies a large proportion of the semiconductor integrated circuit.

An object of the present invention is to provide a semiconductor integrated circuit equipped with an MIS type capacitor having a larger capacitance per unit area than the conventional one.

[Means for solving problems]

The semiconductor integrated circuit of the present invention includes a selectively formed first conductivity type semiconductor layer with a high impurity concentration, a first metal film formed on top of the first conductivity type semiconductor layer with a first insulating film interposed therebetween, and the first conductivity type semiconductor layer. a second metal film electrically connected to the layer and a third metal film provided on the first metal film via an insulating film;
Furthermore, it is configured to include an MIS type capacitor having means for electrically connecting the third metal film and the second metal film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of the main parts of a semiconductor chip showing an embodiment of the present invention.

An N+ type sensitive conductor layer 2 with a high impurity concentration is formed in an N type semiconductor substrate 1, and is used as a first electrode. The first metal film 4 consisting of the following is used as a second electrode. Furthermore, the first
A second insulating film 5 made of silicon oxide is formed on the metal film 4 of
form.

On top of that, Aj? used in the second wiring layer? The third consisting of
A metal film 6 is formed to serve as a third electrode. The third metal film 6, the N+ type sensitive conductor layer 2 with high impurity concentration in the N type semiconductor substrate l which is the first electrode, the through hole 7 provided in the second insulating film 5, and the N'' type semiconductor Electrical connection is made by the second metal film 8 that is electrically connected to M2.

〔Effect of the invention〕

As described above, the present invention provides a first conductivity type semiconductor layer with a high impurity concentration in a first conductivity type semiconductor substrate, a first layer wiring layer and a second layer wiring layer of a two-layer wiring structure. A semiconductor integrated circuit device having a metal film and a through hole used in the first conductivity type semiconductor layer with a high impurity concentration in the first conductivity type semiconductor substrate and a first conductivity type semiconductor layer used in the first wiring layer. 1
A capacitor made of a metal film and a first insulating film between them, the first metal film used in the first wiring layer, and the third metal film used in the second wiring layer. A capacitor is created using the second insulating film in between. Furthermore, the third metal film used in the second wiring layer and the first conductivity type semiconductor layer with a high impurity concentration in the first conductivity type semiconductor substrate are used for the through holes and the metal film of the first wiring layer. Since they are electrically connected, the structure is such that the capacitors made up of each are connected in parallel. Therefore, there is an effect that the capacitance can be increased compared to the MIS type capacitor of the conventional structure, and the area required is small when manufacturing a capacitance with the same capacitance as the conventional structure.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of the main part of a semiconductor chip showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the main part of a semiconductor chip showing a conventional example. DESCRIPTION OF SYMBOLS 1... N-type semiconductor substrate, 2... N-type semiconductor layer, 3
... first insulating film, 4... first metal film (second electrode), 5... second insulating film, 6... third metal film (third electrode), 7 ...Through hole, 8...Second metal film. Ara 1 diagram Z diagram

Claims (1)

[Claims] A first conductivity type semiconductor layer with a high impurity concentration selectively formed on a first conductivity type semiconductor substrate, a first metal film formed on top of the first conductivity type semiconductor layer with a first insulating film interposed therebetween, and the first conductivity type semiconductor layer. a second metal film electrically connected to the layer, a third metal film provided on the first metal film via an insulating film, and further a third metal film and a second metal film. 1. A semiconductor integrated circuit comprising: a capacitor having means for electrically connecting a capacitor to a capacitor;