JPH06120368A - Semiconductor package and semiconductor device using that - Google Patents
Semiconductor package and semiconductor device using thatInfo
- Publication number
- JPH06120368A JPH06120368A JP4296313A JP29631392A JPH06120368A JP H06120368 A JPH06120368 A JP H06120368A JP 4296313 A JP4296313 A JP 4296313A JP 29631392 A JP29631392 A JP 29631392A JP H06120368 A JPH06120368 A JP H06120368A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- conductor layer
- lead frame
- conductor
- glass
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はリードフレームをガラス
溶着してなる半導体パッケージ及びこれを用いた半導体
装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package in which a lead frame is glass-welded and a semiconductor device using the same.
【０００２】[0002]
【従来の技術および発明が解決しようとする課題】セラ
ミック基板にリードフレームをガラス溶着した半導体パ
ッケージとして、サーディップ、サークワッドタイプ等
の製品が提供されている。これらの製品はパッケージ本
体にセラミックを使用した製品として比較的安価に製造
でき、耐熱性が高い等の利点を有する一方、電気的特性
等の機能面ではそれほど高機能を有しないという問題点
があった。2. Description of the Related Art As a semiconductor package in which a lead frame is glass-welded to a ceramic substrate, products such as sardip and squad type are provided. These products have advantages that they can be manufactured at a relatively low cost as products using ceramics in the package body and that they have high heat resistance, but that they do not have such high functions in terms of electrical characteristics and the like. It was
【０００３】したがって、サーディップあるいはサーク
ワッドタイプの半導体パッケージはそれほど多ピンの製
品は製造されず、さほど高速な素子も搭載されなかった
が、最近はこれらの半導体パッケージも多ピン化の傾向
にあり、高速素子を搭載可能とする優れた電気的特性等
を有するとともに、多層セラミックパッケージと同等の
機能を備えた製品が求められるようになってきた。本発
明はこれら問題点に鑑みてなされたものであり、その目
的とするところは、セラミック基体にリードフレームを
ガラス溶着して成るパッケージで、多層セラミックパッ
ケージと同じような多機能を有する半導体パッケージ及
びこれを用いた半導体装置を提供するにある。Therefore, cerdip or sir quad type semiconductor packages have not been manufactured with a large number of pins, and devices with a relatively high speed have not been mounted. Recently, these semiconductor packages also tend to have a large number of pins. In addition, products having excellent electrical characteristics such that high-speed elements can be mounted and having functions equivalent to those of multilayer ceramic packages have been demanded. The present invention has been made in view of these problems, and an object thereof is a package formed by glass-welding a lead frame to a ceramic substrate, which has a multi-functional semiconductor package similar to a multilayer ceramic package and It is to provide a semiconductor device using this.
【０００４】[0004]
【課題を解決するための手段】本発明は上記目的を達成
するため次の構成を備える。すなわち、リードフレーム
を低融点ガラスによりガラス溶着した半導体パッケージ
において、前記パッケージ本体のセラミック基体上にア
ルミニウムの導体層が形成されるとともに、該アルミニ
ウムの導体層の表面を酸化して形成した酸化被膜を挟ん
でアルミニウムの導体層が形成され、これら複数の導体
層を形成した層上に前記リードフレームがガラス溶着さ
れたことを特徴とする。また、前記半導体パッケージに
半導体チップが搭載され、導体層のうちの一つを接地層
とし、導体層の他の一つを電源層として、前記半導体チ
ップと接地層、電源層、リードフレームとをそれぞれ接
続して成ることを特徴とする。The present invention has the following constitution in order to achieve the above object. That is, in a semiconductor package in which a lead frame is glass-welded with low-melting glass, an aluminum conductor layer is formed on the ceramic base of the package body, and an oxide film formed by oxidizing the surface of the aluminum conductor layer is formed. Aluminum conductor layers are formed so as to be sandwiched, and the lead frame is glass-welded on the layer on which the plurality of conductor layers are formed. In addition, a semiconductor chip is mounted on the semiconductor package, one of the conductor layers serves as a ground layer, and the other one of the conductor layers serves as a power supply layer, and the semiconductor chip, the ground layer, the power supply layer, and the lead frame are connected to each other. It is characterized by being connected to each other.
【０００５】[0005]
【作用】セラミック基体上にアルミニウムを被着して導
体層を形成するとともに、該アルミニウムの導体層の表
面を酸化することによって表面に電気的絶縁性を有する
酸化被膜を形成し、この酸化被膜の上層にさらにアルミ
ニウムを被着させることによって電気的絶縁層を層間に
挟んだ複数の導体層を形成する。リードフレームはこれ
ら導体層の層上に低融点ガラスを介してガラス溶着す
る。導体層は接地層、電源層として使用することがで
き、これによってパッケージの電気的特性を改善するこ
とができる。[Function] The conductor layer is formed by depositing aluminum on the ceramic substrate, and the surface of the conductor layer of aluminum is oxidized to form an oxide film having an electrically insulating property on the surface. Aluminum is further deposited on the upper layer to form a plurality of conductor layers with an electrically insulating layer sandwiched therebetween. The lead frame is glass-welded on the layers of these conductor layers through the low melting point glass. The conductor layer can be used as a ground layer and a power layer, and thereby the electrical characteristics of the package can be improved.
【０００６】[0006]
【実施例】以下、本発明の好適な実施例を添付図面に従
って詳細に説明する。図１は本発明に係る半導体パッケ
ージの一実施例の製造方法を示す説明図である。図１
(a) はパッケージ本体となるセラミック基体１０を形成
した状態を示す。セラミック基体１０はセラミック粉末
を粉末成形し焼成して得る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is an explanatory view showing a manufacturing method of an embodiment of a semiconductor package according to the present invention. Figure 1
(a) shows a state in which the ceramic base body 10 serving as the package body is formed. The ceramic substrate 10 is obtained by powder-molding ceramic powder and firing it.
【０００７】次に、上記セラミック基体１０にアルミニ
ウム金属を蒸着し、第１の導体層１２を形成する。図１
(b) は第１の導体層１２を被着した状態を示す。実施例
では導体層１２はセラミック基体１０の上面で半導体チ
ップを接合する範囲を除いてほぼ全面に設けた。Next, aluminum metal is vapor-deposited on the ceramic substrate 10 to form a first conductor layer 12. Figure 1
(b) shows a state in which the first conductor layer 12 is adhered. In the embodiment, the conductor layer 12 is provided on almost the entire upper surface of the ceramic substrate 10 except the area where the semiconductor chip is bonded.
【０００８】次に、第１の導体層１２にアルマイト処理
を施して導体層１２の表面にアルミニウムの酸化被膜を
形成する。このアルマイト処理は陽極酸化法による。陽
極酸化法では前記導体層１２に陽極側の電極を押接して
アルミニウムの酸化被膜１４を形成する（図１(c) ）。
陽極酸化法によって形成されるアルミニウムの酸化被膜
１４はγAl2O3 ・H2Oのアルミナ結晶として析出し、導
体層１２の表面全体を被覆する。アルミナは電気的絶縁
体であるから、この陽極酸化処理によって導体層１２の
表面に電気的絶縁層が形成されることになる。Next, the first conductor layer 12 is anodized to form an aluminum oxide film on the surface of the conductor layer 12. This alumite treatment is based on the anodic oxidation method. In the anodic oxidation method, an electrode on the anode side is pressed against the conductor layer 12 to form an aluminum oxide film 14 (FIG. 1 (c)).
Oxide layer 14 of aluminum formed by the anodic oxidation method is precipitated as alumina crystals γAl 2 O 3 · H 2 O , to cover the entire surface of the conductor layer 12. Since alumina is an electrical insulator, this anodic oxidation treatment forms an electrical insulating layer on the surface of the conductor layer 12.
【０００９】なお、陽極酸化法では電極が接触する部分
には酸化膜が形成されないから、導体層１２に電極を接
触させる場合には導体層１２の内周縁部でボンディング
ワイヤを接続する部分に電極を接触させて陽極酸化処理
を施す。図１(c) はこのようにして導体層１２の内周縁
部を除いて酸化被膜１４を形成した状態を示す。次に、
上記の酸化被膜１４の上層にアルミニウムを蒸着して第
２の導体層１６を形成する（図１(d) ）。こうして、第
１層と第２層の層間に電気的絶縁性を有する酸化被膜１
４を挟んで２つの導体層１２、１６が形成される。In the anodic oxidation method, an oxide film is not formed at the portion where the electrode is in contact, so when the electrode is brought into contact with the conductor layer 12, the electrode is provided at the inner peripheral edge of the conductor layer 12 where the bonding wire is connected. Are contacted with each other to perform anodizing treatment. FIG. 1 (c) shows a state in which the oxide film 14 is formed in this manner except the inner peripheral edge of the conductor layer 12. next,
Aluminum is vapor-deposited on the oxide layer 14 to form the second conductor layer 16 (FIG. 1 (d)). Thus, the oxide film 1 having electrical insulation between the first layer and the second layer
Two conductor layers 12 and 16 are formed with 4 interposed therebetween.
【００１０】上記のようにセラミック基体１０に導体層
１２、１６を形成した後、低融点ガラス１８を用いてリ
ードフレーム２０をガラス溶着して半導体パッケージを
形成する。半導体チップ２２はセラミック基体１０に接
合した後、第１の導体層１２、第２の導体層１６、リー
ドフレーム２０と各々ワイヤボンディングして接続す
る。第１の導体層１２、第２の導体層１６は多層セラミ
ックパッケージと同じように接地層、電源層として使用
する。導体層１２、１６をそれぞれ接地電位、電源電位
とするためリードフレーム２０の接地ライン、電源ライ
ンと導体層１２、１６とをワイヤボンディングして電気
的に接続する。なお、導体層１２、１６のどちらを接地
層とし、電源層とするかは製品に応じて適宜選択する。After forming the conductor layers 12 and 16 on the ceramic substrate 10 as described above, the lead frame 20 is glass-welded using the low melting point glass 18 to form a semiconductor package. After the semiconductor chip 22 is bonded to the ceramic substrate 10, it is connected to the first conductor layer 12, the second conductor layer 16 and the lead frame 20 by wire bonding. The first conductor layer 12 and the second conductor layer 16 are used as a ground layer and a power supply layer as in the multilayer ceramic package. In order to set the conductor layers 12 and 16 to the ground potential and the power source potential, respectively, the ground line and the power source line of the lead frame 20 are electrically connected to the conductor layers 12 and 16 by wire bonding. Which of the conductor layers 12 and 16 is used as the ground layer and the power layer is appropriately selected according to the product.
【００１１】導体層１２、１６を接地層、電源層とする
ことにより半導体チップ２２と導体層１２、１６とを接
続することで簡単に接地ラインあるいは電源ラインに接
続することができる。これによりリードフレーム２０の
接地ライン、電源ラインに割り当てられるリード数を減
らすことができ、パッケージの多ピン化に有効に対応す
ることができる。また、導体層１２、１６の中間に設け
たアルミニウムの酸化被膜１４は誘電体として作用し、
導体層１２と導体層１６との間でコンデンサー成分を形
成することができる。アルミニウムの酸化被膜の膜厚は
１μｍ程度に制御して形成することができるから、誘電
体を電極間に挟む場合などとくらべてはるかに大きな電
気容量を得ることが可能である。これによって、パッケ
ージの電気的特性を改善しパッケージの高速信号特性を
改善することが可能になる。By using the conductor layers 12 and 16 as the ground layer and the power source layer, the semiconductor chip 22 and the conductor layers 12 and 16 can be easily connected to the ground line or the power source line. As a result, the number of leads assigned to the ground line and the power supply line of the lead frame 20 can be reduced, and it is possible to effectively cope with the increase in the number of pins in the package. Further, the aluminum oxide film 14 provided between the conductor layers 12 and 16 acts as a dielectric,
A capacitor component can be formed between the conductor layer 12 and the conductor layer 16. Since the thickness of the aluminum oxide film can be controlled to be about 1 μm, it is possible to obtain a much larger electric capacity than when a dielectric is sandwiched between electrodes. This makes it possible to improve the electrical characteristics of the package and the high speed signal characteristics of the package.
【００１２】セラミック基体１０に設けた導体層を接地
層あるいは電源層として使用する場合は、導体層を接地
電位あるいは電源電位とする必要がある。この場合、上
記のようにリードフレーム２０の接地ライン、電源ライ
ンと導体層１２、１６とをワイヤボンディングによって
接続する方法とは別に、図２に示すように導体層にリー
ドを直接接続するようにすることも可能である。図２に
示す方法は、セラミック基体１０に導体層１２、１６を
形成した後、低融点ガラス１８をスクリーン印刷する際
に導体層１６を一部露出させる穴を設けておき、電源ラ
イン２４の先端をＬ形に折曲して穴内に先端を挿入する
ことによって電源ライン２４と導体層１６とを接続する
方法である。When the conductor layer provided on the ceramic substrate 10 is used as a ground layer or a power source layer, it is necessary to set the conductor layer to the ground potential or the power source potential. In this case, in addition to the method of connecting the ground line and the power line of the lead frame 20 to the conductor layers 12 and 16 by wire bonding as described above, the leads are directly connected to the conductor layer as shown in FIG. It is also possible to do so. In the method shown in FIG. 2, after the conductor layers 12 and 16 are formed on the ceramic substrate 10, a hole for exposing a part of the conductor layer 16 when screen-printing the low melting point glass 18 is provided and the tip of the power supply line 24 is provided. Is bent into an L shape and the tip is inserted into the hole to connect the power supply line 24 and the conductor layer 16.
【００１３】導体層１６に接続する電源ライン２４は信
号ラインとは異なり前方まで延出させずに外周位置で止
め、導体層１６に接続して導体層１６を電源電位とす
る。電源ライン２４の先端を穴内に挿入し銀ガラス等の
導電性接着剤２６を穴内にドッティングして電源ライン
２４と導体層とを確実に接続する。下層の導体層１２に
対しても電源ライン２４とは別位置で同様にしてリード
フレームの接地ラインと接続することが可能である。た
とえば、導体層１２の外周縁に接地ラインとの接続部を
設ける等による。Unlike the signal line, the power supply line 24 connected to the conductor layer 16 is not extended to the front and is stopped at the outer peripheral position, and is connected to the conductor layer 16 so that the conductor layer 16 has a power supply potential. The tip of the power supply line 24 is inserted into the hole and a conductive adhesive 26 such as silver glass is put into the hole to securely connect the power supply line 24 and the conductor layer. The lower conductor layer 12 can be similarly connected to the ground line of the lead frame at a position different from the power supply line 24. For example, by providing a connection portion with the ground line on the outer peripheral edge of the conductor layer 12.
【００１４】上記実施例では導体層１２、１６を形成す
る金属としてアルミニウムを使用したが、アルミニウム
以外の導体金属も使用可能である。しかしながら、導体
層間に形成する酸化被膜は好適な電気的絶縁性を有する
必要があり、この点電気的絶縁性の優れた酸化被膜が形
成できるアルミニウムまたはアルミニウム合金がもっと
も有効である。また、上記実施例では導体層を２層設け
た例について説明したが、陽極酸化法とアルミニウムの
蒸着を繰り返し使用することにより３層以上の導体層を
形成することも可能である。また、導体層を形成する場
合も、単に所定の全面に導体層を形成する他、任意のパ
ターンに形成することも可能である。また、導体層を複
数層とせずセラミック基体１０上に単層で導体層を設け
てリードフレームをガラス溶着するタイプの製品も有効
である。Although aluminum is used as the metal forming the conductor layers 12 and 16 in the above embodiment, conductor metals other than aluminum can also be used. However, the oxide film formed between the conductor layers needs to have a suitable electrical insulation property, and aluminum or an aluminum alloy capable of forming an oxide film having an excellent electrical insulation property is most effective in this respect. In addition, although an example in which two conductor layers are provided has been described in the above embodiment, it is possible to form three or more conductor layers by repeatedly using the anodic oxidation method and vapor deposition of aluminum. Also, when forming the conductor layer, it is possible to form the conductor layer in an arbitrary pattern in addition to simply forming the conductor layer on a predetermined entire surface. Further, a product of the type in which a single conductor layer is provided on the ceramic substrate 10 without forming a plurality of conductor layers and the lead frame is glass-welded is also effective.
【００１５】また、上記実施例では導体層１２、１６を
形成する際にアルミニウムを蒸着して形成したが、もち
ろんスパッタリング等の他の方法を使用してもよい。本
発明では複数の導体層を形成する方法として、焼成して
得たセラミック基体に対してアルミニウムを蒸着するこ
とと、陽極酸化法によって酸化被膜を形成する方法を採
用することによって、容易に複数の導体層が形成できる
という利点があり、サーディップあるいはサークワッド
タイプの半導体パッケージで多機能を備えた製品として
容易に製造できるという利点がある。Further, in the above embodiment, aluminum was vapor-deposited when the conductor layers 12 and 16 were formed, but of course other methods such as sputtering may be used. In the present invention, as a method of forming a plurality of conductor layers, by adopting a method of depositing aluminum on a ceramic substrate obtained by firing and a method of forming an oxide film by an anodic oxidation method, a plurality of conductor layers can be easily formed. It has an advantage that a conductor layer can be formed, and has an advantage that it can be easily manufactured as a product having multiple functions in a sardip or squad type semiconductor package.
【００１６】[0016]
【発明の効果】本発明に係る半導体パッケージ及びこれ
を用いた半導体装置によれば、上述したように、パッケ
ージ内にリードフレームの他に接地層、電源層として使
用できる導体層を別層で形成したことにより、リードフ
レームの多ピン化を図ることができるとともに、パッケ
ージを多機能化させることができ高速素子を搭載するこ
とが可能になる等の著効を奏する。According to the semiconductor package and the semiconductor device using the same according to the present invention, as described above, a conductor layer that can be used as a ground layer and a power supply layer is formed as a separate layer in the package in addition to the lead frame. As a result, the lead frame can have a large number of pins, the package can be made to have multiple functions, and high-speed elements can be mounted.
【図１】半導体パッケージの一実施例の製造方法を示す
説明図である。FIG. 1 is an explanatory diagram showing a manufacturing method of an embodiment of a semiconductor package.
【図２】導体層と電源ラインとの接続方法を示す説明図
である。FIG. 2 is an explanatory diagram showing a method of connecting a conductor layer and a power supply line.
１０ セラミック基体 １２、１６ 導体層 １４ 酸化被膜 １８ 低融点ガラス ２０ リードフレーム ２２ 半導体チップ ２４ 電源ライン ２６ 導電性接着剤 10 Ceramic Substrate 12, 16 Conductor Layer 14 Oxide Film 18 Low Melting Glass 20 Lead Frame 22 Semiconductor Chip 24 Power Line 26 Conductive Adhesive
Claims (2)
ラス溶着した半導体パッケージにおいて、 前記パッケージ本体のセラミック基体上にアルミニウム
の導体層が形成されるとともに、 該アルミニウムの導体層の表面を酸化して形成した酸化
被膜を挟んでアルミニウムの導体層が形成され、 これら複数の導体層を形成した層上に前記リードフレー
ムがガラス溶着されたことを特徴とする半導体パッケー
ジ。1. A semiconductor package in which a lead frame is glass-welded with a low melting point glass, wherein an aluminum conductor layer is formed on a ceramic base of the package body, and the surface of the aluminum conductor layer is oxidized to form. A semiconductor package, characterized in that an aluminum conductor layer is formed with an oxide film sandwiched therebetween, and the lead frame is glass-welded on a layer having the plurality of conductor layers formed therein.
体チップが搭載され、導体層のうちの一つを接地層と
し、導体層の他の一つを電源層として、 前記半導体チップと接地層、電源層、リードフレームと
をそれぞれ接続して成ることを特徴とする半導体装置。2. A semiconductor chip is mounted on the semiconductor package according to claim 1, wherein one of the conductor layers serves as a ground layer and the other one of the conductor layers serves as a power supply layer, and the semiconductor chip and the ground layer, A semiconductor device comprising a power supply layer and a lead frame connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4296313A JPH06120368A (en) | 1992-10-08 | 1992-10-08 | Semiconductor package and semiconductor device using that |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4296313A JPH06120368A (en) | 1992-10-08 | 1992-10-08 | Semiconductor package and semiconductor device using that |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06120368A true JPH06120368A (en) | 1994-04-28 |
Family
ID=17831934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4296313A Pending JPH06120368A (en) | 1992-10-08 | 1992-10-08 | Semiconductor package and semiconductor device using that |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06120368A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523621A (en) * | 1994-05-15 | 1996-06-04 | Kabushiki Kaisha Toshiba | Semiconductor device having a multilayer ceramic wiring substrate |
| JP2007258714A (en) * | 2006-03-20 | 2007-10-04 | Samsung Electro-Mechanics Co Ltd | Insulating structure suitable for high-temperature process, and its manufacturing method |
-
1992
- 1992-10-08 JP JP4296313A patent/JPH06120368A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5523621A (en) * | 1994-05-15 | 1996-06-04 | Kabushiki Kaisha Toshiba | Semiconductor device having a multilayer ceramic wiring substrate |
| JP2007258714A (en) * | 2006-03-20 | 2007-10-04 | Samsung Electro-Mechanics Co Ltd | Insulating structure suitable for high-temperature process, and its manufacturing method |
| US7998879B2 (en) | 2006-03-20 | 2011-08-16 | Samsung Electro-Mechanics Co., Ltd. | Insulation structure for high temperature conditions and manufacturing method thereof |
| US9231167B2 (en) | 2006-03-20 | 2016-01-05 | Samsung Electronics Co., Ltd. | Insulation structure for high temperature conditions and manufacturing method thereof |
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