JPH06163807A - Package for housing semiconductor element - Google Patents
Package for housing semiconductor elementInfo
- Publication number
- JPH06163807A JPH06163807A JP30915392A JP30915392A JPH06163807A JP H06163807 A JPH06163807 A JP H06163807A JP 30915392 A JP30915392 A JP 30915392A JP 30915392 A JP30915392 A JP 30915392A JP H06163807 A JPH06163807 A JP H06163807A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- package
- insulating substrate
- housing
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関し、より詳細には
内部に収容する半導体素子への電源ノイズの悪影響を有
効に防止するようになした半導体素子収納用パッケージ
の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element accommodating package for accommodating semiconductor elements, and more particularly to a semiconductor for effectively preventing adverse effects of power source noise on semiconductor elements accommodated inside. The present invention relates to improvement of an element storage package.
【０００２】[0002]
【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは図３に示すように、酸化アル
ミニウム質焼結体から成り、上面に半導体素子10を収容
するための凹部11a 及び該凹部11a 周辺から下面にかけ
て導出するタングステン、モリブデン、マンガン等の高
融点金属粉末から成るメタライズ配線層12を有する絶縁
基体11と、半導体素子10の各電極を外部電気回路に接続
するために前記メタライズ配線層12に銀ロウ等のロウ材
を介し取着された外部リード端子13と、蓋体14とから構
成されており、絶縁基体11の凹部11a 底面に半導体素子
10をガラス、樹脂、ロウ材等の接着剤を介して接着固定
するとともに各電極をメタライズ配線層12にボンディン
グワイヤ15を介して電気的に接続し、しかる後、絶縁基
体11の上面に蓋体14をガラス、樹脂、ロウ材等の封止材
を介して接合させ，絶縁基体11と蓋体14とから成る容器
内部に半導体素子10を気密に封入することによって製品
としての半導体装置となる。2. Description of the Related Art Conventionally, as shown in FIG. 3, a semiconductor element accommodating package for accommodating a semiconductor element is made of an aluminum oxide sintered body and has a concave portion 11a for accommodating the semiconductor element 10 and an upper surface thereof. An insulating substrate 11 having a metallized wiring layer 12 made of a refractory metal powder such as tungsten, molybdenum, or manganese, which is led out from the periphery of the recess 11a to the lower surface, and the metallized wiring for connecting each electrode of the semiconductor element 10 to an external electric circuit. It is composed of an external lead terminal 13 attached to the layer 12 via a brazing material such as silver solder, and a lid 14, and the semiconductor element is provided on the bottom surface of the recess 11a of the insulating base 11.
10 is adhered and fixed through an adhesive such as glass, resin, or a brazing material, and each electrode is electrically connected to the metallized wiring layer 12 through a bonding wire 15, and thereafter, a lid is provided on the upper surface of the insulating base 11. A semiconductor device as a product is obtained by bonding 14 through a sealing material such as glass, resin, a brazing material, etc., and hermetically sealing the semiconductor element 10 inside a container composed of the insulating base 11 and the lid 14.
【０００３】尚、かかる従来の半導体素子収納用パッケ
ージは絶縁基体11の上面に内部に収容する半導体素子10
の電源電極及び接地電極に接続される接続パッド16が形
成されており、該接続パッドにチタン酸バリウム磁器を
誘電体とした容量素子17が半田等のロウ材やエポキシ樹
脂に銀粉末を充填して成る導電性接着剤を介して直接取
着され、半導体素子10の電源電極と接地電極の間に容量
素子を接続することによって半導体素子10への電源ノイ
ズの悪影響を有効に防止するように成っている。The conventional package for accommodating a semiconductor element has a semiconductor element 10 housed inside an upper surface of an insulating substrate 11.
Connection pads 16 to be connected to the power supply electrode and the ground electrode of are formed, and the connection elements are filled with a brazing material such as solder or an epoxy resin with silver powder as a capacitive element 17 using barium titanate porcelain as a dielectric. It is directly attached via a conductive adhesive composed of a semiconductor element 10, and a capacitive element is connected between the power electrode and the ground electrode of the semiconductor element 10 to effectively prevent the adverse effect of power source noise on the semiconductor element 10. ing.
【０００４】しかしながら、この従来の半導体素子収納
用パッケージは半導体素子10を収容する絶縁基体11が酸
化アルミニウム質焼結体から成り、その熱伝導率が15W/
m ・K と低いこと及び近時、半導体素子10は高密度化、
高集積化、高速度化が急激に進み、半導体素子10の単位
面積、単位体積当たりの発熱量が増大してきたこと等か
ら絶縁基体11の凹部11a 内に半導体素子10を収容し、半
導体装置となした後、半導体素子10を作動させると半導
体素子10が該素子10自身の発する熱によって高温とな
り、半導体素子10に熱破壊を起こさせたり、特性に熱変
化を来し、誤動作させるという欠点を有していた。However, in this conventional semiconductor element housing package, the insulating substrate 11 for housing the semiconductor element 10 is made of an aluminum oxide sintered body, and its thermal conductivity is 15 W /
It is as low as m · K, and recently, the semiconductor element 10 has a higher density,
Due to the rapid progress of high integration and high speed, the amount of heat generated per unit area and unit volume of the semiconductor element 10 has increased, the semiconductor element 10 is housed in the recess 11a of the insulating base 11, and the semiconductor device After that, when the semiconductor element 10 is operated, the semiconductor element 10 becomes a high temperature due to the heat generated by the element 10 itself, causing thermal destruction of the semiconductor element 10 or causing a thermal change in the characteristics, which causes a malfunction. Had.
【０００５】そこで上記欠点を解消するために絶縁基体
11を酸化アルミニウム質焼結体に変えて熱伝導率が50W/
m ・K 以上と極めて熱を伝えやすい窒化アルミニウム質
焼結体で形成し、半導体素子10の発する熱を絶縁基体11
を介し大気中に良好に放散させることが考えられる。Therefore, in order to solve the above-mentioned drawbacks, an insulating substrate
11 is replaced with aluminum oxide sintered body and the thermal conductivity is 50 W /
The heat generated by the semiconductor element 10 is formed by an aluminum nitride sintered body that is extremely easy to transfer heat at m.
It is thought that it is satisfactorily released into the atmosphere via
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、窒化ア
ルミニウム質焼結体で絶縁基体11を形成した場合、窒化
アルミニウム質焼結体の熱膨張係数は4 〜5 ×10-6/ ℃
であり、容量素子17を構成するチタン酸バリウム磁器の
熱膨張係数(10 〜11×10-6/ ℃) と大きく相違するため
半導体素子10の作動時に発する熱が絶縁基体11と容量素
子17との接合部に印加されると両者の接合部に両者の熱
膨張係数の相違に起因する大きな熱応力が発生し、その
結果、前記熱応力によって容量素子17が絶縁基体11上面
より外れ、容量素子17によって半導体素子10への電源ノ
イズの悪影響を有効に防止することができなくなるとい
う欠点を誘発した。However, when the insulating substrate 11 is formed of an aluminum nitride sintered body, the thermal expansion coefficient of the aluminum nitride sintered body is 4 to 5 × 10 -6 / ° C.
The thermal expansion coefficient of the barium titanate porcelain that constitutes the capacitive element 17 (10 to 11 × 10 -6 / ° C.) is greatly different from the heat generated during the operation of the semiconductor element 10 between the insulating substrate 11 and the capacitive element 17. When applied to the joint portion of, a large thermal stress is generated in the joint portion due to the difference in thermal expansion coefficient between the two, and as a result, the thermal element causes the capacitive element 17 to deviate from the upper surface of the insulating substrate 11, 17 has caused a drawback that the adverse effect of power supply noise on the semiconductor element 10 cannot be effectively prevented.
【０００７】[0007]
【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は半導体素子への熱の影響及び電源ノイ
ズの影響を有効に防止し、半導体素子を長期間にわたり
正常、且つ安定に作動させることができる半導体素子収
納用パッケージを提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to effectively prevent the influence of heat and power supply noise on a semiconductor element, and to keep the semiconductor element normal for a long period of time, and An object of the present invention is to provide a package for accommodating semiconductor devices, which can be operated stably.
【０００８】[0008]
【課題を解決するための手段】本発明は内部に半導体素
子を収容するための空所を有する窒化アルミニウム質焼
結体から成る絶縁容器の外表面に、内部に収容する半導
体素子の電源電極及び接地電極に接続される接続パッド
を形成するとともに該接続パッドに容量素子を取着して
成る半導体素子収納用パッケージであって、前記絶縁容
器に形成された接続パッドと容量素子との間にビッカー
ス硬度（Ｈｖ）が300 以下の軟質な金属部材が介在して
いることを特徴とするものである。According to the present invention, a power supply electrode for a semiconductor element to be housed therein is provided on the outer surface of an insulating container made of an aluminum nitride sintered body having a cavity for housing the semiconductor element therein. What is claimed is: 1. A semiconductor element housing package comprising a connection pad connected to a ground electrode and a capacitance element attached to the connection pad, the Vickers being formed between the connection pad and the capacitance element formed in the insulating container. It is characterized in that a soft metal member having a hardness (Hv) of 300 or less is interposed.
【０００９】[0009]
【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁容器を窒化アルミニウム質焼結体で形成したこ
とから半導体素子の作動時に発する熱は容器を介して大
気中に良好に放散され、その結果、容器内部に収容され
る半導体素子は常に低温となり、半導体素子を長期間に
わたり正常、且つ安定に作動させることができる。According to the package for accommodating a semiconductor element of the present invention, since the insulating container is made of the aluminum nitride sintered body, the heat generated during the operation of the semiconductor device is well dissipated into the atmosphere through the container. As a result, the semiconductor element housed inside the container is always at a low temperature, and the semiconductor element can be operated normally and stably for a long period of time.
【００１０】また絶縁容器の外表面に設けた接続パッド
と容量素子とを間にビッカース硬度（Ｈｖ）が300 以下
の軟質な金属部材を介在させた状態で取着したことから
絶縁容器と容量素子との間に発生する両者の熱膨張係数
の相違に起因する熱応力は前記金属部材を変形させるこ
とによって吸収され、その結果、絶縁容器に容量素子が
強固に取着され、該容量素子によって半導体素子への電
源ノイズの悪影響が有効に防止される。Further, since the soft metal member having a Vickers hardness (Hv) of 300 or less is attached between the connection pad provided on the outer surface of the insulating container and the capacitive element, the insulating container and the capacitive element are attached. The thermal stress caused by the difference in the thermal expansion coefficient between the two is absorbed by deforming the metal member, and as a result, the capacitive element is firmly attached to the insulating container, and the semiconductor element is attached by the capacitive element. The adverse effect of power supply noise on the element is effectively prevented.
【００１１】[0011]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。The present invention will now be described in detail with reference to the accompanying drawings.
【００１２】図1 及び図2 は本発明の半導体素子収納用
パッケージの一実施例を示し、1 は絶縁基体、2 は蓋体
である。この絶縁基体1 と蓋体2 とで半導体素子3 を収
容するための容器4 が構成される。1 and 2 show an embodiment of a package for housing a semiconductor device according to the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 form a container 4 for housing the semiconductor element 3.
【００１３】前記絶縁基体1 は窒化アルミニウム質焼結
体から成り、その上面に凹部1aを有し、該凹部1a底面に
は半導体素子3 がガラス、樹脂、ロウ材等の接着剤を介
して接着固定される。The insulating substrate 1 is made of an aluminum nitride sintered body and has a recess 1a on its upper surface. The semiconductor element 3 is bonded to the bottom of the recess 1a with an adhesive such as glass, resin or brazing material. Fixed.
【００１４】前記窒化アルミニウム質焼結体から成る絶
縁基体1 は例えば、アルミナ(Al 2O 3 ) 、イットリア
(Y2 O 3 ) 、カルシア(CaO) 、マグネシア(MgO) 等の原
料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状と
なすとともにこれを従来周知のドクターブレード法やカ
レンダーロール法等を採用することによってセラミック
グリーンシート( セラミック生シート) を得、しかる
後、前記セラミックグリーンシートに適当な打ち抜き加
工を施すとともに複数枚積層し、高温( 約1800℃) で焼
成することによって製作される。The insulating substrate 1 made of the aluminum nitride sintered material is, for example, alumina (Al 2 O 3 ) or yttria.
(Y 2 O 3 ), calcia (CaO), magnesia (MgO), etc.A suitable organic solvent is added to the raw material powder and mixed with the solvent to form a slurry, which is conventionally known as a doctor blade method or a calendar roll method. A ceramic green sheet (ceramic green sheet) is obtained by adopting, and thereafter, the ceramic green sheet is appropriately punched, laminated with a plurality of sheets, and fired at a high temperature (about 1800 ° C). .
【００１５】前記窒化アルミニウム焼結体から成る絶縁
基体1 はその熱伝導率が50W/m ・K以上であり、熱を伝
え易いことから半導体素子3 が作動時に多量の熱を発生
したとしてもその熱は絶縁基体1 を介して大気中に良好
に放散され、その結果、半導体素子3 は該素子3 自身の
発する熱によって高温になることは一切なく、半導体素
子3 に熱破壊や特性に熱変化を来し、誤動作を起こさせ
ることはなくなる。Since the insulating substrate 1 made of the aluminum nitride sintered body has a thermal conductivity of 50 W / m · K or more and easily transfers heat, even if the semiconductor element 3 generates a large amount of heat during operation, The heat is satisfactorily dissipated into the atmosphere through the insulating substrate 1, and as a result, the semiconductor element 3 is never heated to a high temperature by the heat generated by the element 3 itself, and the semiconductor element 3 is thermally destroyed or its characteristics change. Will not cause a malfunction.
【００１６】また前記絶縁基体1 は凹部1a周辺から下面
にかけて複数個のメタライズ配線層5 が被着形成されて
おり、該メタライズ配線層5 の凹部1a周辺部には半導体
素子3 の各電極( 電源電極、接地電極、信号電極) がボ
ンディングワイヤ6 を介して電気的に接続され、また絶
縁基体1 の下面に導出された部位には外部電気回路と接
続される外部リード端子7 が銀ロウ等のロウ材を介し取
着されている。Further, a plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery of the recess 1a to the lower surface thereof, and the metallized wiring layer 5 is surrounded by the recesses 1a. (Electrode, ground electrode, signal electrode) are electrically connected via the bonding wire 6, and the external lead terminal 7 connected to an external electric circuit is connected to an external electric circuit at a portion led out to the lower surface of the insulating substrate 1. It is attached via brazing material.
【００１７】前記メタライズ配線層5 はタングステン、
モリブデン、マンガン等の高融点金属粉末から成り、該
タングステン等の高融点金属粉末に適当な有機溶剤、溶
媒を添加混合して得た金属ペーストを絶縁基体1 となる
セラミックグリーンシートに予め従来周知のスクリーン
印刷法により所定パターンに印刷塗布しておくことによ
って絶縁基体1 の凹部1a周辺から下面にかけて被着され
る。The metallized wiring layer 5 is made of tungsten,
A metal paste made of a refractory metal powder such as molybdenum or manganese, which is obtained by adding and mixing an appropriate organic solvent or a solvent to the refractory metal powder such as tungsten is previously known to the ceramic green sheet serving as the insulating substrate 1. By printing and applying a predetermined pattern by the screen printing method, the insulating substrate 1 is deposited from around the recess 1a to the lower surface.
【００１８】尚、前記メタライズ配線層5 はその露出表
面にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ
性の良い金属をメッキ法により1.0 乃至20.0μm の厚み
に層着させておくとメタライズ配線層5 の酸化腐食を有
効に防止することができるとともにメタライズ配線層5
とボンディングワイヤ6 との接続及びメタライズ配線層
5 への外部リード端子の取着を強固となすことができ
る。従って、メタライズ配線層5 の酸化腐食を防止し、
メタライズ配線層5 とボンディングワイヤ6 及び外部リ
ード端子7 との取着を強固とするにはメタライズ配線層
5 の露出表面にニッケル、金等を1.0 乃至20.0μm の厚
みに層着させておくことが好ましい。The metallized wiring layer 5 is formed by depositing a metal such as nickel or gold, which has excellent corrosion resistance and has a good wettability with a brazing material, to a thickness of 1.0 to 20.0 μm by plating. The metallized wiring layer 5 can be effectively prevented from being oxidized and corroded.
And bonding wire 6 and metallized wiring layer
It is possible to firmly attach the external lead terminal to 5. Therefore, the oxidation corrosion of the metallized wiring layer 5 is prevented,
To strengthen the attachment of the metallized wiring layer 5 to the bonding wires 6 and the external lead terminals 7, the metallized wiring layer
It is preferable to deposit nickel, gold or the like on the exposed surface of layer 5 in a thickness of 1.0 to 20.0 μm.
【００１９】また前記メタライズ配線層5 に銀ロウ等の
ロウ材を介して取着される外部リード端子7 はコバール
金属( 鉄ーニッケルーコバルト合金) や42アロイ( 鉄ー
ニッケル合金) 等の金属材料から成り、外部リード端子
7 を外部電気回路に接続することによって絶縁基体1 の
凹部1a内に収容される半導体素子3 の各電極はメタライ
ズ配線層5 及び外部リード端子7 を介して外部電気回路
に電気的に接続されることとなる。The external lead terminals 7 attached to the metallized wiring layer 5 via a brazing material such as silver brazing are metal materials such as Kovar metal (iron-nickel-cobalt alloy) and 42 alloy (iron-nickel alloy). Consisting of an external lead terminal
Each electrode of the semiconductor element 3 housed in the recess 1a of the insulating substrate 1 by connecting 7 to the external electric circuit is electrically connected to the external electric circuit via the metallized wiring layer 5 and the external lead terminal 7. It will be.
【００２０】前記外部リード端子7 はコバール金属のイ
ンゴット( 塊) を圧延加工法や打ち抜き加工法等、従来
周知の金属加工法を採用することによって所定の形状に
形成される。The external lead terminal 7 is formed in a predetermined shape by adopting a conventionally known metal processing method such as a rolling method or a punching method for an ingot (lump) of Kovar metal.
【００２１】また前記外部リード端子7 はその露出表面
にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ性
の良い金属をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくと外部リード端子7 の酸化腐食を有効に
防止することができるとともに外部リード端子7 を半田
等のロウ材を介し外部電気回路に強固に接続することが
可能となる。従って、前記外部リード端子7 はその露出
表面にニッケル、金等を1.0 乃至20.0μm の厚みに層着
させておくことが好ましい。Further, the external lead terminal 7 may be formed by depositing a metal such as nickel or gold, which has excellent corrosion resistance and has good wettability with a brazing material, to a thickness of 1.0 to 20.0 μm by plating. Oxidation and corrosion of the external lead terminals 7 can be effectively prevented, and the external lead terminals 7 can be firmly connected to an external electric circuit via a brazing material such as solder. Therefore, it is preferable that the exposed surface of the external lead terminal 7 is layered with nickel, gold or the like in a thickness of 1.0 to 20.0 μm.
【００２２】前記絶縁基体1 はまたその上面に内部に収
容する半導体素子3 の電源電極及び接地電極に接続され
る接続パッド5aが形成されており、該接続パッド5aには
容量素子8 が間にビッカース硬度（Ｈｖ）が300 以下の
軟質な金属部材9 を挟んだ状態で半田や導電性樹脂によ
り取着されている。The insulating substrate 1 also has on its upper surface a connection pad 5a connected to the power supply electrode and the ground electrode of the semiconductor element 3 housed therein, and the capacitance element 8 is interposed between the connection pad 5a and the connection pad 5a. The soft metal member 9 having a Vickers hardness (Hv) of 300 or less is sandwiched and is attached by solder or conductive resin.
【００２３】前記接続パッド5aは容量素子8 を絶縁基体
1 上面に取着させるための下地部材として作用するとと
もに容量素子8 を半導体素子3 の電源電極と接地電極の
間に接続させる作用を為し、タングステン、モリブデ
ン、マンガン等の高融点金属粉末により形成されてい
る。The connection pad 5a serves as an insulating base for the capacitive element 8.
1 It acts as a base member for attachment to the upper surface and also acts to connect the capacitive element 8 between the power supply electrode and the ground electrode of the semiconductor element 3, and is made of a refractory metal powder such as tungsten, molybdenum, or manganese. Has been done.
【００２４】尚、前記接続パッド5aはメタライズ配線層
5 と同様の方法によって絶縁基体1の上面に所定形状に
形成される。The connection pad 5a is a metallized wiring layer.
A predetermined shape is formed on the upper surface of the insulating substrate 1 by the same method as in 5.
【００２５】また前記接続パッド5aに取着される容量素
子8 は例えば、チタン酸バリウム磁器内に対向電極を多
数埋設して形成され、該容量素子8 は半導体素子3 の誤
動作の原因となる供給電源電圧の変動に起因する電源ノ
イズを除去する作用を為し、これによって半導体素子3
は電源ノイズの悪影響から保護され、長期間にわたり正
常、且つ安定に作動することが可能となる。The capacitive element 8 attached to the connection pad 5a is formed, for example, by embedding a large number of opposing electrodes in a barium titanate porcelain, and the capacitive element 8 is a supply element that causes malfunction of the semiconductor element 3. It acts to eliminate power supply noise caused by fluctuations in the power supply voltage, which allows the semiconductor element 3
Is protected from the adverse effects of power supply noise and can operate normally and stably for a long period of time.
【００２６】更に前記絶縁基体1 に設けた接続パッド5a
と容量素子8 との間にはビッカース硬度（Ｈｖ）を300
以下とした軟質な金属部材9 が介在されており、該金属
部材9 はそれ自体が変形することによって絶縁基体1 と
容量素子8 との間に両者の熱膨張係数の相違に起因して
発生する熱応力を吸収し、これによって絶縁基体1 に容
量素子8 が強固に取着されることとなり、容量素子8 に
よって半導体素子3 への電源ノイズの悪影響が有効に防
止されることとなる。Further, connection pads 5a provided on the insulating base 1
Vickers hardness (Hv) between the capacitor and the capacitive element 8 is 300
The following soft metal member 9 is interposed, and the metal member 9 is generated between the insulating substrate 1 and the capacitive element 8 due to the deformation of the metal member 9 due to the difference in thermal expansion coefficient between them. The thermal stress is absorbed, whereby the capacitive element 8 is firmly attached to the insulating base 1, and the capacitive element 8 effectively prevents the adverse effect of power source noise on the semiconductor element 3.
【００２７】尚、前記金属部材9 はそのビッカース硬度
（Ｈｖ）が300 を越える硬質なものになると金属部材9
を変形させることによって絶縁基体1 と容量素子8 との
間に発生する熱応力を吸収するのが困難となる。従っ
て、前記金属部材9 はそのビッカース硬度（Ｈｖ）が30
0 以下の軟質なものに特定される。If the Vickers hardness (Hv) of the metal member 9 exceeds 300, the metal member 9 will be
By deforming, it becomes difficult to absorb the thermal stress generated between the insulating substrate 1 and the capacitive element 8. Therefore, the metal member 9 has a Vickers hardness (Hv) of 30.
It is specified to be softer than 0.
【００２８】また前記金属部材9 としては銅、コバール
金属等のビッカース硬度（Ｈｖ）が300 以下の軟質な材
料が好適に使用され、断面が板状、波状、Ｓ字状として
絶縁基体1 に設けた接続パッド5aと容量素子8 との間に
介在される。As the metal member 9, a soft material having a Vickers hardness (Hv) of 300 or less, such as copper or Kovar metal, is preferably used and is provided on the insulating substrate 1 with a plate-shaped, corrugated or S-shaped cross section. It is interposed between the connection pad 5a and the capacitive element 8.
【００２９】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体１の凹部1a底面に半導体素子3 を
ガラス、樹脂、ロウ材等の接着剤を介して接着固定する
とともに半導体素子3 の各電極をメタライズ配線層5 に
ボンディングワイヤ6 を介して電気的に接続し、しかる
後、絶縁基体1 の上面に蓋体2 をガラス、樹脂、ロウ材
等から成る封止材を介して接合させ、絶縁基体1 と蓋体
2 とから成る容器4 内部に半導体素子3 を気密に収容す
ることによって製品としての半導体装置が完成する。Thus, according to the package for accommodating semiconductor elements of the present invention, the semiconductor element 3 is adhered and fixed to the bottom surface of the recess 1a of the insulating substrate 1 via an adhesive such as glass, resin, or brazing material, and each electrode of the semiconductor element 3 is attached. Are electrically connected to the metallized wiring layer 5 via bonding wires 6, and then the lid 2 is bonded to the upper surface of the insulating substrate 1 via a sealing material made of glass, resin, brazing material, etc. Base 1 and lid
A semiconductor device as a product is completed by hermetically housing the semiconductor element 3 in a container 4 composed of 2 and.
【００３０】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。The present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the gist of the present invention.
【００３１】[0031]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば絶縁容器を窒化アルミニウム質焼結体で形成した
ことから半導体素子の作動時に発する熱は容器を介して
大気中に良好に放散され、その結果、容器内部に収容さ
れる半導体素子は常に低温となり、半導体素子を長期間
にわたり正常、且つ安定に作動させることができる。According to the package for accommodating semiconductor elements of the present invention, since the insulating container is made of the aluminum nitride sintered material, the heat generated during the operation of the semiconductor element is radiated well into the atmosphere through the container, As a result, the temperature of the semiconductor element housed inside the container is always low, and the semiconductor element can be operated normally and stably for a long period of time.
【００３２】また絶縁容器の外表面に設けた接続パッド
と容量素子とを間にビッカース硬度（Ｈｖ）が300 以下
の軟質な金属部材を介在させた状態で取着したことから
絶縁容器と容量素子との間に発生する両者の熱膨張係数
の相違に起因する熱応力は前記金属部材を変形させるこ
とによって吸収され、その結果、絶縁容器に容量素子が
強固に取着され、該容量素子によって半導体素子への電
源ノイズの悪影響が有効に防止される。Since the soft metal member having a Vickers hardness (Hv) of 300 or less is attached between the connection pad provided on the outer surface of the insulating container and the capacitive element, the insulating container and the capacitive element are attached. The thermal stress caused by the difference in the thermal expansion coefficient between the two is absorbed by deforming the metal member, and as a result, the capacitive element is firmly attached to the insulating container, and the semiconductor element is attached by the capacitive element. The adverse effect of power supply noise on the element is effectively prevented.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.
【図２】図1 に示すパッケージの要部拡大断面図であ
る。FIG. 2 is an enlarged sectional view of a main part of the package shown in FIG.
【図３】従来の半導体素子収納用パッケージの断面図で
ある。FIG. 3 is a cross-sectional view of a conventional semiconductor element housing package.
１・・・・・絶縁基体 ２・・・・・蓋体 ３・・・・・半導体素子 ４・・・・・絶縁容器 ５・・・・・メタライズ配線層 ５ａ・・・・接続パッド ８・・・・・容量素子 ９・・・・・金属部材 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4 ... Insulating container 5 ... Metallized wiring layer 5a ... Connection pad 8. .... Capacitance element 9 ... Metal member
Claims (1)
有する窒化アルミニウム質焼結体から成る絶縁容器の外
表面に、内部に収容する半導体素子の電源電極及び接地
電極に接続される接続パッドを形成するとともに該接続
パッドに容量素子を取着して成る半導体素子収納用パッ
ケージであって、前記絶縁容器に形成された接続パッド
と容量素子との間にビッカース硬度（Ｈｖ）が３００以
下の軟質な金属部材が介在していることを特徴とする半
導体素子収納用パッケージ。1. A connection, which is connected to a power electrode and a ground electrode of a semiconductor element housed inside, on the outer surface of an insulating container made of an aluminum nitride sintered body having a cavity for housing a semiconductor element inside. A package for accommodating a semiconductor element, comprising a pad and a capacitance element attached to the connection pad, wherein a Vickers hardness (Hv) between the connection pad and the capacitance element formed in the insulating container is 300 or less. A semiconductor element housing package, characterized in that the soft metal member of (1) is interposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30915392A JP2962951B2 (en) | 1992-11-19 | 1992-11-19 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30915392A JP2962951B2 (en) | 1992-11-19 | 1992-11-19 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06163807A true JPH06163807A (en) | 1994-06-10 |
| JP2962951B2 JP2962951B2 (en) | 1999-10-12 |
Family
ID=17989562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30915392A Expired - Lifetime JP2962951B2 (en) | 1992-11-19 | 1992-11-19 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2962951B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777383A (en) * | 1996-05-09 | 1998-07-07 | Lsi Logic Corporation | Semiconductor chip package with interconnect layers and routing and testing methods |
| US7064412B2 (en) * | 2000-01-25 | 2006-06-20 | 3M Innovative Properties Company | Electronic package with integrated capacitor |
-
1992
- 1992-11-19 JP JP30915392A patent/JP2962951B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5777383A (en) * | 1996-05-09 | 1998-07-07 | Lsi Logic Corporation | Semiconductor chip package with interconnect layers and routing and testing methods |
| US7064412B2 (en) * | 2000-01-25 | 2006-06-20 | 3M Innovative Properties Company | Electronic package with integrated capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2962951B2 (en) | 1999-10-12 |
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