JPH06236938A - Package for semiconductor-element housing - Google Patents

Package for semiconductor-element housing

Info

Publication number
JPH06236938A
JPH06236938A JP5022665A JP2266593A JPH06236938A JP H06236938 A JPH06236938 A JP H06236938A JP 5022665 A JP5022665 A JP 5022665A JP 2266593 A JP2266593 A JP 2266593A JP H06236938 A JPH06236938 A JP H06236938A
Authority
JP
Japan
Prior art keywords
semiconductor element
package
semiconductor
sintered body
capacitive element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5022665A
Other languages
Japanese (ja)
Inventor
Eizou Otosu
栄蔵 乙須
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP5022665A priority Critical patent/JPH06236938A/en
Publication of JPH06236938A publication Critical patent/JPH06236938A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a package, for semiconductor-element housing, wherein it can effectively prevent the influence of heat and the influence of a power- supply noise on a semiconductor element and it can operate the semiconductor element normally and stably for a long time. CONSTITUTION:In a package for semiconductor-element housing, connecting pads 5a connected to a power-supply electrode and a grounding electrode for a semiconductor element housed at the inside are formed in an insulating container 1 which has a space used to house the semiconductor element at the inside and which is composed of an aluminum nitride sintered body, and a capacity element is attached and bonded to the connecting pads 5a. In the package, a sheet member 9 composed of an aluminum oxide sintered body is interposed between the connecting pads 5a formed in the insulating container 1 and the capacity element 8.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関し、より詳細には
内部に収容する半導体素子への電源ノイズの悪影響を有
効に防止するようになした半導体素子収納用パッケージ
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element accommodating package for accommodating semiconductor elements, and more particularly to a semiconductor for effectively preventing adverse effects of power source noise on semiconductor elements accommodated inside. The present invention relates to an element storage package.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは図3に示すように、酸化アル
ミニウム質焼結体から成り、上面に半導体素子10を収容
するための凹部11a 及び該凹部11a 周辺から下面にかけ
て導出するタングステン、モリブデン、マンガン等の高
融点金属粉末から成るメタライズ配線層12を有する絶縁
基体11と、半導体素子10の各電極を外部電気回路に接続
するために前記メタライズ配線層12に銀ロウ等のロウ材
を介し取着された外部リード端子13と、蓋体14とから構
成されており、絶縁基体11の凹部11a 底面に半導体素子
10をガラス、樹脂、ロウ材等の接着剤を介して接着固定
するとともに各電極をメタライズ配線層12にボンディン
グワイヤ15を介して電気的に接続し、しかる後、絶縁基
体11の上面に蓋体14をガラス、樹脂、ロウ材等の封止材
を介して接合させ、絶縁基体11と蓋体14とから成る容器
内部に半導体素子10を気密に封入することによって製品
として半導体装置となる。
2. Description of the Related Art Conventionally, as shown in FIG. 3, a semiconductor element accommodating package for accommodating a semiconductor element is made of an aluminum oxide sintered body and has a concave portion 11a for accommodating the semiconductor element 10 and an upper surface thereof. An insulating substrate 11 having a metallized wiring layer 12 made of a refractory metal powder such as tungsten, molybdenum, or manganese, which is led out from the periphery of the recess 11a to the lower surface, and the metallized wiring for connecting each electrode of the semiconductor element 10 to an external electric circuit. It is composed of an external lead terminal 13 attached to the layer 12 via a brazing material such as silver solder, and a lid 14, and the semiconductor element is provided on the bottom surface of the recess 11a of the insulating base 11.
10 is adhered and fixed through an adhesive such as glass, resin, or a brazing material, and each electrode is electrically connected to the metallized wiring layer 12 through a bonding wire 15, and thereafter, a lid is provided on the upper surface of the insulating base 11. A semiconductor device is obtained as a product by bonding 14 together with a sealing material such as glass, resin, a brazing material, etc., and hermetically sealing the semiconductor element 10 inside a container composed of the insulating base 11 and the lid 14.

【0003】尚、かかる従来の半導体素子収納用パッケ
ージは絶縁基体11の上面に内部に収容される半導体素子
10の電源電極及び接地電極に接続される接続パッド16が
形成されており、該接続パッドにチタン酸バリウム磁器
を誘電体とした容量素子17が半田等のロウ材やエポキシ
樹脂に銀粉末を充填して成る導電性接着剤を介して直接
取着され、半導体素子10の電源電極と接地電極の間に容
量素子を接続することによって半導体素子10への電源ノ
イズの悪影響を有効に防止するようになっている。
Incidentally, such a conventional semiconductor element housing package is a semiconductor element housed inside the upper surface of the insulating base 11.
A connection pad 16 connected to the power supply electrode 10 and the ground electrode 10 is formed, and a capacitive element 17 having a barium titanate porcelain as a dielectric is filled in the connection pad with a brazing material such as solder or an epoxy resin filled with silver powder. Directly attached via a conductive adhesive formed by, and by connecting a capacitive element between the power electrode and the ground electrode of the semiconductor element 10 to effectively prevent the adverse effect of power noise to the semiconductor element 10. Has become.

【0004】しかしながら、この従来の半導体素子収納
用パッケージは半導体素子10を収容する絶縁基体11が酸
化アルミニウム質焼結体から成り、その熱伝導率が15W/
m ・K と低いこと及び近時、半導体素子10は高密度化、
高集積化が急激に進み、半導体素子10の単位面積、単位
体積当たりの発熱量が増大してきたこと等から絶縁基体
11の凹部11a 内に半導体素子10を収容し、半導体装置と
なした後、半導体素子10を作動させると半導体素子10が
該素子10自身の発する熱膨張係数によって高温となり、
半導体素子10に熱破壊を起こさせたり、特性に熱変化を
来し、誤動作させるという欠点を有していた。
However, in this conventional semiconductor element housing package, the insulating substrate 11 for housing the semiconductor element 10 is made of an aluminum oxide sintered body, and its thermal conductivity is 15 W /
It is as low as m · K, and recently, the semiconductor element 10 has a higher density,
Due to the rapid progress of high integration, the amount of heat generated per unit area and unit volume of the semiconductor element 10 has increased.
After the semiconductor element 10 is housed in the recess 11a of 11 to form a semiconductor device, when the semiconductor element 10 is operated, the semiconductor element 10 has a high temperature due to the thermal expansion coefficient of the element 10 itself,
The semiconductor element 10 has the drawback of causing thermal breakdown or causing a thermal change in its characteristics to cause a malfunction.

【0005】そこで上記欠点を解消するために絶縁基体
11を酸化アルミニウム質焼結体に変えて熱伝導率が50W/
m ・K 以上と極めて熱を伝えやすい窒化アルミニウム質
焼結体で形成し、半導体素子10の発する熱を絶縁基体11
を介して大気中に良好に放散させることが考えられる。
Therefore, in order to solve the above-mentioned drawbacks, an insulating substrate
11 is replaced with aluminum oxide sintered body and the thermal conductivity is 50 W /
The heat generated by the semiconductor element 10 is formed by an aluminum nitride sintered body that is extremely easy to transfer heat at m.
It is thought that it can be satisfactorily diffused into the atmosphere via.

【0006】[0006]

【発明が解決しようとする課題】しかしながら、窒化ア
ルミニウム質焼結体で絶縁基体11を形成した場合、窒化
アルミニウム質焼結体の熱膨張係数は4 〜5 ×10-6/ ℃
であり、容量素子17を構成するチタン酸バリウム磁器の
熱膨張係数(10 〜11×10-6/ ℃) と大きく相違するため
半導体素子10の作動時に発する熱が絶縁基体11と容量素
子17との接合部に印加されると両者の接合部に両者の熱
膨張係数の相違に起因する大きな熱応力が発生し、その
結果、前記熱応力によって容量素子17が絶縁基体11上面
より外れ、容量素子17によって半導体素子10への電源ノ
イズの悪影響を有効に防止することができなくなるとい
う欠点を誘発した。
However, when the insulating substrate 11 is formed of an aluminum nitride sintered body, the thermal expansion coefficient of the aluminum nitride sintered body is 4 to 5 × 10 -6 / ° C.
The thermal expansion coefficient of the barium titanate porcelain that constitutes the capacitive element 17 (10 to 11 × 10 -6 / ° C.) is greatly different from the heat generated during the operation of the semiconductor element 10 between the insulating substrate 11 and the capacitive element 17. When applied to the joint portion of, a large thermal stress is generated in the joint portion due to the difference in thermal expansion coefficient between the two, and as a result, the thermal element causes the capacitive element 17 to deviate from the upper surface of the insulating substrate 11, 17 has caused a drawback that the adverse effect of power supply noise on the semiconductor element 10 cannot be effectively prevented.

【0007】[0007]

【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は半導体素子への熱の影響及び電源ノイ
ズの影響を有効に防止し、半導体素子を長期間にわたり
正常、且つ安定に作動させることができる半導体素子収
納用パッケージを提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and its purpose is to effectively prevent the influence of heat and power supply noise on a semiconductor element, and to keep the semiconductor element normal for a long period of time, and An object of the present invention is to provide a package for accommodating semiconductor devices, which can be operated stably.

【0008】[0008]

【課題を解決するための手段】本発明は内部に半導体素
子を収容するための空所を有する窒化アルミニウム質焼
結体から成る絶縁容器に、内部に収容する半導体素子の
電源電極及び接地電極に接続される接続パッドを形成す
るとともに該接続パッドに容量素子を取着して成る半導
体素子収納用パッケージであって、前記絶縁容器に形成
された接続パッドと容量素子との間に酸化アルミニウム
質焼結体から成る板部材が介在していることを特徴とす
るものである。
SUMMARY OF THE INVENTION The present invention provides an insulating container made of an aluminum nitride sintered body having a cavity for accommodating a semiconductor element therein, and a power supply electrode and a ground electrode of the semiconductor element accommodated therein. What is claimed is: 1. A package for storing a semiconductor element, comprising a connection pad to be connected and a capacitance element attached to the connection pad, wherein an aluminum oxide burnt material is provided between the connection pad and the capacitance element formed in the insulating container. It is characterized in that a plate member made of a unit is interposed.

【0009】[0009]

【作用】本発明の半導体素子収納用パッケージによれ
ば、絶縁容器を窒化アルミニウム質焼結体で形成したこ
とから半導体素子の作動時に発する熱は容器を介して大
気中に良好に放散され、その結果、容器内部に収容され
る半導体素子は常に低温となり、半導体素子を長期間に
わたり正常、且つ安定に作動させることができる。
According to the package for accommodating a semiconductor element of the present invention, since the insulating container is made of the aluminum nitride sintered body, the heat generated during the operation of the semiconductor device is well dissipated into the atmosphere through the container. As a result, the semiconductor element housed inside the container is always at a low temperature, and the semiconductor element can be operated normally and stably for a long period of time.

【0010】また絶縁容器に設けた接続パッドに容量素
子を、間に熱膨張係数が絶縁容器と容量素子の熱膨張係
数に対し中間値である酸化アルミニウム質焼結体から成
る板部材を介在させて取着したことから絶縁容器と容量
素子との間には大きな熱応力が発生することはなく、そ
の結果、絶縁容器に容量素子が強固に取着され、該容量
素子によって半導体素子への電源ノイズの悪影響が有効
に防止される。
Further, the capacitive element is interposed between the connection pads provided on the insulating container, and the plate member made of an aluminum oxide sintered body having a thermal expansion coefficient intermediate between the thermal expansion coefficient of the insulating container and the thermal expansion coefficient of the capacitive element is interposed therebetween. Since a large thermal stress is not generated between the insulating container and the capacitive element due to the attachment, the capacitive element is firmly attached to the insulating container, and the capacitive element supplies power to the semiconductor element. The adverse effects of noise are effectively prevented.

【0011】[0011]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。
The present invention will now be described in detail with reference to the accompanying drawings.

【0012】図1 及び図2 は本発明の半導体素子収納用
パッケージの一実施例を示し、1 は絶縁基体、2 は蓋体
である。この絶縁基体1 と蓋体2 とで半導体素子3 を収
容するための容器4 が構成される。前記絶縁基体1 は窒
化アルミニウム質焼結体から成り、その上面に半導体素
子3を収容する空所を形成するための凹部1aを有し、該
凹部1a底面には半導体素子3 がガラス、樹脂、ロウ材等
の接着剤を介して接着固定される。
1 and 2 show an embodiment of a package for housing a semiconductor device according to the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 form a container 4 for housing the semiconductor element 3. The insulating substrate 1 is made of an aluminum nitride sintered body, and has a concave portion 1a for forming a space for accommodating the semiconductor element 3 on the upper surface thereof, and the semiconductor element 3 is made of glass, resin or the like on the bottom surface of the concave portion 1a. It is adhesively fixed through an adhesive such as a brazing material.

【0013】前記窒化アルミニウム質焼結体から成る絶
縁基体1 は例えば、窒化アルミニウム(AlN) 、イットリ
ア(Y2 O 3 ) 、カルシア(CaO) 、マグネシア(MgO) 等の
原料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状
となすとともにこれを従来周知のドクターブレード法や
カンレンダーロール法等を採用することによってセラミ
ックグリーンシート( セラミック生シート) を得、しか
る後、前記セラミックグリーンシートに適当な打ち抜き
加工を施すとともに複数枚積層し、高温( 約1800℃) で
焼成することによって製作される。
The insulating substrate 1 made of the aluminum nitride sintered body is, for example, an organic solvent suitable for a raw material powder such as aluminum nitride (AlN), yttria (Y 2 O 3 ), calcia (CaO), magnesia (MgO). A ceramic green sheet (ceramic green sheet) is obtained by adding and mixing a solvent to form a slurry, and adopting the conventionally known doctor blade method, canender roll method, etc. It is manufactured by performing appropriate punching, stacking multiple sheets, and baking at high temperature (about 1800 ℃).

【0014】前記窒化アルミニウム質焼結体から成る絶
縁基体1 はその熱伝導率が50W/m ・K 以上であり、熱を
伝え易いことから半導体素子3 が作動時に多量の熱を発
生したとしてもその熱は絶縁基体1 を介して大気中に良
好に放散され、その結果、半導体素子3 は該素子3 自身
の発する熱によって高温になることは一切なく、半導体
素子3 に熱破壊や特性に熱変化を来し、誤動作を起こさ
せることはなくなる。
Since the insulating substrate 1 made of the aluminum nitride sintered body has a thermal conductivity of 50 W / m · K or more and is easy to transfer heat, even if the semiconductor element 3 generates a large amount of heat during operation. The heat is satisfactorily dissipated into the atmosphere through the insulating substrate 1, and as a result, the semiconductor element 3 never rises in temperature due to the heat generated by the element 3 itself, and the semiconductor element 3 is not destroyed by thermal destruction or characteristics. It will not change and cause malfunctions.

【0015】また前記絶縁基体1 は凹部1a周辺から下面
にかけて複数個のメタライズ配線層5 が被着形成されて
おり、該メタライズ配線層5 の凹部1a周辺部には半導体
素子3 の各電極( 電源電極、接地電極、信号電極) がボ
ンディングワイヤ6 を介して電気的に接続され、また絶
縁基体1 の下面に導出された部位には外部電気回路と接
続される外部リード端子7 が銀ロウ等のロウ材を介して
取着されている。
A plurality of metallized wiring layers 5 are deposited on the insulating substrate 1 from the periphery of the recess 1a to the lower surface, and the electrodes of the semiconductor element 3 (power supply) are formed in the periphery of the recess 1a of the metallized wiring layer 5. (Electrode, ground electrode, signal electrode) are electrically connected via the bonding wire 6, and the external lead terminal 7 connected to an external electric circuit is connected to an external electric circuit at a portion led out to the lower surface of the insulating substrate 1. It is attached via brazing material.

【0016】前記メタライズ配線層5 はタングステン、
モリブデン、マンガン等の高融点金属粉末から成り、該
タングステン等の高融点金属粉末に適当な有機溶剤、溶
媒を添加混合して得た金属ペーストを絶縁基体1 となる
セラミックグリーンシートに予め従来周知のスクリーン
印刷法により所定パターンに印刷塗布しておくことによ
って絶縁基体1 の凹部1a周辺から下面にかけて被着され
る。
The metallized wiring layer 5 is made of tungsten,
A metal paste made of a refractory metal powder such as molybdenum or manganese, which is obtained by adding and mixing an appropriate organic solvent or a solvent to the refractory metal powder such as tungsten is previously known to the ceramic green sheet serving as the insulating substrate 1. By printing and applying a predetermined pattern by the screen printing method, the insulating substrate 1 is deposited from around the recess 1a to the lower surface.

【0017】尚、前記メタライズ配線層5 はその露出表
面にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ
性の良い金属をメッキ法により1.0 乃至20.0μm の厚み
に層着させておくとメタライズ配線層5 の酸化腐食を有
効に防止することができるとともにメタライズ配線層5
とボンディングワイヤ6 との接続及びメタライズ配線層
5 への外部リード端子の取着を強固となすことができ
る。従って、メタライズ配線層5 の酸化腐食を防止し、
メタライズ配線層5 とボンディングワイヤ6 及び外部リ
ード端子7 との取着を強固とするにはメタライズ配線層
5 の露出表面にニッケル、金等を1.0 乃至20.0μm の厚
みに層着させておくことが好ましい。
The metallized wiring layer 5 is formed by depositing a metal such as nickel and gold, which has excellent corrosion resistance and has a good wettability with a brazing material, on the exposed surface by plating to a thickness of 1.0 to 20.0 μm. The metallized wiring layer 5 can be effectively prevented from being oxidized and corroded.
And bonding wire 6 and metallized wiring layer
It is possible to firmly attach the external lead terminal to 5. Therefore, the oxidation corrosion of the metallized wiring layer 5 is prevented,
To strengthen the attachment of the metallized wiring layer 5 to the bonding wires 6 and the external lead terminals 7, the metallized wiring layer
It is preferable to deposit nickel, gold or the like on the exposed surface of layer 5 in a thickness of 1.0 to 20.0 μm.

【0018】また前記メタライズ配線層5 に銀ロウ等の
ロウ材を介して取着される外部リード端子7 はコバール
金属( 鉄ーニッケルーコバルト合金) や42アロイ( 鉄ー
ニッケル合金) 等の金属材料から成り、外部リード端子
7 を外部電気回路に接続することによって絶縁基体1 の
凹部1a内に収容される半導体素子3 の各電極はメタライ
ズ配線層5 及び外部リード端子7 を介して外部電気回路
に電気的に接続されることとなる。
The external lead terminals 7 attached to the metallized wiring layer 5 via a brazing material such as silver braze are metal materials such as Kovar metal (iron-nickel-cobalt alloy) and 42 alloy (iron-nickel alloy). Consisting of an external lead terminal
Each electrode of the semiconductor element 3 housed in the recess 1a of the insulating substrate 1 by connecting 7 to the external electric circuit is electrically connected to the external electric circuit via the metallized wiring layer 5 and the external lead terminal 7. It will be.

【0019】前記外部リード端子7 はコバール金属等の
インゴット( 塊) を圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用することによって所定の形状
に形成される。
The external lead terminal 7 is formed in a predetermined shape by adopting a conventionally known metal working method such as a rolling working method or a punching working method for an ingot (lump) of Kovar metal or the like.

【0020】また前記外部リード端子7 はその露出表面
にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ性
の良い金属をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくと外部リード端子7 の酸化腐食を有効に
防止することができるとともに外部リード端子7 を半田
等のロウ材を介し外部電気回路に強固に接続することが
可能となる。従って、前記外部リード端子7 はその露出
表面にニッケル、金等を1.0 乃至20.0μm の厚みに層着
させておくことが好ましい。
Further, when the external lead terminal 7 is formed by depositing a metal such as nickel or gold, which has excellent corrosion resistance and has good wettability with the brazing material, to a thickness of 1.0 to 20.0 μm by plating. Oxidation and corrosion of the external lead terminals 7 can be effectively prevented, and the external lead terminals 7 can be firmly connected to an external electric circuit via a brazing material such as solder. Therefore, it is preferable that the exposed surface of the external lead terminal 7 is layered with nickel, gold or the like in a thickness of 1.0 to 20.0 μm.

【0021】前記絶縁基体1 はまたその上面に内部に収
容する半導体素子3 の電源電極及び接地電極に接続され
る接続パッド5aが形成されており、該接続パッド5aには
図2に示すように容量素子8 が間に酸化アルミニウム質
焼結体から成る板部材9 を挟んだ状態で半田や導電性樹
脂により取着されている。
The insulating substrate 1 also has on its upper surface a connection pad 5a connected to the power supply electrode and the ground electrode of the semiconductor element 3 housed therein, and the connection pad 5a is formed as shown in FIG. The capacitive element 8 is attached with solder or a conductive resin with a plate member 9 made of an aluminum oxide sintered body sandwiched therebetween.

【0022】前記接続パッド5aは容量素子8 を絶縁基体
1 上面に取着させるための下地部材として作用するとと
もに容量素子8 を半導体素子3 の電源電極と接地電極の
間に接続させる作用を為し、タングステン、モリブデ
ン、マンガン等の高融点金属粉末により形成されてい
る。
The connection pad 5a serves as an insulating base for the capacitive element 8.
1 It acts as a base member for attachment to the upper surface and also acts to connect the capacitive element 8 between the power supply electrode and the ground electrode of the semiconductor element 3, and is made of a refractory metal powder such as tungsten, molybdenum, or manganese. Has been done.

【0023】尚、前記接続パッド5aはメタライズ配線層
5 と同様の方法によって絶縁基体1の上面に所定形状に
形成される。
The connection pad 5a is a metallized wiring layer.
A predetermined shape is formed on the upper surface of the insulating substrate 1 by the same method as in 5.

【0024】また前記接続パッド5aに取着される容量素
子8 は例えば、チタン酸バリウム磁器内に対向電極を多
数埋設して形成され、該容量素子8 は半導体素子3 の誤
動作の原因となる供給電源電圧の変動に起因する電源ノ
イズを除去する作用を為し、これによって半導体素子3
は電源ノイズの悪影響から保護され、長期間にわたり正
常、且つ安定に作動することが可能となる。
The capacitive element 8 attached to the connection pad 5a is formed, for example, by embedding a large number of counter electrodes in a barium titanate porcelain, and the capacitive element 8 is a supply source that causes a malfunction of the semiconductor element 3. It acts to eliminate power supply noise caused by fluctuations in the power supply voltage, which allows the semiconductor element 3
Is protected from the adverse effects of power supply noise and can operate normally and stably for a long period of time.

【0025】前記絶縁基体1 に設けた接続パッド5aと容
量素子8 との間には更に絶縁基体1の熱膨張係数(4〜5
×10-6/ ℃) と容量素子8 の熱膨張係数(10 〜11×10-6
/ ℃) に対し、中間の熱膨張係数(7×10-6/ ℃) を有す
る酸化アルミニウム質焼結体から成る板部材9 が介在さ
れており、該板部材9 は絶縁基体1 と容量素子8 との間
に両者の熱膨張係数の相違に起因して発生する熱応力を
緩和する作用を為し、これによって絶縁基体1 に容量素
子8 が強固に取着されることとなり、容量素子8 によっ
て半導体素子3 への電源ノイズの悪影響が有効に防止さ
れることとなる。
A thermal expansion coefficient (4 to 5) of the insulating base 1 is further provided between the connection pad 5a provided on the insulating base 1 and the capacitive element 8.
× 10 -6 / ℃) and the thermal expansion coefficient of the capacitive element 8 (10 ~ 11 × 10 -6
/ ° C), a plate member 9 made of an aluminum oxide sintered body having an intermediate coefficient of thermal expansion (7 × 10 -6 / ° C) is interposed, and the plate member 9 is an insulating substrate 1 and a capacitive element. 8 and 8 has the effect of alleviating the thermal stress caused by the difference in the thermal expansion coefficient between the two, and by this, the capacitive element 8 is firmly attached to the insulating substrate 1, and the capacitive element 8 As a result, the adverse effect of power supply noise on the semiconductor element 3 is effectively prevented.

【0026】前記板部材9 は酸化アルミニウム(Al 2 O
3 ) 、シリカ(SiO2 ) 、カルシア(CaO) 、マグネシア(M
gO) 等に適当な有機溶剤、溶媒を添加混合して原料粉末
を調整し、次に前記原料粉末を所定金型内に充填すると
ともに一定圧力で押圧して生成形体を形成し、しかる
後、前記生成形体を約1600℃の温度で焼成することによ
って製作される。
The plate member 9 is made of aluminum oxide (Al 2 O
3 ), silica (SiO 2 ), calcia (CaO), magnesia (M
(gO) etc. a suitable organic solvent, a solvent is added and mixed to prepare a raw material powder, and then the raw material powder is filled in a predetermined mold and pressed at a constant pressure to form a green body, and thereafter, It is manufactured by firing the green body at a temperature of about 1600 ° C.

【0027】また前記酸化アルミニウム質焼結体から成
る板部材9 はその上面から下面にかけてメタライズ金属
層9aが被着されており、該メタライズ金属層9aは容量素
子8の各電極を半導体素子3 の電源電極及び接地電極が
接続されている接続パッド5aに電気的に接続させる作用
を為す。
Further, the plate member 9 made of the aluminum oxide sintered body is covered with a metallized metal layer 9a from the upper surface to the lower surface thereof, and the metallized metal layer 9a connects each electrode of the capacitor element 8 to the semiconductor element 3 It serves to electrically connect to the connection pad 5a to which the power supply electrode and the ground electrode are connected.

【0028】尚、前記板部材9 のメタライズ金属層9aは
タングステン、モリブデン等から成り、タングステン等
の粉末に適当な有機溶剤、溶媒を添加混合して得た金属
ペーストを板部材9 となる生成形体に予め所定形状に塗
布しておくことによって板部材9 の上面から下面にかけ
て被着される。
The metallized metal layer 9a of the plate member 9 is made of tungsten, molybdenum or the like, and a metal paste obtained by adding and mixing a powder of tungsten or the like with an appropriate organic solvent or solvent is used as the plate member 9. It is applied from the upper surface to the lower surface of the plate member 9 by applying it in a predetermined shape in advance.

【0029】また前記酸化アルミニウム質焼結体から成
る板部材9 を間に介在しての絶縁基体1 上への容量素子
8 の取着は絶縁基体1 に設けた接続パッド5a上に板部材
9 及び容量素子8 を順次、各々の間に半田や導電性接着
剤を挟んで載置させ、しかる後、接続パッド5aと板部材
9 との間及び板部材9 と容量素子8 との間に挟まれてい
る半田や導電性接着剤を加熱溶融、或いは熱硬化させる
ことによって行われる。この場合、板部材9 の熱膨張係
数が接続パッド5aの被着されている窒化アルミニウム質
焼結体1 の熱膨張係数と容量素子8 の熱膨張係数の中間
値であることから絶縁基体1 と板部材9 との間及び板部
材9 と容量素子8 との間には大きな熱応力が発生するこ
とはなく、結果として容量素子9 を絶縁基体1 の接続パ
ッド5aに極めて強固に取着することが可能となる。
Further, the capacitive element on the insulating substrate 1 with the plate member 9 made of the aluminum oxide sintered body interposed therebetween
8 is attached by a plate member on the connection pad 5a provided on the insulating substrate 1.
9 and the capacitive element 8 are placed one after another with solder or a conductive adhesive sandwiched between them, and then the connection pad 5a and the plate member.
9 and the plate member 9 and the capacitive element 8 are sandwiched between the solder and the conductive adhesive by heating, melting, or thermosetting. In this case, since the thermal expansion coefficient of the plate member 9 is an intermediate value between the thermal expansion coefficient of the aluminum nitride sintered body 1 to which the connection pad 5a is adhered and the thermal expansion coefficient of the capacitor element 8, No large thermal stress is generated between the plate member 9 and between the plate member 9 and the capacitive element 8, and as a result, the capacitive element 9 is extremely firmly attached to the connection pad 5a of the insulating base 1. Is possible.

【0030】かくして本発明の半導体素子収納用パッケ
ージによれば絶縁基体1 の凹部1a底面に半導体素子3 を
ガラス、樹脂、ロウ材等の接着剤を介して接着固定する
とともに半導体素子3 の各電極をメタライズ配線層5 に
ボンディングワイヤ6 を介して電気的に接続し、しかる
後、絶縁基体1 の上面に蓋体2 をガラス、樹脂、ロウ材
等から成る封止材を介して接合させ、絶縁基体1 と蓋体
2 とから成る容器4 内部に半導体素子3 を気密に収容す
ることによって製品としての半導体装置が完成する。
Thus, according to the semiconductor element housing package of the present invention, the semiconductor element 3 is adhered and fixed to the bottom surface of the concave portion 1a of the insulating substrate 1 through an adhesive such as glass, resin, or brazing material, and each electrode of the semiconductor element 3 is attached. Are electrically connected to the metallized wiring layer 5 via bonding wires 6, and then the lid 2 is bonded to the upper surface of the insulating substrate 1 via a sealing material made of glass, resin, brazing material, etc. Base 1 and lid
A semiconductor device as a product is completed by hermetically housing the semiconductor element 3 in a container 4 composed of 2 and.

【0031】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the gist of the present invention.

【0032】[0032]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば絶縁容器を窒化アルミニウム質焼結体で形成した
ことから半導体素子の作動時に発する熱は容器を介して
大気中に良好に放散され、その結果、容器内部に収容さ
れる半導体素子は常に低温となり、半導体素子を長期間
にわたり正常、且つ安定に作動させることができる。
According to the package for accommodating semiconductor elements of the present invention, since the insulating container is made of the aluminum nitride sintered material, the heat generated during the operation of the semiconductor element is radiated well into the atmosphere through the container, As a result, the temperature of the semiconductor element housed inside the container is always low, and the semiconductor element can be operated normally and stably for a long period of time.

【0033】また絶縁容器に設けた接続パッドに容量素
子を、間に熱膨張係数が絶縁容器と容量素子の熱膨張係
数に対し中間値である酸化アルミニウム質焼結体から成
る板部材を介在させて取着したことから絶縁容器と容量
素子との間には大きな熱応力が発生することはなく、そ
の結果、絶縁容器に容量素子が強固に取着され、該容量
素子によって半導体素子への電源ノイズの悪影響が有効
に防止される。
Further, the capacitive element is interposed between the connection pads provided in the insulating container, and the plate member made of an aluminum oxide sintered body having a thermal expansion coefficient intermediate between the thermal expansion coefficient of the insulating container and the thermal expansion coefficient of the capacitive element is interposed therebetween. Since a large thermal stress is not generated between the insulating container and the capacitive element due to the attachment, the capacitive element is firmly attached to the insulating container, and the capacitive element supplies power to the semiconductor element. The adverse effects of noise are effectively prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【図2】図1に示すパッケージの要部拡大断面図であ
る。
FIG. 2 is an enlarged cross-sectional view of a main part of the package shown in FIG.

【図3】従来の半導体素子収納用パッケージの断面図で
ある。
FIG. 3 is a cross-sectional view of a conventional semiconductor element housing package.

【符号の説明】[Explanation of symbols]

1・・・・絶縁基体 2・・・・蓋体 3・・・・半導体素子 4・・・・容器 5・・・・メタライズ配線層 7・・・・外部リード端子 8・・・・容量素子 9・・・・板部材 1 ... Insulating substrate 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Metallized wiring layer 7 ... External lead terminal 8 ... Capacitance element 9 ... Plate member

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】内部に半導体素子を収容するための空所を
有する窒化アルミニウム質焼結体から成る絶縁容器に、
内部に収容する半導体素子の電源電極及び接地電極に接
続される接続パッドを形成するとともに該接続パッドに
容量素子を取着して成る半導体素子収納用パッケージで
あって、前記絶縁容器に形成された接続パッドと容量素
子との間に酸化アルミニウム質焼結体から成る板部材が
介在していることを特徴とする半導体素子収納用パッケ
ージ。
1. An insulating container made of an aluminum nitride sintered body having a cavity for housing a semiconductor element therein.
A package for storing a semiconductor element, which is formed by forming a connection pad connected to a power supply electrode and a ground electrode of a semiconductor element housed inside and attaching a capacitive element to the connection pad, the package being formed in the insulating container. A package for accommodating a semiconductor element, characterized in that a plate member made of an aluminum oxide sintered body is interposed between the connection pad and the capacitive element.
JP5022665A 1993-02-10 1993-02-10 Package for semiconductor-element housing Pending JPH06236938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5022665A JPH06236938A (en) 1993-02-10 1993-02-10 Package for semiconductor-element housing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5022665A JPH06236938A (en) 1993-02-10 1993-02-10 Package for semiconductor-element housing

Publications (1)

Publication Number Publication Date
JPH06236938A true JPH06236938A (en) 1994-08-23

Family

ID=12089151

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5022665A Pending JPH06236938A (en) 1993-02-10 1993-02-10 Package for semiconductor-element housing

Country Status (1)

Country Link
JP (1) JPH06236938A (en)

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