JPH05144953A - Electronic component containing package - Google Patents
Electronic component containing packageInfo
- Publication number
- JPH05144953A JPH05144953A JP3301758A JP30175891A JPH05144953A JP H05144953 A JPH05144953 A JP H05144953A JP 3301758 A JP3301758 A JP 3301758A JP 30175891 A JP30175891 A JP 30175891A JP H05144953 A JPH05144953 A JP H05144953A
- Authority
- JP
- Japan
- Prior art keywords
- electronic component
- lid
- signal line
- ground
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/162—Disposition
- H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、電子部品を収容するた
めの電子部品収納用パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component storage package for storing electronic components.
【０００２】[0002]
【従来の技術及びその課題】従来の電子部品収納用パッ
ケージは、内部に電源線、グランド線、信号線を有し、
且つ上面に電子部品を搭載するための搭載部を有するア
ルミナセラミックス等の電気絶縁材料より成る基体と、
同じくアルミナセラミックス等の電気絶縁材料より成
り、前記基体の搭載部に搭載される半導体素子等の電子
部品を収容する空所を形成するための凹部を有する蓋体
とから構成されており、基体の搭載部に半導体素子等の
電子部品を搭載固定するとともに該電子部品の各端子を
基体に設けた電源線、グランド線、信号線にボンディン
グワイヤを介し電気的に接続し、しかる後、基体上に蓋
体を内部に電子部品を収容するようにして封止材により
接合させ、これによって最終製品としての電子装置が完
成する。2. Description of the Related Art A conventional electronic component storing package has a power line, a ground line, and a signal line inside,
And a base made of an electrically insulating material such as alumina ceramics having a mounting portion for mounting an electronic component on the upper surface,
Similarly, it is made of an electrically insulating material such as alumina ceramics, and is composed of a lid body having a recess for forming a space for accommodating an electronic component such as a semiconductor element mounted on the mounting portion of the base body. An electronic component such as a semiconductor element is mounted and fixed to the mounting portion, and each terminal of the electronic component is electrically connected to a power supply line, a ground line, and a signal line provided on the base through bonding wires, and then, on the base. The lid body is bonded with a sealing material so as to accommodate the electronic components inside, and thus an electronic device as a final product is completed.
【０００３】しかしながら、従来、基体や蓋体に使用さ
れているアルミナセラミックスはノイズに対するシール
ド効果が低いこと、及び近時、半導体素子等の電子部品
は高速駆動が行われるようになってきており、ノイズの
影響を極めて受け易いものとなってきていること等から
外部近接位置にノイズ発生源があると内部に収容する半
導体素子等の電子部品や基体に設けた信号線にノイズが
極めて容易に入り込み、その結果、前記入り込んだノイ
ズによって半導体素子等の電子部品に誤動作を発生させ
てしまうという欠点を有していた。However, the alumina ceramics conventionally used for the base and lid have a low noise shielding effect, and in recent years, electronic parts such as semiconductor elements have been driven at high speed. Since it is becoming very susceptible to noise, if a noise source is located near an external location, noise easily enters the electronic components such as semiconductor elements housed inside or the signal lines provided on the base body. As a result, there is a drawback in that the introduced noise causes malfunctions in electronic components such as semiconductor elements.
【０００４】また高速駆動を行う電子部品はそれ自体が
ノイズを発生し易く、電子部品が発生したノイズは他の
装置に入り込んで誤動作等の悪影響を与えるという問題
も有していた。Further, the electronic parts which are driven at a high speed are apt to generate noises themselves, and the noises generated by the electronic parts have a problem that they enter other devices and have a bad influence such as malfunction.
【０００５】[0005]
【発明の目的】本発明は上記欠点に鑑み案出されたもの
でその目的は、内部に収容する電子部品と基板の信号線
とを外部から完全にシールドし、内部に収容する電子部
品を正常、且つ安定に作動させることができる電子部品
収納用パッケージを提供することにある。SUMMARY OF THE INVENTION The present invention has been conceived in view of the above-mentioned drawbacks, and an object thereof is to completely shield an electronic component housed inside and a signal line of a substrate from the outside so that an electronic component housed inside can be normally operated. It is another object of the present invention to provide a package for storing electronic components that can be stably operated.
【０００６】[0006]
【課題を解決するための手段】本発明は、信号線、グラ
ンド線を有し、且つ電子部品を搭載するための搭載部を
有する基体上に、該搭載部に搭載される電子部品を内部
に収容するように凹部を有する椀状の蓋体を金属製封止
材を介して取着する電子部品収納用パッケージであっ
て、前記基体の信号線をグランド線で挟むとともに椀状
蓋体の凹部内壁に金属層を被着させ、且つ前記基体のグ
ランド線と蓋体の金属層とを金属製封止材で電気的に接
続させたことを特徴とするものである。SUMMARY OF THE INVENTION According to the present invention, an electronic component to be mounted on the mounting portion is internally provided on a base having a signal line, a ground line and a mounting portion for mounting the electronic component. A package for storing electronic parts, wherein a bowl-shaped lid body having a recessed portion to be accommodated is attached via a metallic sealing material, wherein the signal line of the base body is sandwiched by a ground line and a recessed portion of the bowl-shaped lid body is provided. A metal layer is deposited on the inner wall, and the ground wire of the base body and the metal layer of the lid are electrically connected by a metal sealing material.
【０００７】[0007]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図１は本発明の電子部品収納用パッケージとして半
導体素子を収容する半導体素子収納用パッケージを例に
示す断面図であり、半導体素子収納用パッケージ１は、
主に、基体２と蓋体３とから構成されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing an example of a semiconductor element housing package for housing a semiconductor element as an electronic component housing package of the present invention.
It is mainly composed of a base body 2 and a lid body 3.
【０００８】前記基体２は、概ね四角形の板状の部材で
あり、酸化アルミニウム質焼結体、ムライト質焼結体、
窒化アルミニウム質焼結体、炭化珪素質焼結体等の電気
絶縁材料で構成されている。The base body 2 is a substantially rectangular plate-shaped member, and is made of an aluminum oxide sintered body, a mullite sintered body,
It is made of an electrically insulating material such as an aluminum nitride sintered body or a silicon carbide sintered body.
【０００９】また前記基体２の上面中央部には半導体素
子４を搭載する搭載部Ａが形成されており、該搭載部Ａ
には半導体素子４が接着剤を介して取着固定されてい
る。A mounting portion A for mounting the semiconductor element 4 is formed in the center of the upper surface of the base body 2.
The semiconductor element 4 is attached and fixed to the semiconductor device via an adhesive.
【００１０】尚、前記基体２は例えば、酸化アルミニウ
ム質焼結体から成る場合、アルミナ(Al 2 0 3 ) 、シリ
カ(SiO2 ) 、カルシア(CaO) 、マグネシア(MgO) 等の原
料粉末に適当なバインダー、有機溶媒を添加混合して泥
漿状となすとともにこれを従来周知のドクターブレード
法を採用することによってセラミックグリーンシート(
セラミック生シート) を得、しかる後、前記セラミック
グリーンシートに適当な打ち抜き加工を施すとともにこ
れを複数枚積層し、高温( 約1600℃) の温度で焼成する
ことによって製作される。When the base 2 is made of, for example, an aluminum oxide sintered body, it is suitable as a raw material powder of alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), magnesia (MgO), or the like. Ceramic green sheet (by adding a binder and an organic solvent to form a slurry and adopting the well-known doctor blade method)
A ceramic green sheet) is obtained, and thereafter, the ceramic green sheet is appropriately punched, and a plurality of the green sheets are laminated and fired at a high temperature (about 1600 ° C.).
【００１１】また、前記基体２はその内部及び上下面に
信号線5a及びグランド線5bが被着形成されており、該信
号線5a及びグランド線5bの基体2 上面部に導出する部位
には半導体素子4 の各電極がボンディングワイヤ6 を介
して電気的に接続され、また基体2 の下面部に導出する
部位には外部リードピン7 が銀ロウ等のロウ材を介し取
着されている。The base 2 has a signal line 5a and a ground line 5b adhered to the inside and upper and lower surfaces thereof, and a semiconductor is provided at a portion of the signal line 5a and the ground line 5b leading to the upper surface of the base 2. Each electrode of the element 4 is electrically connected via a bonding wire 6, and an external lead pin 7 is attached to a portion leading to the lower surface of the base 2 via a brazing material such as silver brazing.
【００１２】前記信号線5a及びグランド線5bは半導体素
子4の各電極( 信号電極及び電源グランド電極等) を外
部電気回路と接続される外部リードピン7 に電気的に接
続させる作用を為し、該信号線5a及びグランド線5bは、
タングステン(W) 、モリブデン(Mo)、マンガン(Mn)等の
高融点金属粉末により形成されている。The signal line 5a and the ground line 5b serve to electrically connect each electrode (signal electrode, power supply ground electrode, etc.) of the semiconductor element 4 to an external lead pin 7 connected to an external electric circuit. The signal line 5a and the ground line 5b are
It is formed of a refractory metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn).
【００１３】前記信号線5a及びグランド線5bは具体的に
はタングステン等の高融点金属粉末に適当な有機溶剤、
溶媒を添加混合して得た金属ペーストを基体2 となるセ
ラミックグリーンシートの表面に予め従来周知のスクリ
ーン印刷法等の厚膜手法を採用して印刷塗布しておくこ
とによって基体2 の内部及び上下面に被着形成される。The signal line 5a and the ground line 5b are specifically an organic solvent suitable for refractory metal powder such as tungsten,
The metal paste obtained by adding and mixing the solvent is applied to the surface of the ceramic green sheet to be the base 2 by applying it in advance by using a thick film method such as the well-known screen printing method in advance. It is adhered and formed on the lower surface.
【００１４】また信号線5a及びグランド線5bに取着され
る外部リードピン7 は内部に収容する半導体素子4 の各
電極を外部電気回路に電気的に接続する作用を為し、コ
バール金属(Fe-Ni-Co 合金) や42アロイ(Fe-Ni合金) 等
の金属を棒状に加工したものが使用される。The external lead pins 7 attached to the signal line 5a and the ground line 5b serve to electrically connect the respective electrodes of the semiconductor element 4 housed inside to an external electric circuit, and are made of Kovar metal (Fe- A rod-shaped metal such as Ni-Co alloy or 42 alloy (Fe-Ni alloy) is used.
【００１５】尚、前記信号線5a及びグランド層5bはその
露出する表面にニッケル、金等から成る耐蝕性に優れ、
且つ良導電性の金属を従来周知のメッキ法により1.0 乃
至20.0μm の厚みに層着させておけば信号線5a及びグラ
ンド層5bが酸化腐食して断線等するのを有効に防止する
ことができるとともに信号線5a及びグランド層5bへのボ
ンディングワイヤ6 の接続及び外部リードピンの取着を
確実、強固と成すことができる。従って、前記信号線5a
及びグランド層5bはその露出する表面にニッケル、金等
から成る耐蝕性に優れ、且つ良導電性の金属を1.0 乃至
20.0μm の厚みに層着させておくことが好ましい。The signal lines 5a and the ground layer 5b have excellent corrosion resistance made of nickel, gold, etc. on their exposed surfaces,
In addition, by depositing a metal having good conductivity to a thickness of 1.0 to 20.0 μm by the well-known plating method, it is possible to effectively prevent the signal line 5a and the ground layer 5b from being oxidized and corroded to cause disconnection. At the same time, the connection of the bonding wire 6 to the signal line 5a and the ground layer 5b and the attachment of the external lead pin can be achieved reliably and firmly. Therefore, the signal line 5a
Also, the ground layer 5b has a metal such as nickel, gold, etc. having excellent corrosion resistance and good conductivity on the exposed surface of 1.0 to
It is preferable that the layers are layered to a thickness of 20.0 μm.
【００１６】また同時に外部リードピン7 の露出表面に
ニッケル、金等を従来周知のメッキ法により1.0 乃至2
0.0μm の厚みに層着させておけば外部リードピン7 を
外部電気回路に確実、且つ強固に接続させることができ
る。従って、外部リードピン7の露出表面にもニッケ
ル、金等を1.0 乃至20.0μm の厚みに層着させておくこ
とが好ましい。At the same time, the exposed surface of the external lead pin 7 is plated with nickel, gold, etc. by 1.0 to 2 by a well-known plating method.
The external lead pins 7 can be reliably and firmly connected to the external electric circuit by layering them to a thickness of 0.0 μm. Therefore, it is preferable that nickel, gold or the like is also layered on the exposed surface of the external lead pin 7 to a thickness of 1.0 to 20.0 μm.
【００１７】前記基体2 の内部及び上下面に被着させた
信号線5a及びグランド線5bはまた信号線5aがグランド線
5bに挟まれた状態で基体2 に形成されており、信号線5a
を周囲のグランド線5bによって完全にシールドした状態
となっている。そのため信号線5aに外部からノイズが入
り込もうとしても該ノイズはグランド線5bで遮断され、
信号線5aにノイズが入り込んで半導体素子4 を誤動作さ
せることはない。The signal line 5a and the ground line 5b attached to the inside and the upper and lower surfaces of the base 2 are also the signal line 5a and the ground line.
It is formed on the base 2 while being sandwiched between the signal lines 5a and 5b.
Is completely shielded by the surrounding ground wire 5b. Therefore, even if noise enters the signal line 5a from the outside, the noise is blocked by the ground line 5b,
The semiconductor element 4 does not malfunction due to noise entering the signal line 5a.
【００１８】また前記基体２はその上面に蓋体３が半田
等の金属製封止材8 を介して接合される。A lid 3 is joined to the upper surface of the base body 2 via a metallic sealing material 8 such as solder.
【００１９】前記蓋体３は、酸化アルミニウム質焼結
体、ムライト質焼結体、窒化アルミニウム質焼結体、炭
化珪素質焼結体等の電気絶縁材料から成り、その下面中
央部に半導体素子4 を収容する空所を形成するための凹
部Ｂが形成された椀状となっている。The lid 3 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, and a silicon carbide sintered body. It has a bowl-like shape with a recess B for forming a cavity for accommodating 4.
【００２０】前記蓋体３は例えば酸化アルミニウム質焼
結体から成る場合、基体2 と同様、アルミナ、シリカ、
カルシア、マグネシア等の原料粉末に適当なバインダ
ー、有機溶媒を添加混合して泥漿状となすとともにこれ
を従来周知のドクターブレード法を採用することによっ
てセラミックグリーンシート( セラミック生シート) を
得、しかる後、前記セラミックグリーンシートに適当な
打ち抜き加工を施すとともに複数枚積層し、高温( 約16
00℃) で焼成することによって製作される。When the lid 3 is made of, for example, an aluminum oxide sintered body, the same as the base 2, alumina, silica,
A ceramic green sheet (ceramic green sheet) is obtained by adding a suitable binder and organic solvent to raw material powder of calcia, magnesia, etc. and mixing them to form a slurry and adopting the conventionally known doctor blade method. Appropriate punching processing is applied to the ceramic green sheets and multiple sheets are laminated, and high temperature (about 16
It is manufactured by firing at 00 ℃.
【００２１】また、前記蓋体３はその凹部Ｂの内壁に、
タングステン、モリブデン等の高融点金属から成る金属
層９が形成されており、該金属層9 は半田等の金属製封
止材8 を介し基体2 のグランド線5bと電気的に接続され
ている。この場合、内部に収容される半導体素子4 は基
体2 に設けたグランド層5bと該グランド層5bと電気的に
接続する蓋体2 の金属層9 とで完全に囲まれてシールド
され、外部ノイズが蓋体2 を介して入り込む、或いは内
部に収容した半導体素子４等から発生するノイズが蓋体
３を介して外部に漏れることは殆ど無くなり、半導体素
子収納用パッケージ１内に収容される半導体素子４をノ
イズに関し外部と完全に遮断させることが可能となる。The lid 3 is provided on the inner wall of the recess B,
A metal layer 9 made of a refractory metal such as tungsten or molybdenum is formed, and the metal layer 9 is electrically connected to the ground wire 5b of the base 2 via a metal sealing material 8 such as solder. In this case, the semiconductor element 4 housed inside is completely surrounded and shielded by the ground layer 5b provided on the base body 2 and the metal layer 9 of the lid body 2 electrically connected to the ground layer 5b, and the external noise is prevented. Is rarely introduced through the lid 2 or noise generated from the semiconductor element 4 or the like housed inside is leaked to the outside through the lid 3, and the semiconductor element housed in the semiconductor element housing package 1 is almost eliminated. It is possible to completely shut off 4 from the outside with respect to noise.
【００２２】尚、前記金属層９はタングステン等の高融
点金属粉末に適当なバインダー、有機溶媒を添加混合す
ることによって得た金属ペーストを蓋体３となるセラミ
ックグリーンシートに予め従来周知のスクリーン印刷等
の厚膜手法で印刷塗布させておくことによって蓋体３の
凹部Ｂ内壁に被着形成される。For the metal layer 9, a metal paste obtained by adding and mixing an appropriate binder and an organic solvent to a high melting point metal powder such as tungsten is preliminarily known by screen printing on a ceramic green sheet serving as the lid body 3. It is adhered and formed on the inner wall of the concave portion B of the lid 3 by printing and applying it by a thick film method such as.
【００２３】また前記蓋体2 に被着させた金属層９はそ
の露出表面を酸化アルミニウム、ムライト、窒化アルミ
ニウム、炭化珪素等の電気絶縁材料から成る被覆層で覆
っておくと基体2 に形成した信号線5a及びシールド線5b
に半導体素子４の各電極をボンディングワイヤ6 を介し
て接続する際、ボンディングワイヤ6 の一部が蓋体３に
被着させた金属層９に接触して短絡するのを有効に防止
することができる。従って、前記蓋体2 に被着させた金
属層９はその露出表面を電気絶縁材料から成る被覆層で
覆っておくことが好ましい。The metal layer 9 deposited on the lid 2 is formed on the base 2 by covering the exposed surface with a coating layer made of an electrically insulating material such as aluminum oxide, mullite, aluminum nitride, or silicon carbide. Signal line 5a and shielded line 5b
When connecting the respective electrodes of the semiconductor element 4 to each other via the bonding wires 6, it is possible to effectively prevent a part of the bonding wires 6 from coming into contact with the metal layer 9 attached to the lid body 3 to cause a short circuit. it can. Therefore, it is preferable that the exposed surface of the metal layer 9 deposited on the lid 2 is covered with a coating layer made of an electrically insulating material.
【００２４】更に前記被覆層はその材質を蓋体３と実質
的に同一材質となしておくと蓋体３と被覆層との間に熱
が印加された際、両者間に両者の熱膨張係数の相違に起
因した熱応力が殆ど発生せず、被覆層を蓋体３に強固に
被着させて金属層９を常に被覆することができる。従っ
て、前記被覆層は蓋体３と実質的に同一の材質で形成し
ておくことが好ましい。Further, if the cover layer is made of substantially the same material as that of the cover 3, when heat is applied between the cover 3 and the cover layer, the coefficient of thermal expansion of the cover and the cover 3 is increased. The thermal stress due to the difference is hardly generated, and the cover layer can be firmly adhered to the lid body 3 to always cover the metal layer 9. Therefore, it is preferable that the covering layer is formed of substantially the same material as the lid 3.
【００２５】かくして本発明の半導体素子収納用パッケ
ージによれば、基体２の搭載部Ａに半導体素子４を取着
搭載した後、半導体素子４の各電極を基体2 に形成した
信号線5a及びシールド線5bにボンディングワイヤ6 を介
して接続し、最後に基体２の上面に蓋体３を、該蓋体3
の凹部内壁に被着させた金属層9 が基体2 に形成したシ
ールド線5bに電気的に接続するように半田等の金属製封
止材8 を介して接合させ、基体2 と蓋体3 から成る容器
内部に半導体素子4 を気密に封止することによって最終
製品としての半導体装置となる。Thus, according to the semiconductor element housing package of the present invention, after the semiconductor element 4 is mounted and mounted on the mounting portion A of the base body 2, the electrodes of the semiconductor element 4 are formed on the base body 2 and the signal line 5a and the shield. It is connected to the wire 5b through a bonding wire 6, and finally, the lid 3 is attached to the upper surface of the substrate 2 and the lid 3
The metal layer 9 adhered to the inner wall of the concave portion is bonded to the shield wire 5b formed on the base body 2 via a metal sealing material 8 such as solder so as to be electrically connected to the base body 2 and the lid body 3. The semiconductor device as a final product is obtained by hermetically sealing the semiconductor element 4 inside the container.
【００２６】尚、本発明は前記実施例に限定されるもの
ではなく、本発明の要旨を逸脱しない範囲であれば種々
の変更は可能であり、例えば前記実施例では蓋体3 に被
着させた金属層９をタングステンやモリブデン等の高融
点金属粉末で形成したが、銀−パラジウムや銅等の他の
金属で形成してもよい。この場合、銀−パラジウムや銅
等から成る金属層９はまずセラミックグリーンシートを
複数枚積層するとともに高温で焼成して蓋体３を得、し
かる後、蓋体３の凹部Ｂ内壁に銀−パラジウム、銅等の
金属ペーストを従来周知のスクリーン印刷等の厚膜手法
を採用することによって印刷塗布するとともにこれを約
１０００℃の高温で焼き付けるとによって蓋体３の凹部
Ｂ内壁に被着させる。The present invention is not limited to the above-mentioned embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the above-mentioned embodiment, the lid 3 is attached to the cover 3. Although the metal layer 9 is formed of a refractory metal powder such as tungsten or molybdenum, it may be formed of another metal such as silver-palladium or copper. In this case, the metal layer 9 made of silver-palladium, copper or the like is first laminated with a plurality of ceramic green sheets and fired at a high temperature to obtain the lid body 3, and then the inner wall of the recess B of the lid body 3 is silver-palladium. , A metal paste such as copper is applied by printing by using a conventionally known thick film technique such as screen printing, and is baked at a high temperature of about 1000 ° C. to adhere to the inner wall of the recess B of the lid 3.
【００２７】また、前記実施例では金属層９をスクリー
ン印刷等の厚膜手法を採用して被着形成したが、蒸着や
スパッタ等の薄膜手法を採用して被着形成してもよい。Further, in the above-mentioned embodiment, the metal layer 9 is deposited by using a thick film method such as screen printing, but it may be deposited by using a thin film method such as vapor deposition or sputtering.
【００２８】更に、前記実施例は半導体素子収納用パッ
ケージを例にとって説明したが、水晶振動子やＳＡＷフ
ィルター等の他の種類の電子部品を収容するパッケージ
にも適用し得る。Further, although the above embodiment has been described by taking the package for storing a semiconductor device as an example, the present invention can be applied to a package for storing other kinds of electronic parts such as a crystal oscillator and a SAW filter.
【００２９】[0029]
【発明の効果】本発明に係る電子部品収納用パッケージ
によれば、基体に形成した信号線をグランド線で挟み、
椀状蓋体の凹部内壁に金属層を被着させ、そして基体の
グランド線と蓋体の金属層とを金属製封止材で電気的に
接続させたことから基体に形成した信号線及びパッケー
ジの内部に収容する電子部品の両方をグランド線で完全
にシールドすることができ、その結果、基体に形成した
信号線及びパッケージの内部に収容する電子部品に外部
ノイズが入り込むことは一切無く、内部に収容する電子
部品を正常、且つ安定に作動させることが可能となる。According to the electronic component storing package of the present invention, the signal line formed on the base body is sandwiched between the ground lines,
A metal layer is deposited on the inner wall of the concave portion of the bowl-shaped lid, and the ground wire of the base and the metal layer of the lid are electrically connected by a metal sealing material. Both of the electronic components housed inside can be completely shielded by the ground line, and as a result, external noise does not enter the signal lines formed on the base body and the electronic components housed inside the package at all. It is possible to normally and stably operate the electronic components housed in.
【００３０】また同時に内部に収容する電子部品等が発
生するノイズはパッケージの外部に漏れることはなく、
その結果、近接して配置される他の装置に誤動作等の悪
影響を与えることもない。At the same time, noise generated by electronic components housed inside does not leak to the outside of the package,
As a result, other devices arranged close to each other are not adversely affected such as malfunction.
【図１】本発明の電子部品収納用パッケージを半導体素
子を収容する半導体素子収納用パッケージを例にとって
説明するための断面図である。FIG. 1 is a cross-sectional view for explaining an electronic component storage package of the present invention by taking a semiconductor element storage package for storing a semiconductor element as an example.
１・・・・・・電子部品収納用パッケージ ２・・・・・・基体 ３・・・・・・蓋体 ５ａ・・・・・信号線 ５ｂ・・・・・グランド線 ８・・・・・・金属製封止材 ９・・・・・・金属層 Ａ・・・・・・電子部品搭載部 Ｂ・・・・・・蓋体の凹部 1- ・ Package for storing electronic parts 2 --- Base body 3--Lid body 5a-Signal line 5b-Ground line 8- ..Metallic encapsulant 9 ... Metal layer A ... Electronic component mounting part B ... Recess in the lid
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 23/14 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 23/14
Claims (1)
を搭載するための搭載部を有する基体上に、該搭載部に
搭載される電子部品を内部に収容するように凹部を有す
る椀状の蓋体を金属製封止材を介して取着する電子部品
収納用パッケージであって、前記基体の信号線をグラン
ド線で挟むとともに椀状蓋体の凹部内壁に金属層を被着
させ、且つ前記基体のグランド線と蓋体の金属層とを金
属製封止材で電気的に接続させたことを特徴とする電子
部品収納用パッケージ。1. A bowl having a recess for accommodating an electronic component mounted on the mounting portion on a base having a mounting portion for mounting an electronic component and having a signal line and a ground line. A package for storing electronic parts, in which a lid-shaped lid is attached via a metal sealing material, wherein a signal line of the base body is sandwiched between ground lines and a metal layer is adhered to the inner wall of the recess of the bowl-shaped lid. A package for storing electronic parts, characterized in that the ground wire of the base and the metal layer of the lid are electrically connected by a metal sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3301758A JP2851732B2 (en) | 1991-11-18 | 1991-11-18 | Electronic component storage package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3301758A JP2851732B2 (en) | 1991-11-18 | 1991-11-18 | Electronic component storage package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05144953A true JPH05144953A (en) | 1993-06-11 |
| JP2851732B2 JP2851732B2 (en) | 1999-01-27 |
Family
ID=17900817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3301758A Expired - Fee Related JP2851732B2 (en) | 1991-11-18 | 1991-11-18 | Electronic component storage package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2851732B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11274344A (en) * | 1998-03-20 | 1999-10-08 | Nec Kansai Ltd | Package for sealing electronic element and electronic element sealing structure thereof |
| JP2000058692A (en) * | 1998-08-14 | 2000-02-25 | Toyo Commun Equip Co Ltd | Package for electronic components |
| US6355978B1 (en) | 1999-07-19 | 2002-03-12 | Mitsubishi Denki Kabushiki Kaisha | Package for accommodating electronic parts, semiconductor device and method for manufacturing package |
| US6800189B2 (en) | 1999-08-18 | 2004-10-05 | Murata Manufacturing Co., Ltd. | Method of forming insulating film of conductive cap by anodizing or electrodeposition |
-
1991
- 1991-11-18 JP JP3301758A patent/JP2851732B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11274344A (en) * | 1998-03-20 | 1999-10-08 | Nec Kansai Ltd | Package for sealing electronic element and electronic element sealing structure thereof |
| JP2000058692A (en) * | 1998-08-14 | 2000-02-25 | Toyo Commun Equip Co Ltd | Package for electronic components |
| US6355978B1 (en) | 1999-07-19 | 2002-03-12 | Mitsubishi Denki Kabushiki Kaisha | Package for accommodating electronic parts, semiconductor device and method for manufacturing package |
| US6800189B2 (en) | 1999-08-18 | 2004-10-05 | Murata Manufacturing Co., Ltd. | Method of forming insulating film of conductive cap by anodizing or electrodeposition |
| US6866893B2 (en) | 1999-08-18 | 2005-03-15 | Murata Manufacturing Co., Ltd. | Conductive cap, electronic component, and method of forming insulating film of conductive cap |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2851732B2 (en) | 1999-01-27 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |