JPH05226514A - Semiconductor element containing package - Google Patents

Semiconductor element containing package

Info

Publication number
JPH05226514A
JPH05226514A JP3076592A JP3076592A JPH05226514A JP H05226514 A JPH05226514 A JP H05226514A JP 3076592 A JP3076592 A JP 3076592A JP 3076592 A JP3076592 A JP 3076592A JP H05226514 A JPH05226514 A JP H05226514A
Authority
JP
Japan
Prior art keywords
semiconductor element
frame member
metal base
metal
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3076592A
Other languages
Japanese (ja)
Inventor
Tsutomu Ishida
勉 石田
Tetsuo Abumita
哲郎 鐙田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP3076592A priority Critical patent/JPH05226514A/en
Publication of JPH05226514A publication Critical patent/JPH05226514A/en
Pending legal-status Critical Current

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To actuate a semiconductor element normally and stably by a method wherein a metallic substrate is effectivelly prevented from warping so as to efficiently absorb the heat generated by the semiconductor chip. CONSTITUTION:Within the tile semiconductor element containing package, an iron alloy made frame member 2 having an insulating member 3 engaged therewith is attached to the surface outer periphery of a metallic substrate 1 so as to fixedly contain a semiconductor chip 4 in a space formed by the surface of the semiconductor chip 1 and the frame member 2 to be contained in the space. In such a constitution, the metallic substrate 1 is composed of a molybdenum plate 5 with copper plates 6, 7 junctioned with upper and lower surfaces while assuming the thickness of the molybdenum plate 5, the copper plate 6 positioned on the upper surface side whereto the semiconductor chip 4 is fixed and the other copper plate 7 positioned on the rear surface side respectively as T1, T2, T3, T2/T1 = to while T3/T2=-T2/12T1+1.3 to -T2/12T1+1.6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体素子、特に高出
力、高周波数のパワートランジスタ等を収容するための
半導体素子収納用パッケージの改良に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an improvement of a semiconductor device housing package for housing a high power, high frequency power transistor and the like.

【0002】[0002]

【従来技術及びその課題】従来、高出力、高周波数のパ
ワートランジスタ等を収容する半導体素子収納用パッケ
ージは上面に半導体素子が載置固定される載置部を有す
る金属基体と、該載置部を囲繞するように金属基体の上
面外周部に銀ロウ等のロウ材を介し取着される枠部材
と、枠部材に設けた貫通穴に嵌着され、内部に収容する
半導体素子の電極を外部電気回路に接続するためのメタ
ライズ配線層を有する絶縁部材とから構成されており、
金属基体の半導体素子載置部に半導体素子を接着材を介
して載置固定するとともに半導体素子の各電極を絶縁部
材のメタライズ配線層にボンディングワイヤを介して電
気的に接続し、しかる後、枠部材の上面に蓋体をロウ材
等から成る封止材を介して接合させ、内部に半導体素子
を気密に封止することによって最終製品としての半導体
装置となる。
2. Description of the Related Art Conventionally, a semiconductor element accommodating package for accommodating high-output, high-frequency power transistors and the like has a metal base body having a mounting portion on which a semiconductor element is mounted and fixed, and the mounting portion. A frame member that is attached to the outer peripheral portion of the upper surface of the metal base via a brazing material such as silver solder so as to surround the metal base, and the electrode of the semiconductor element that is fitted inside the through hole provided in the frame member and is externally And an insulating member having a metallized wiring layer for connecting to an electric circuit,
The semiconductor element is mounted and fixed on the semiconductor element mounting portion of the metal substrate through the adhesive, and each electrode of the semiconductor element is electrically connected to the metallized wiring layer of the insulating member through the bonding wire. A lid is joined to the upper surface of the member via a sealing material made of a brazing material or the like, and the semiconductor element is hermetically sealed inside, so that a semiconductor device as a final product is obtained.

【0003】尚、前記半導体素子収納用パッケージにお
いては通常、絶縁部材が酸化アルミニウム質焼結体から
成っており、該絶縁部材が嵌着される枠部材は前記絶縁
部材と熱膨張係数を合わせるためにコバール金属等の鉄
合金材料で形成されている。
In the package for housing the semiconductor element, the insulating member is usually made of an aluminum oxide sintered body, and the frame member to which the insulating member is fitted has the same thermal expansion coefficient as that of the insulating member. It is made of iron alloy material such as Kovar metal.

【0004】また前記金属基体は該金属基体にロウ付け
取着される枠部材と熱膨張係数を合わせるために同じく
コバール金属等の鉄合金材料により形成されている。
The metal base is also made of an iron alloy material such as Kovar metal in order to match the thermal expansion coefficient with the frame member brazed and attached to the metal base.

【0005】しかしながら、上記従来の半導体素子収納
用パッケージにおいては金属基体がコバール金属等の鉄
合金から成り、その熱伝導率が0.040cal/sec・cm・℃程
度と低いこと及び近時、パワートランジスタ等の半導体
素子はその出力が極めて大きく多量の熱を発生するもの
となってきていること等からパッケージ内部に半導体素
子を収容し半導体装置となした後、半導体素子を作動さ
せると該半導体素子の作動時に発生する熱が外部に良好
に放出されずに半導体素子自身に蓄積されてしまい、そ
の結果、半導体素子が高温となり、半導体素子に熱破壊
を起こさせたり、半導体素子の特性に変化を与え、半導
体素子を誤動作させるという欠点を招来した。
However, in the conventional package for accommodating semiconductor elements described above, the metal substrate is made of an iron alloy such as Kovar metal, and its thermal conductivity is as low as 0.040 cal / sec · cm · ° C. Since the output of such a semiconductor element is extremely large and a large amount of heat is generated, the semiconductor element is housed inside the package to form a semiconductor device, and then the semiconductor element is operated when the semiconductor element is operated. The heat generated during operation is not radiated well to the outside and is accumulated in the semiconductor element itself, resulting in a high temperature of the semiconductor element, causing thermal damage to the semiconductor element or changing the characteristics of the semiconductor element. However, there is a drawback that the semiconductor device malfunctions.

【0006】そこで上記欠点を解消するために半導体素
子が固定される金属基体を熱伝導率が0.9cal/sec・cm・
℃と高い無酸素銅を使用することが考えられる。
Therefore, in order to solve the above-mentioned drawbacks, a metal substrate on which a semiconductor element is fixed has a thermal conductivity of 0.9 cal / sec · cm ·
It is conceivable to use oxygen-free copper as high as ℃.

【0007】しかしながら、この無酸素銅を金属基体と
して使用した場合、半導体素子が作動時に発する熱は金
属基体を介して外部に良好に放出され半導体素子を低温
となすことができるものの無酸素銅の熱膨張係数が18.3
×10-6/ ℃と高く枠部材の熱膨張係数(5.7×10-6/ ℃〜
6.2 ×10-6/ ℃:800℃) と大きく相違するため金属部材
に枠部材を銀ロウ等のロウ材を介してロウ付け取着する
際、両者の熱膨張係数の相違に起因する熱応力によって
金属基体が大きく反り返り、その結果、金属基体に半導
体素子を強固に固定することができなくなったり、半導
体素子と金属基体との間に空隙が形成され、半導体素子
の発生する熱を金属基体に良好に吸収させることが不可
となったりする欠点を誘発してしまう。
However, when this oxygen-free copper is used as a metal substrate, the heat generated during the operation of the semiconductor element is satisfactorily released to the outside through the metal substrate, and the temperature of the semiconductor element can be kept low. Coefficient of thermal expansion is 18.3
× 10 -6 / ℃ as high as the thermal expansion coefficient of the frame member (5.7 × 10 -6 / ℃ ~
(6.2 × 10 -6 / ° C: 800 ° C), the thermal stress caused by the difference in the thermal expansion coefficient between the frame member and the metal member when brazing and attaching it to the metal member via the brazing material such as silver solder. As a result, the metal base is largely warped, and as a result, the semiconductor element cannot be firmly fixed to the metal base, or a gap is formed between the semiconductor element and the metal base, and the heat generated by the semiconductor element is transferred to the metal base. It causes a defect that it cannot be absorbed well.

【0008】[0008]

【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は熱伝導率が高い金属基体に鉄合金製枠
部材を前記金属基体に反りを発生することなく取着し、
これによって半導体素子を金属基体に強固に固定し、且
つ半導体素子の発生する熱を外部に良好に放出し、半導
体素子を常に低温として長期間にわたり正常、且つ安定
に作動させることができる半導体素子収納用パッケージ
を提供することにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object of the present invention is to attach an iron alloy frame member to a metal base having a high thermal conductivity without warping the metal base. ,
With this, the semiconductor element is firmly fixed to the metal substrate, and the heat generated by the semiconductor element is satisfactorily radiated to the outside, so that the semiconductor element can be kept at a low temperature and can be operated normally and stably for a long period of time. To provide a package for.

【0009】[0009]

【課題を解決するための手段】本発明は酸化アルミニウ
ム質焼結体から成る絶縁部材を嵌着させた鉄合金製枠部
材を金属基体の上面外周部に取着させ、金属基体上面と
枠部材とによって形成される空間内に半導体素子を固定
収容するようになした半導体素子収納用パッケージであ
って、前記金属基体はモリブデン板の上下両面に銅板を
接合させたものから成り、且つモリブデン板の厚みをT
1、半導体素子の固定される上面側に位置する銅板の厚
みをT2、下面側に位置する銅板の厚みをT3とすると T2/T1=1〜7で、且つ T3/T2=−T2/12T1+1.3〜−T2/12
T1+1.6 であることを特徴とするものである。
According to the present invention, an iron alloy frame member fitted with an insulating member made of an aluminum oxide sintered body is attached to an outer peripheral portion of an upper surface of a metal base, and the upper surface of the metal base and the frame member are attached. A semiconductor element housing package, in which a semiconductor element is fixedly housed in a space formed by, wherein the metal base is composed of a molybdenum plate and copper plates bonded to both upper and lower surfaces of the molybdenum plate. Thickness is T
1. If the thickness of the copper plate located on the upper surface side of the semiconductor element to be fixed is T2 and the thickness of the copper plate located on the lower surface side is T3, then T2 / T1 = 1 to 7, and T3 / T2 = −T2 / 12T1 + 1. 3 to -T2 / 12
It is characterized in that it is T1 + 1.6.

【0010】[0010]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings.

【0011】図1 及び図2 は本発明の半導体素子収納用
パッケージの一実施例を示し、1 は金属基体、2 は枠部
材、3 は絶縁部材である。
1 and 2 show an embodiment of a package for housing a semiconductor device according to the present invention, in which 1 is a metal base, 2 is a frame member, and 3 is an insulating member.

【0012】前記金属基体1 はその上面外周部に枠部材
2 が銀ロウ等のロウ材を介して取着されており、該枠部
材2 によって囲まれる金属基体1 の上面には半導体素子
4 がロウ材等の接着材を介して載置固定される。
The metal base 1 has a frame member on the outer periphery of its upper surface.
2 is attached via a brazing material such as silver brazing, and a semiconductor element is provided on the upper surface of the metal substrate 1 surrounded by the frame member 2.
4 is placed and fixed via an adhesive such as a brazing material.

【0013】前記金属基体1 はモリブデン板5 の上下両
面に銅板6 、7 を配した3 層構造を有しており、下側銅
板7 、モリブデン板5 、上側銅板6 及び枠部材2 を順次
積層するとともにその各々を銀ロウ等のロウ材で同時に
接合させることによって金属基体1 の上面外周部に枠部
材を取着したものが得られる。
The metal substrate 1 has a three-layer structure in which copper plates 6 and 7 are arranged on both upper and lower surfaces of a molybdenum plate 5, and a lower copper plate 7, a molybdenum plate 5, an upper copper plate 6 and a frame member 2 are sequentially laminated. At the same time, each of them is simultaneously joined with a brazing material such as silver brazing to obtain a metal base 1 having a frame member attached to the outer peripheral surface of the upper surface thereof.

【0014】前記金属基体1 を構成する上側銅板6 は金
属基体1 上に枠部材2 を取着する際、金属基体1 を構成
するモリブデン板5 と枠部材2 との間に発生する両者の
熱膨張係数の相違に起因する熱応力の一部を吸収する作
用を為し、また下側銅板7 は前記金属基体1 を構成する
モリブデン板5 と枠部材2 との間に残余する熱応力によ
って金属基体1 に反りが発生するのを打ち消す作用を為
し、これによって金属基板1 は反りを発生することなく
その上面に枠部材2 を取着することができる。
The upper copper plate 6 forming the metal base 1 is heated by the molybdenum plate 5 forming the metal base 1 and the frame member 2 when the frame member 2 is mounted on the metal base 1. The lower copper plate 7 acts to absorb a part of the thermal stress due to the difference in the expansion coefficient, and the lower copper plate 7 is made of metal by the residual thermal stress between the molybdenum plate 5 and the frame member 2 constituting the metal base 1. The base member 1 has a function of canceling the occurrence of warpage, whereby the metal substrate 1 can mount the frame member 2 on its upper surface without causing warpage.

【0015】尚、前記金属基体1 はモリブデン板5 の厚
みをT1、半導体素子の固定される上面側に位置する銅
板6 の厚みをT2、下面側に位置する銅板7 の厚みをT
3とすると、T2/T1<1の時、金属基体1 の熱伝導
率が低いものとなって半導体素子4 の発する熱を有効に
除去することができなくなり、またT2/T1>7 の
時、金属基体1 の熱膨張係数が大きくなって枠部材2 の
熱膨張係数と合わなくなり、その結果、金属基体1 に大
きな反りが発生して半導体素子4 を強固に固定すること
ができない。従って、前記金属基体1 はモリブデン板5
の厚みをT1、半導体素子の固定される上面側に位置す
る銅板6 の厚みをT2、下面側に位置する銅板7 の厚み
をT3とすると、T2/T1=1〜7の範囲に特定され
る。
In the metal substrate 1, the thickness of the molybdenum plate 5 is T1, the thickness of the copper plate 6 located on the upper surface side where the semiconductor element is fixed is T2, and the thickness of the copper plate 7 located on the lower surface side is T2.
When it is set to 3, when T2 / T1 <1, the heat conductivity of the metal substrate 1 becomes low, and the heat generated by the semiconductor element 4 cannot be effectively removed, and when T2 / T1> 7, The coefficient of thermal expansion of the metal substrate 1 becomes large and does not match the coefficient of thermal expansion of the frame member 2. As a result, a large warp occurs in the metal substrate 1 and the semiconductor element 4 cannot be firmly fixed. Therefore, the metal base 1 is a molybdenum plate 5
Is T1, the thickness of the copper plate 6 located on the upper surface side to which the semiconductor element is fixed is T2, and the thickness of the copper plate 7 located on the lower surface side is T3, T2 / T1 = 1 to 7 is specified. ..

【0016】またT3/T2<−T2/12T1+1.
3の時、金属基体1が凹状に大きく湾曲し、金属基体1
に半導体素子を強固に固定させることが困難となり、ま
た、逆にT3/T2>−T2/12T1+1.6の時、
金属基体1が凸状に大きく湾曲して金属基体1に半導体
素子を強固に固定させることが困難となる。従って、前
記金属基体1 はモリブデン板5 の厚みをT1、半導体素
子の固定される上面側に位置する銅板6 の厚みをT2、
下面側に位置する銅板7 の厚みをT3とすると、T3/
T2=−T2/12T1+1.3〜−T2/12T1+
1.6の範囲に特定される。
In addition, T3 / T2 <-T2 / 12T1 + 1.
When 3, the metal base 1 is greatly curved in a concave shape, and the metal base 1
It becomes difficult to firmly fix the semiconductor element to, and conversely, when T3 / T2> -T2 / 12T1 + 1.6,
Since the metal base 1 is largely curved in a convex shape, it becomes difficult to firmly fix the semiconductor element to the metal base 1. Therefore, the metal substrate 1 has a thickness T1 of the molybdenum plate 5, and a thickness T2 of the copper plate 6 located on the upper surface side on which the semiconductor element is fixed.
If the thickness of the copper plate 7 located on the lower surface side is T3, T3 /
T2 = -T2 / 12T1 + 1.3 to -T2 / 12T1 +
It is specified in the range of 1.6.

【0017】前記モリブデン板5 の上下両面に銅板6 、
7 を接合させた金属基体1はまたその熱伝導率が約0.75
〜0.9cal/sec・cm・℃であり、熱伝導率が高いため半導
体素子4 が作動時に発生する熱は金属基体1が直接伝導
吸収するとともに大気中に良好に放出して半導体素子4
を常に低温とし、その結果、半導体素子4 を長期間にわ
たり正常、且つ安定に作動させることが可能となる。
Copper plates 6 are formed on both upper and lower surfaces of the molybdenum plate 5,
The metal base 1 bonded with 7 also has a thermal conductivity of about 0.75.
The heat generated when the semiconductor element 4 is operated is directly conducted and absorbed by the metal substrate 1 and is well radiated into the atmosphere, because it has a thermal conductivity of up to 0.9 cal / sec · cm · ° C.
Is always kept at a low temperature, and as a result, the semiconductor element 4 can be operated normally and stably for a long period of time.

【0018】また前記金属基体1 の上面外周部に取着さ
れる枠部材2 はコバール金属(Fe-Ni-Co 合金) 等の鉄合
金材料から成り、半導体素子4 を収容する空間を形成す
るための壁材として作用する。
Further, the frame member 2 attached to the outer peripheral portion of the upper surface of the metal substrate 1 is made of an iron alloy material such as Kovar metal (Fe-Ni-Co alloy) and forms a space for housing the semiconductor element 4. Acts as a wall material for.

【0019】前記枠部材2 はコバール金属等のインゴッ
ト( 塊) を金属圧延加工法や研削加工法等、従来周知の
金属加工法を採用することによって所定の枠状に形成さ
れる。
The frame member 2 is formed in a predetermined frame shape by adopting a conventionally known metal processing method such as a metal rolling processing method or a grinding processing method for an ingot (lump) of Kovar metal or the like.

【0020】前記枠部材2 はまたその一部に貫通穴8 が
形成されており、該貫通穴8 には内部に収容する半導体
素子4 の電極を外部電気回路に電気的に接続するための
メタライズ配線層9 を有するは絶縁部材3 が銀ロウ等の
ロウ材を介して嵌着されている。
The frame member 2 also has a through hole 8 formed in a part thereof, and the through hole 8 is a metallization for electrically connecting the electrode of the semiconductor element 4 housed therein to an external electric circuit. The insulating member 3 having the wiring layer 9 is fitted via a brazing material such as silver brazing.

【0021】前記絶縁部材3 は酸化アルミニウム質焼結
体から成り、アルミナ(Al2O3) 、シリカ(SiO2)、カルシ
ア(CaO) 、マグネシア(MgO) 等の原料粉末に適当な有機
溶剤、溶媒を添加混合して泥漿となすとともにこれをド
クターブレード法やカレンダーロール法を採用すること
によってグリーンシート( 生シート) を形成し、しかる
後、グリーンシートに適当な打ち抜き加工を施すととも
に複数枚積層し、高温( 約1600℃) で焼成することによ
って製作される。
The insulating member 3 is made of an aluminum oxide sintered body, and an organic solvent suitable for raw material powder such as alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO) and magnesia (MgO), A solvent is added and mixed to form sludge, which is then formed into a green sheet (raw sheet) by using the doctor blade method or calendar roll method.After that, the green sheet is punched appropriately and multiple sheets are laminated. It is manufactured by firing at high temperature (about 1600 ℃).

【0022】前記酸化アルミニウム質焼結体から成る絶
縁部材3 はその熱膨張係数が枠部材2 を構成する鉄合金
材と近似し、そのため枠部材2 に絶縁部材3 を嵌着した
後、両者に熱が印加されたとしても両者間には熱膨張係
数の相違に起因する熱応力が発生することはなく、絶縁
部材3 を枠部材2 に極めて強固に嵌着させることが可能
となる。
The insulating member 3 made of the aluminum oxide sintered body has a thermal expansion coefficient similar to that of the iron alloy material forming the frame member 2. Therefore, after the insulating member 3 is fitted to the frame member 2, both Even if heat is applied, no thermal stress is generated between them due to the difference in thermal expansion coefficient, and the insulating member 3 can be fitted to the frame member 2 extremely firmly.

【0023】また前記絶縁部材3 には枠部材2 の内外を
挿通するようにメタライズ配線層9が設けてあり、該メ
タライズ配線層9 の一端には半導体素子4 の電極がボン
ディングワイヤ10を介して接続され、また他端には外部
電気回路に直接接続される外部リード端子11がロウ付け
されている。
Further, a metallized wiring layer 9 is provided on the insulating member 3 so as to pass through the inside and outside of the frame member 2, and an electrode of the semiconductor element 4 is provided with a bonding wire 10 at one end of the metallized wiring layer 9. An external lead terminal 11 which is connected to the other end and which is directly connected to an external electric circuit is brazed.

【0024】前記メタライズ配線層9 はモリブデンやタ
ングステン等の高融点金属粉末から成り、該モリブデン
粉末等に適当な有機溶剤、溶媒を添加混合して得た金属
ペーストを絶縁部材3 となるグリーンシートに予めスク
リーン印刷等の厚膜手法で印刷塗布しておくことによっ
て絶縁部材3 に所定形状に被着される。
The metallized wiring layer 9 is made of a refractory metal powder such as molybdenum or tungsten, and a metal paste obtained by adding and mixing a suitable organic solvent or solvent to the molybdenum powder or the like is used as a green sheet for the insulating member 3. The insulating member 3 is applied in a predetermined shape by printing and applying it in advance by a thick film technique such as screen printing.

【0025】尚、前記メタライズ配線層9 はその表面に
ニッケル(Ni)、金(Au)等の耐蝕性に優れ、且つ良導電性
である金属材料をメッキ法により1.0 乃至20.0μm の厚
みに層着させておくとメタライズ配線層9 の酸化腐食を
有効に防止することができるとともにメタライズ配線層
9 にボンディングワイヤ10及び外部リード端子11を強固
に取着させることができる。従って、前記メタライズ配
線層9 の表面にはニッケル、金等を1.0 乃至20.0μm の
厚みに層着させておくことが好ましい。
On the surface of the metallized wiring layer 9, a metal material having excellent corrosion resistance such as nickel (Ni) and gold (Au) and good conductivity is formed by plating to a thickness of 1.0 to 20.0 μm. The metallized wiring layer 9 can effectively prevent oxidative corrosion of the metallized wiring layer 9 when it is attached.
The bonding wire 10 and the external lead terminal 11 can be firmly attached to the 9. Therefore, it is preferable to deposit nickel, gold or the like on the surface of the metallized wiring layer 9 to a thickness of 1.0 to 20.0 μm.

【0026】また前記メタライズ配線層9 の一端にロウ
付けされる外部リード端子11はコバール金属や42アロイ
(Fe-Ni合金) 等の金属材料から成り、外部リード端子11
を外部電気回路に接続することによって内部に収容する
半導体素子4 はその電極が外部電気回路に電気的に接続
されることとなる。
The external lead terminal 11 brazed to one end of the metallized wiring layer 9 is made of Kovar metal or 42 alloy.
External lead terminal 11 made of metallic material such as (Fe-Ni alloy)
Is connected to an external electric circuit, the electrodes of the semiconductor element 4 housed inside are electrically connected to the external electric circuit.

【0027】前記外部リード端子11はコバール金属等の
インゴット( 塊) を圧延加工法や打ち抜き加工法等、従
来周知の金属加工法を採用することによって所定の板状
に形成され、その一端が銀ロウ等のロウ材を介し絶縁部
材3 のメタライズ配線層9 に取着される。尚、前記外部
リード端子11はその表面に耐蝕性に優れ、且つ良導電性
であるニッケル、金等をメッキ法により1.0 〜20.0μm
に層着させておくと外部リート端子11の酸化腐食を有効
に防止することができるとともに外部リード端子11を外
部電気回路に強固に接続させることができる。従って、
前記外部リード端子11はその表面にニッケル、金等を1.
0 乃至20.0μm の厚みに層着させておくことが好まし
い。
The external lead terminal 11 is formed into a predetermined plate shape by adopting a conventionally known metal processing method such as rolling method or punching method of an ingot (lump) of Kovar metal or the like, one end of which is silver. It is attached to the metallized wiring layer 9 of the insulating member 3 via a brazing material such as brazing. The surface of the external lead terminals 11 is 1.0 to 20.0 μm by plating with nickel, gold, etc., which has excellent corrosion resistance and good conductivity.
If it is layered on the outer lead terminal 11, the outer lead terminal 11 can be effectively prevented from being oxidized and corroded, and the outer lead terminal 11 can be firmly connected to the external electric circuit. Therefore,
The external lead terminal 11 has nickel, gold, etc. on its surface.
It is preferable that the layer is deposited to a thickness of 0 to 20.0 μm.

【0028】かくして本発明の半導体素子収納用パッケ
ージによれば枠部材2 に囲まれた金属基体1 表面に半導
体素子4 を接着材を介して固定するとともに半導体素子
4 の電極をボンディングワイヤ10を介して絶縁部材3 の
メタライズ配線層9 に接続し、しかる後、枠部材2 の上
部に蓋体12をロウ材等の封止材を介して接合させ、半導
体素子4 を気密に封止することによって最終製品として
半導体装置となる。
Thus, according to the package for accommodating semiconductor elements of the present invention, the semiconductor element 4 is fixed to the surface of the metal base 1 surrounded by the frame member 2 with an adhesive and the semiconductor element is
The electrode 4 is connected to the metallized wiring layer 9 of the insulating member 3 via the bonding wire 10, and then the lid 12 is joined to the upper portion of the frame member 2 via a sealing material such as a brazing material to form a semiconductor element. The final product is a semiconductor device by hermetically sealing 4

【0029】尚、本発明は上述の実施例に限定されるも
のではなく本発明の要旨を逸脱しない範囲であれば種々
の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the gist of the present invention.

【0030】[0030]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば金属基体をモリブデン板の上下両面に銅板を接合
させた3 層構造とするとともにモリブデン板の厚みをT
1、半導体素子の固定される上面側に位置する銅板の厚
みをT2、下面側に位置する銅板の厚みをT3とした
時、 T2/T1=1〜7で、且つ T3/T2=−T2/12T1+1〜−T2/12T1
+1.6 としたことから下側銅板、モリブデン板、上側銅板及び
枠部材を順次積層するとともにその各々を銀ロウ等のロ
ウ材で同時に接合させる際、金属基体に反りを発生する
ことなく金属基体の上面外周部に枠部材を取着すること
が可能となる。
According to the package for accommodating semiconductor elements of the present invention, the metal base has a three-layer structure in which copper plates are joined to the upper and lower surfaces of a molybdenum plate, and the thickness of the molybdenum plate is T.
1. When the thickness of the copper plate located on the upper surface side of the semiconductor element to be fixed is T2 and the thickness of the copper plate located on the lower surface side is T3, T2 / T1 = 1 to 7 and T3 / T2 = -T2 / 12T1 + 1 to -T2 / 12T1
Since it is +1.6, when the lower copper plate, the molybdenum plate, the upper copper plate and the frame member are sequentially laminated and they are simultaneously joined by a brazing material such as silver brazing, the metal substrate does not warp. It is possible to attach the frame member to the outer peripheral portion of the upper surface of the.

【0031】従って、本発明の半導体素子収納用パッケ
ージでは金属基体が平坦であることから半導体素子を金
属基体に強固に固定することができるとともに半導体素
子の発する熱を金属基体を介して大気中に良好に放出す
ることができる。
Therefore, in the package for housing a semiconductor element of the present invention, since the metal base is flat, the semiconductor element can be firmly fixed to the metal base and the heat generated by the semiconductor element is transferred to the atmosphere through the metal base. It can be released well.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す斜視図である。
FIG. 1 is a perspective view showing an embodiment of a semiconductor element housing package of the present invention.

【図2】図1に示すパッケージのX−X線断面図であ
る。
FIG. 2 is a sectional view taken along line XX of the package shown in FIG.

【符号の説明】[Explanation of symbols]

1・・・・金属基体 2・・・・枠部材 3・・・・絶縁部材 4・・・・半導体素子 5・・・・モリブデン板 6・・・・上側銅板 7・・・・下側銅板 9・・・・メタライズ配線層 11・・・・外部リード端子 1 ... Metal base 2 ... Frame member 3 ... Insulation member 4 ... Semiconductor element 5 ... Molybdenum plate 6 ... Upper copper plate 7 ... Lower copper plate 9 ... Metallized wiring layer 11 ... External lead terminals

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】酸化アルミニウム質焼結体から成る絶縁部
材を嵌着させた鉄合金製枠部材を金属基体の上面外周部
に取着させ、金属基体上面と枠部材とによって形成され
る空間内に半導体素子を固定収容するようになした半導
体素子収納用パッケージであって、前記金属基体はモリ
ブデン板の上下両面に銅板を接合させたものから成り、
且つモリブデン板の厚みをT1、半導体素子の固定され
る上面側に位置する銅板の厚みをT2、下面側に位置す
る銅板の厚みをT3とすると T2/T1=1〜7で、且つ T3/T2=−T2/12T1+1.3〜−T2/12
T1+1.6 であることを特徴とする半導体素子収納用パッケージ。
1. A space formed by an upper surface of a metal base and a frame member, wherein an iron alloy frame member fitted with an insulating member made of an aluminum oxide sintered body is attached to an outer periphery of an upper surface of the metal base. A semiconductor element housing package for fixedly housing a semiconductor element, wherein the metal base is formed by joining copper plates to upper and lower surfaces of a molybdenum plate,
Further, assuming that the thickness of the molybdenum plate is T1, the thickness of the copper plate located on the upper surface side where the semiconductor element is fixed is T2, and the thickness of the copper plate located on the lower surface side is T3, then T2 / T1 = 1 to 7, and T3 / T2 = -T2 / 12T1 + 1.3 to -T2 / 12
A package for housing a semiconductor element, which is T1 + 1.6.
JP3076592A 1992-02-18 1992-02-18 Semiconductor element containing package Pending JPH05226514A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3076592A JPH05226514A (en) 1992-02-18 1992-02-18 Semiconductor element containing package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3076592A JPH05226514A (en) 1992-02-18 1992-02-18 Semiconductor element containing package

Publications (1)

Publication Number Publication Date
JPH05226514A true JPH05226514A (en) 1993-09-03

Family

ID=12312784

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3076592A Pending JPH05226514A (en) 1992-02-18 1992-02-18 Semiconductor element containing package

Country Status (1)

Country Link
JP (1) JPH05226514A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011003718A (en) * 2009-06-18 2011-01-06 Toshiba Corp Semiconductor package
JP2011009370A (en) * 2009-06-24 2011-01-13 Toshiba Corp Fixture for semiconductor device and fixing structure thereof
JP2015192008A (en) * 2014-03-28 2015-11-02 京セラ株式会社 Semiconductor element housing package and semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011003718A (en) * 2009-06-18 2011-01-06 Toshiba Corp Semiconductor package
JP2011009370A (en) * 2009-06-24 2011-01-13 Toshiba Corp Fixture for semiconductor device and fixing structure thereof
JP2015192008A (en) * 2014-03-28 2015-11-02 京セラ株式会社 Semiconductor element housing package and semiconductor device

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