JP2746802B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2746802B2
JP2746802B2 JP4282732A JP28273292A JP2746802B2 JP 2746802 B2 JP2746802 B2 JP 2746802B2 JP 4282732 A JP4282732 A JP 4282732A JP 28273292 A JP28273292 A JP 28273292A JP 2746802 B2 JP2746802 B2 JP 2746802B2
Authority
JP
Japan
Prior art keywords
semiconductor element
concave portion
insulating base
semiconductor device
adhesive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP4282732A
Other languages
Japanese (ja)
Other versions
JPH06132420A (en
Inventor
祥司 植垣
慎吾 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4282732A priority Critical patent/JP2746802B2/en
Publication of JPH06132420A publication Critical patent/JPH06132420A/en
Application granted granted Critical
Publication of JP2746802B2 publication Critical patent/JP2746802B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子収納用パッケ
ージ内部に半導体素子を収容して成る半導体装置に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element housed in a semiconductor element housing package.

【0002】[0002]

【従来の技術】従来、コンピュータ等の情報処理装置に
は半導体素子を半導体素子収納用パッケージ内に気密に
収容した半導体装置が使用されている。
2. Description of the Related Art Conventionally, a semiconductor device in which a semiconductor element is hermetically housed in a semiconductor element housing package is used for an information processing apparatus such as a computer.

【0003】かかる情報処理装置に使用される半導体装
置は通常、図3 及び図4 に示すように、まずアルミナセ
ラミックス等の電気絶縁材料から成り、上面中央部に半
導体素子20を収容するための凹部21a 及び該凹部21a 周
辺から外周縁にかけて導出された複数個のメタライズ配
線層22を有する絶縁基体21と、半導体素子20を外部電気
回路に電気的に接続するために前記メタライズ配線層22
に銀ロウ等のロウ材を介し取着された外部リード端子23
と、蓋体24とから成る半導体素子収納用パッケージを準
備し、絶縁基体21の凹部21a 底面に半導体素子をガラ
ス、樹脂等の接着剤25を介して接着固定するとともに該
半導体素子20の各電極をボンディングワイヤ26を介して
メタライズ配線層22に接続し、しかる後、絶縁基体21上
面に蓋体24を封止材を介して接合させ,絶縁基体21と蓋
体24とから成る容器内部に半導体素子20を気密に収容す
ることによって半導体装置となる。
As shown in FIGS. 3 and 4, a semiconductor device used in such an information processing apparatus is usually made of an electrically insulating material such as alumina ceramics, and has a concave portion for accommodating a semiconductor element 20 in the center of the upper surface. An insulating base 21 having a plurality of metallized wiring layers 22 extending from the periphery of the recess 21a to the outer peripheral edge; and the metallized wiring layer 22 for electrically connecting the semiconductor element 20 to an external electric circuit.
External lead terminals 23 attached through a brazing material such as silver brazing
And a lid 24, a semiconductor element housing package is prepared, and the semiconductor element is adhered and fixed to the bottom surface of the concave portion 21a of the insulating base 21 via an adhesive 25 such as glass or resin, and the respective electrodes of the semiconductor element 20 are also fixed. Is connected to the metallized wiring layer 22 via bonding wires 26, and then a lid 24 is bonded to the upper surface of the insulating base 21 via a sealing material, and the semiconductor is placed inside the container formed of the insulating base 21 and the lid 24. A semiconductor device is obtained by housing the element 20 in an airtight manner.

【0004】尚、絶縁基体21の凹部21a 底面への半導体
素子20の接着固定は、一般に接着剤25としてガラスを使
用する場合、まずガラス粉末に適当な有機溶剤、溶媒を
添加混合して得たガラスペーストを絶縁基体21の凹部21
a 底面に塗布し、次に前記ガラスペースト上に半導体素
子20を載置させるとともにガラスペースを約450 ℃の温
度で加熱し、ガラスペースト中の有機溶剤、溶媒を飛散
させるとともにガラス粉末を溶融させることによって行
われる。
Incidentally, the bonding and fixing of the semiconductor element 20 to the bottom surface of the concave portion 21a of the insulating base 21 is generally performed by first adding a suitable organic solvent and a solvent to glass powder when glass is used as the adhesive 25. The glass paste is applied to the concave portion 21 of the insulating base 21.
a Apply to the bottom surface, then place the semiconductor element 20 on the glass paste and heat the glass paste at a temperature of about 450 ° C. to disperse the organic solvent and the solvent in the glass paste and melt the glass powder. This is done by:

【0005】[0005]

【発明が解決しようとする課題】しかしながら、近時、
半導体素子は高密度化、高集積化が急激に進み、その形
状が極めて大きなものとなり、これを従来の半導体素子
収納用パッケージに収容した場合、半導体素子が絶縁基
体の凹部底面の面積に対し90% 以上の面積を占め、凹部
側壁と半導体素子側面との間隔が極めて狭いものとなっ
てきた。そのため半導体素子収納用パッケージの絶縁基
体凹部底面に半導体素子を例えば、ガラスから成る接着
剤を用いて接着固定すると、ガラスペースト中に含まれ
ている有機溶剤、溶媒が絶縁基体の凹部側壁と半導体素
子の側面との間隔が狭いことに起因して外部に良好に飛
散されず接着剤中に包含され、その結果、半導体素子の
絶縁基体凹部底面に対する接着強度が極めて弱いものと
なり、外力印加によって容易に外れるという欠点を有し
ていた。
However, recently,
Semiconductor devices have rapidly increased in density and integration, and have become extremely large in shape. When the semiconductor device is housed in a conventional semiconductor device housing package, the semiconductor device has an area of 90% of the area of the bottom of the concave portion of the insulating base. %, And the gap between the side wall of the concave portion and the side surface of the semiconductor element has become extremely narrow. Therefore, when the semiconductor element is adhered and fixed to the bottom surface of the insulating base recess of the package for semiconductor element storage using, for example, an adhesive made of glass, the organic solvent and the solvent contained in the glass paste are removed from the side wall of the recess of the insulating base and the semiconductor element. Due to the small distance between the side surfaces of the semiconductor device, the semiconductor device is not scattered well and is included in the adhesive. As a result, the adhesive strength of the semiconductor element to the bottom surface of the concave portion of the insulating substrate becomes extremely weak, and the semiconductor device is easily squeezed by the application of external force. It had the disadvantage of coming off.

【0006】[0006]

【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は半導体素子収納用パッケージの絶縁基体
凹部底面に半導体素子を強固に接着固定し、半導体素子
を長期間にわたり正常、且つ安定に作動させることがで
きる半導体装置を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and has as its object to firmly adhere and fix a semiconductor element to the bottom surface of a concave portion of an insulating substrate of a package for housing a semiconductor element so that the semiconductor element can be normally used for a long time. Another object of the present invention is to provide a semiconductor device that can be operated stably.

【0007】[0007]

【課題を解決するための手段】本発明は表面に凹部を有
する絶縁基体と、前記凹部内に収容される半導体素子
と、前記凹部を塞ぐ蓋体とから成る半導体装置であっ
て、前記絶縁基体はその凹部底面の面積S1 が半導体素
子の平面積S2 に対しS2 ≧0.9S1 であり、且つ凹
部側壁に少なくとも1 つの切欠部が形成されていること
を特徴とするものである。
According to the present invention, there is provided a semiconductor device comprising an insulating base having a concave portion on the surface, a semiconductor element housed in the concave portion, and a lid for closing the concave portion. Is characterized in that the area S 1 of the bottom surface of the recess is S 2 ≧ 0.9S 1 with respect to the plane area S 2 of the semiconductor element, and at least one notch is formed in the side wall of the recess. .

【0008】[0008]

【作用】本発明の半導体装置によれば、半導体素子を収
容する絶縁基体の凹部側壁に切欠部を形成したことから
半導体素子の大きさが凹部底面の面積に対し90% 以上を
占める大きなものになったとしても凹部側壁と半導体素
子側面との間には広い間隙を形成することができ、その
結果、半導体素子を絶縁基体の凹部底面に接着剤を介し
て接着固定する際、接着剤から放出される有機溶剤、溶
媒は前記間隙を通して外部に良好に放散され、接着剤中
に包含されることは殆どなく、これによって半導体素子
を絶縁基体の凹部底面に極めて強固に接着固定すること
が可能となる。
According to the semiconductor device of the present invention, the size of the semiconductor element occupies 90% or more of the area of the bottom surface of the recess because the notch is formed in the side wall of the recess of the insulating base for housing the semiconductor element. Even if this occurs, a wide gap can be formed between the side wall of the concave portion and the side surface of the semiconductor element. As a result, when the semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating base via an adhesive, the semiconductor element is released from the adhesive. The organic solvent and the solvent are satisfactorily radiated to the outside through the gap, and are hardly included in the adhesive. This makes it possible to bond and fix the semiconductor element to the bottom surface of the concave portion of the insulating base very strongly. Become.

【0009】[0009]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図1 及び図2 は本発明の半導体装置の一実施例を示
し、1 は絶縁基体、2 は蓋体、3 は半導体素子である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and 2 show one embodiment of the semiconductor device of the present invention, wherein 1 is an insulating base, 2 is a lid, and 3 is a semiconductor element.

【0010】前記絶縁基体1 は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体、ガラスーセラミックス焼結体等の電気
絶縁材料から成り、その上面中央部に半導体素子3 を収
容する空所を形成するための凹部1aが形成されている。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, a glass-ceramic sintered body, etc. A concave portion 1a for forming a space for accommodating the semiconductor element 3 is formed in the center of the upper surface.

【0011】前記絶縁基体1 は例えば、酸化アルミニウ
ム質焼結体から成る場合、アルミナ(Al 2 O 3 ) 、シリ
カ(SiO2 ) 、カルシア(CaO) 、マグネシア(MgO) 等の原
料粉末に適当な有機溶剤、溶媒を添加混合して泥漿状と
なすとともにこれを従来周知のドクターブレード法やカ
レンダーロール法等を採用することによってセラミック
グリーンシート( セラミック生シート) を得、しかる
後、前記セラミックグリーンシートに適当な打ち抜き加
工を施すとともにこれを複数枚積層し、高温( 約1600
℃) で焼成することによって製作される。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, it is suitable for a raw material powder such as alumina (Al 2 O 3 ), silica (SiO 2 ), calcia (CaO), and magnesia (MgO). An organic solvent, a solvent is added and mixed to form a slurry, and a ceramic green sheet (ceramic green sheet) is obtained by adopting a conventionally known doctor blade method, calender roll method, or the like. In addition to performing appropriate punching processing, and laminating a plurality of these, high temperature (about 1600
(° C).

【0012】また前記絶縁基体1 に形成した凹部1aには
その底面に半導体素子3 がガラス、樹脂等の接着剤4 を
介して固定され、これによって凹部1a内に半導体素子3
が収容される。
A semiconductor element 3 is fixed to the bottom of the recess 1a formed in the insulating base 1 via an adhesive 4 such as glass, resin or the like.
Is accommodated.

【0013】前記絶縁基体1 の凹部1a底面への半導体素
子3 の接着固定は例えば、接着剤4がガラスから成る場
合、まず銀粉末を70乃至90重量%含有するガラス粉末に
適当な有機溶剤、溶媒を添加混合してガラスペーストを
作り、次に前記ガラスペーストを絶縁基体1 の凹部1a底
面に所定厚みに被着するとともに該ガラスペースト上に
半導体素子3 を載置させ、しかる後、前記ガラスペース
トを約450 ℃の温度が加熱し、ガラスペースト中の有機
溶剤、溶媒を外部に飛散させるとともにガラス粉末を加
熱溶融させることによって行われる。
For example, when the adhesive 4 is made of glass, an organic solvent suitable for a glass powder containing 70 to 90% by weight of silver powder is used for bonding and fixing the semiconductor element 3 to the bottom surface of the concave portion 1a of the insulating base 1. A solvent is added and mixed to form a glass paste, and then the glass paste is applied to the bottom surface of the concave portion 1a of the insulating substrate 1 to a predetermined thickness, and the semiconductor element 3 is placed on the glass paste. The paste is heated at a temperature of about 450 ° C. to disperse the organic solvent and the solvent in the glass paste to the outside and heat and melt the glass powder.

【0014】前記絶縁基体1はまたその凹部1a側壁に
は上面に開口する複数個の切欠部1bが形成されてお
り、該切欠部1bは絶縁基体1の凹部1a内に収容する
半導体素子3の大きさが凹部1a底面の面積に対し90
%以上の大きなものになったとしても凹部1a側壁と半
導体素子3側面との間に広い間隙を形成する作用をな
し、これによって半導体素子3を絶縁基体1の凹部1a
底面に接着剤4を介して接着固定する際、接着剤4から
有機溶剤、溶媒が放出されたとしても、該有機溶剤等は
前記間隙を通して外部に良好に放散され接着剤4中に包
含されることは殆どなく、その結果、半導体素子3を絶
縁基体1の凹部1a底面に極めて強固に接着固定するこ
とが可能となる。
The insulating substrate 1 has a plurality of cutouts 1b formed on the side wall of the concave portion 1a, and the cutout portion 1b is formed in the concave portion 1a of the insulating base 1. The size is 90 with respect to the area of the bottom of the concave portion 1a.
% Or more, a large gap is formed between the side wall of the concave portion 1a and the side surface of the semiconductor element 3, whereby the semiconductor element 3 is separated from the concave portion 1a of the insulating base 1.
When the organic solvent and the solvent are released from the adhesive 4 when the adhesive is fixed to the bottom surface with the adhesive 4, the organic solvent and the like are satisfactorily radiated to the outside through the gap and included in the adhesive 4. As a result, the semiconductor element 3 can be extremely firmly bonded and fixed to the bottom surface of the concave portion 1a of the insulating base 1.

【0015】尚、前記凹部1a側壁の切欠部1bは、複数枚
のセラミックグリーンシートを積層焼成して絶縁基体1
を得る際、各セラミックグリーンシートの凹部側壁に対
応する位置に予め打ち抜き加工法により切欠を形成して
おくことによって絶縁基体1の凹部1a側壁に所定形状に
形成される。
The notch 1b on the side wall of the recess 1a is formed by laminating and firing a plurality of ceramic green sheets.
When the substrate is obtained, a notch is formed in advance at a position corresponding to the concave side wall of each ceramic green sheet by a punching method, so that a predetermined shape is formed on the side wall of the concave portion 1a of the insulating base 1.

【0016】また前記絶縁基体1 はその凹部1a周辺から
外周縁にかけて複数個のメタライズ配線層5 が被着形成
されており、該メタライズ配線層5 の凹部1a周辺部には
半導体素子3 の各電極がボンディングワイヤ6 を介して
電気的に接続され、また絶縁基体1 の外周縁に導出され
た部位には外部電気回路と接続される外部リード端子7
が銀ロウ等のロウ材を介し取着されている。
A plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery of the concave portion 1a to the outer peripheral edge thereof. Each electrode of the semiconductor element 3 is provided around the concave portion 1a of the metallized wiring layer 5. Are electrically connected via bonding wires 6 and external lead terminals 7 connected to an external electric circuit are provided at portions led out to the outer peripheral edge of the insulating base 1.
Is attached via a brazing material such as silver brazing.

【0017】前記メタライズ配線層5 はタングステン、
モリブデン、マンガン等の高融点金属粉末から成り、該
高融点金属粉末に適当な有機溶剤、溶媒を添加混合して
得た金属ペーストを従来周知のスクリーン印刷法等の厚
膜手法を採用し、絶縁基体1となるセラミックグリーン
シートに予め所定パターンに印刷塗布しておくことによ
って絶縁基体1 の凹部1a周辺から外周縁にかけて被着形
成される。
The metallized wiring layer 5 is made of tungsten,
A metal paste obtained by adding a suitable organic solvent and a solvent to the high melting point metal powder, such as molybdenum, manganese, etc., is applied to the metal paste by using a conventionally known thick film method such as a screen printing method. By printing and applying a predetermined pattern on a ceramic green sheet serving as the base 1 in advance, the insulating green base 1 is adhered and formed from the periphery of the concave portion 1a to the outer peripheral edge.

【0018】尚、前記メタライズ配線層5 はその露出す
る表面にニッケル、金等の耐蝕性に優れ、且つ良導電性
の金属をメッキ法により1.0 乃至20.0μm の厚みに層着
させておくとメタライズ配線層5 が酸化腐食するのを有
効に防止することができるとともにメタライズ配線層5
とボンディングワイヤ6 との接続及びメタライズ配線層
5 に対する外部リード端子7 のロウ付けを強固となすこ
とができる。従って、前記メタライズ配線層5 が酸化腐
食するのを有効に防止するとともにメタライズ配線層5
とボンディングワイヤ6 との接続、メタライズ配線層5
と外部リード端子7 とのロウ付けを強固とするにはメタ
ライズ配線層5 の露出表面にニッケル、金等の耐蝕性に
優れ、且つ良導電性の金属をメッキ法により0.1 乃至2
0.0μm の厚みに層着させておくことが好ましい。
The metallized wiring layer 5 is formed by plating a metal having excellent corrosion resistance such as nickel and gold and having good conductivity with a thickness of 1.0 to 20.0 μm on the exposed surface by plating. The wiring layer 5 can be effectively prevented from being oxidized and corroded, and the metallized wiring layer 5 can be prevented.
Between metallization and bonding wire 6 and metallized wiring layer
The soldering of the external lead terminal 7 to the terminal 5 can be made firm. Therefore, the metallized wiring layer 5 is effectively prevented from being oxidized and corroded, and the metallized wiring layer 5 is
Connection with bonding wire 6, metallized wiring layer 5
In order to strengthen the brazing between the metallization wiring layer 5 and the external lead terminal 7, a metal having excellent corrosion resistance such as nickel or gold and a good conductive metal is plated on the exposed surface of the metallized wiring layer 5 by 0.1 to 2 mm.
It is preferable to coat the layer to a thickness of 0.0 μm.

【0019】また前記メタライズ配線層5 には外部リー
ド端子7 が銀ロウ等のロウ材を介して取着されており、
該外部リード端子7 は内部に収容する半導体素子3 を外
部電気回路に電気的に接続する作用を為し、外部リード
端子7 を外部電気回路に接続することによって内部に収
容される半導体素子3 はメタライズ配線層5 及び外部リ
ード端子7 を介し外部電気回路と電気的に接続されるこ
ととなる。
External lead terminals 7 are attached to the metallized wiring layer 5 via a brazing material such as silver brazing.
The external lead terminal 7 functions to electrically connect the semiconductor element 3 housed therein to an external electric circuit, and the semiconductor element 3 housed inside by connecting the external lead terminal 7 to an external electric circuit is formed. It is electrically connected to an external electric circuit via the metallized wiring layer 5 and the external lead terminals 7.

【0020】前記外部リード端子7 はコバール金属( 鉄
ーニッケルーコバルト合金) や42アロイ( 鉄ーニッケル
合金) 等から成り、例えばコバール金属等のインゴット
( 塊) を圧延加工法や打ち抜き加工法等、従来周知の金
属加工法を採用することによって所定の板状に形成され
る。
The external lead terminals 7 are made of Kovar metal (iron-nickel-cobalt alloy), 42 alloy (iron-nickel alloy), or the like.
The (mass) is formed into a predetermined plate shape by employing a conventionally known metal working method such as a rolling method or a punching method.

【0021】更に前記絶縁基体1 はその上面に蓋体2
が、絶縁基体1 の凹部1aを塞ぐようにガラス、樹脂等の
封止材を介して接合され、絶縁基体1 と蓋体2 とから成
る容器内部に半導体素子3 が気密に収容されて製品とし
ての半導体装置となる。
Further, the insulating substrate 1 has a lid 2 on its upper surface.
Are bonded via a sealing material such as glass or resin so as to cover the concave portion 1a of the insulating base 1, and the semiconductor element 3 is hermetically housed inside a container formed of the insulating base 1 and the lid 2 to form a product. Semiconductor device.

【0022】前記絶縁基体1 の上面に接合される蓋体2
は酸化アルミニウム質焼結体等の電気絶縁材料やコバー
ル金属等の金属材料から成り、該蓋体2 は半導体素子3
を気密に塞ぐ作用を為す。
A lid 2 joined to the upper surface of the insulating base 1
Is made of an electrical insulating material such as an aluminum oxide sintered body or a metal material such as Kovar metal.
Acts to seal airtightly.

【0023】かくして本発明の半導体装置は外部リード
端子7 を外部電気回路に接続させ、内部の半導体素子3
を外部電気回路に接続することによってコンピュータ等
の情報処理装置に搭載されることとなる。
Thus, in the semiconductor device of the present invention, the external lead terminal 7 is connected to the external electric circuit, and the internal semiconductor element 3
Is connected to an external electric circuit to be mounted on an information processing apparatus such as a computer.

【0024】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば上述の実施例では絶縁基
体1の凹部1a底面に半導体素子3 をガラスから成る接着
剤4 で接着固定したが、銀粉末を含むエポキシ樹脂等の
樹脂から成る接着剤を使用する場合にも適用可能であ
る。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. Although the semiconductor element 3 is bonded and fixed to the bottom surface of the substrate 1a with an adhesive 4 made of glass, the present invention can be applied to a case where an adhesive made of a resin such as an epoxy resin containing silver powder is used.

【0025】[0025]

【発明の効果】本発明の半導体装置によれば、半導体素
子を収容する絶縁基体の凹部側壁に切欠部を形成したこ
とから半導体素子の大きさが凹部底面の平面積に対し90
% 以上を占める大きなものになったとしても凹部側壁と
半導体素子側面との間には広い間隙を形成することがで
き、その結果、半導体素子を絶縁基体の凹部底面に接着
剤を介して接着固定する際、接着剤から放出される有機
溶剤、溶媒は前記間隙を通して外部に良好に放散され、
接着剤中に包含されることは殆どなく、これによって半
導体素子を絶縁基体の凹部底面に極めて強固に接着固定
することが可能となる。
According to the semiconductor device of the present invention, since the notch is formed in the side wall of the concave portion of the insulating base for accommodating the semiconductor element, the size of the semiconductor element is 90% of the flat area of the bottom surface of the concave portion.
%, A wide gap can be formed between the side wall of the recess and the side surface of the semiconductor element even when the semiconductor element becomes large. As a result, the semiconductor element is bonded and fixed to the bottom of the recess of the insulating base via an adhesive. When doing, the organic solvent released from the adhesive, the solvent is satisfactorily diffused to the outside through the gap,
It is hardly included in the adhesive, which allows the semiconductor element to be extremely firmly bonded and fixed to the bottom of the concave portion of the insulating base.

【0026】よって、本発明の半導体装置では半導体素
子が絶縁基体の凹部底面に強固に接着固定されているこ
とから半導体素子に外力が印加されても該半導体素子は
絶縁基体の凹部底面より外れることは一切なく、半導体
素子を長期間わたり正常、且つ安定に作動させことがで
きる。
Therefore, in the semiconductor device of the present invention, since the semiconductor element is firmly adhered and fixed to the bottom of the concave portion of the insulating base, the semiconductor element is separated from the bottom of the concave portion of the insulating base even when an external force is applied to the semiconductor element. And the semiconductor element can be operated normally and stably for a long period of time.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体装置の一実施例を示す断面図で
ある。
FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

【図2】図1に示す半導体装置の要部拡大平面図であ
る。
FIG. 2 is an enlarged plan view of a main part of the semiconductor device shown in FIG.

【図3】従来の半導体装置の断面図である。FIG. 3 is a cross-sectional view of a conventional semiconductor device.

【図4】図3 に示す半導体装置の要部拡大平面図であ
る。
FIG. 4 is an enlarged plan view of a main part of the semiconductor device shown in FIG. 3;

【符号の説明】[Explanation of symbols]

1・・・・・絶縁基体 1a・・・・凹部 1b・・・・切欠部 2・・・・・蓋体 3・・・・・半導体素子 4・・・・・接着剤 1 ... Insulating base 1a ... Recess 1b ... Notch 2 ... Lid 3 ... Semiconductor element 4 ... Adhesive

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】表面に凹部を有する絶縁基体と、前記凹部
内に収容される半導体素子と、前記凹部を塞ぐ蓋体とか
ら成る半導体装置であって、前記絶縁基体はその凹部底
面の面積S1 が半導体素子の平面積S2 に対しS2
0.9S1 であり、かつ凹部側壁に、該凹部の底面より
上面にかけて連通する少なくと1つの切欠部が形成され
ていることを特徴とする半導体装置。
1. A semiconductor device comprising: an insulating base having a concave portion on its surface; a semiconductor element housed in the concave portion; and a lid for closing the concave portion, wherein the insulating base has an area S of a bottom surface of the concave portion. S 21 Whereas plane area S 2 of the semiconductor element
It is 0.9 S 1, and the recess sidewall, the bottom surface of the recess
A semiconductor device, wherein at least one notch communicating with the upper surface is formed.
JP4282732A 1992-10-21 1992-10-21 Semiconductor device Expired - Fee Related JP2746802B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4282732A JP2746802B2 (en) 1992-10-21 1992-10-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4282732A JP2746802B2 (en) 1992-10-21 1992-10-21 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH06132420A JPH06132420A (en) 1994-05-13
JP2746802B2 true JP2746802B2 (en) 1998-05-06

Family

ID=17656328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4282732A Expired - Fee Related JP2746802B2 (en) 1992-10-21 1992-10-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2746802B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61247057A (en) * 1985-04-24 1986-11-04 Nec Corp Semiconductor device
JPH01241828A (en) * 1988-03-23 1989-09-26 Mitsubishi Electric Corp Semiconductor package

Also Published As

Publication number Publication date
JPH06132420A (en) 1994-05-13

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