JP3406710B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP3406710B2 JP3406710B2 JP28783794A JP28783794A JP3406710B2 JP 3406710 B2 JP3406710 B2 JP 3406710B2 JP 28783794 A JP28783794 A JP 28783794A JP 28783794 A JP28783794 A JP 28783794A JP 3406710 B2 JP3406710 B2 JP 3406710B2
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- lead terminals
- semiconductor element
- connecting member
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。
【０００２】
【従来の技術】従来、ＬＳＩ（大規模集積回路素子）等
の半導体素子を収容する半導体素子収納用パッケージは
一般に、図３及び図４に示すように酸化アルミニウム質
焼結体等の電気絶縁材料から成り、上面に半導体素子Ｓ
を収容するための凹部及び該凹部周辺から外周縁にかけ
て導出するタングステン、モリブデン、マンガン等の高
融点金属粉末から成る複数個のメタライズ配線層12を有
する絶縁基体11と、半導体素子Ｓの各電極を外部電気回
路に接続するために前記メタライズ配線層12にその一端
を絶縁基体11の側辺より外側に突出するようにして銀ロ
ウ等のロウ材を介し取着された鉄−ニッケル−コバルト
合金や鉄−ニッケル合金等から成る複数個の外部リード
端子13と蓋体14とから構成されており、絶縁基体11の凹
部底面に半導体素子Ｓをガラス、樹脂、ロウ材等の接着
剤を介して接着固定するとともに半導体素子Ｓの各電極
をメタライズ配線層12にボンディングワイヤ15を介して
電気的に接続し、しかる後、絶縁基体11の上部に蓋体14
をガラス、樹脂、ロウ材等の封止材を介して接合させ、
絶縁基体11と蓋体14とから成る容器内部に半導体素子Ｓ
を気密に収容することによって最終製品としての半導体
装置となる。
【０００３】尚、上記半導体素子収納用パッケージにお
いては、各外部リード端子13の絶縁基体11側辺より外側
に突出する部位がセラミック、ガラス等の電気絶縁性材
料より成る連結部材16に隣接間隔を均等として連結され
ており、連結部材16で隣接する外部リード端子13間の間
隔を一定に維持するとともに外力印加よる外部リード端
子13の大きな変形を防止することによって隣接する外部
リード端子13間の電気的短絡を有効に阻止している。ま
た前記連結部材16は各外部リード端子13を電気的に独立
した状態で支持し、各外部リード端子13に電気的検査装
置のプローブを接触させて容器内部に収容する半導体素
子Ｓの電気特性をチェックする際、その特性チェックの
作業性を良好なものとしている。
【０００４】
【発明が解決しようとする課題】しかしながら、近時、
半導体素子は高密度化、高集積化が急激に進み、該半導
体素子を収容する半導体素子収納用パッケージも外部リ
ード端子の数が急増し、隣接する外部リード端子の間隔
が0.5mm 以下という狭いものになってきたこと、及び従
来の半導体素子収納用パッケージは外部リード端子の連
結部材での隣接間隔が絶縁基体側辺での隣接間隔と同じ
であること等から外部リード端子の連結部材での隣接間
隔が0.5mm 以下という極めて狭いものになってきてお
り、そのため連結部材に電気的に独立した状態で連結さ
れている各外部リード端子に電気的検査装置のプローブ
を接触させて半導体素子収納用パッケージの容器内部に
収容される半導体素子の電気特性をチェックする際、各
外部リード端子の隣接間隔が狭いためプローブが隣接す
る外部リード端子に接触して容器内部に収容する半導体
素子の電気的特性を正確にチェックすることができない
という欠点を招来した。
【０００５】
【発明の目的】本発明は上記欠点に鑑み案出されたもの
で、その目的は隣接する外部リード端子間の電気的短絡
を有効に阻止し、且つ内部に収容する半導体素子の電気
的特性を正確にチェックすることができる半導体素子収
納用パッケージを提供することにある。
【０００６】
【課題を解決するための手段】本発明は、半導体素子を
収容する容器の側辺より複数個の外部リード端子を隣接
間隔を均等として突出させるとともに、該突出する外部
リード端子を各側辺毎に前記側辺に平行に配置したセラ
ミックスまたはガラスから成る電気絶縁性の連結部材で
隣接間隔を均等として連結させて成り、前記外部リード
端子の連結部材での隣接間隔を容器側辺での隣接間隔よ
り広くして、前記外部リード端子の下側を前記連結部材
に接着固定したことを特徴とする。
【０００７】
【作用】本発明の半導体素子収納用パッケージによれ
ば、半導体素子を収容する容器の側辺より外側に突出す
る外部リード端子を電気絶縁性材料より成る連結部材で
連結させたことから隣接する外部リード端子間の間隔は
常に一定に維持され、且つ外力印加よる外部リード端子
の大きな変形が防止されて、隣接する外部リード端子間
の電気的短絡を有効に阻止することが可能となる。
【０００８】また本発明の半導体素子収納用パッケージ
によれば、外部リード端子の連結部材での隣接間隔を容
器側辺での隣接間隔より広いものとなしたことから外部
リード端子の数が急増し、容器側辺での外部リード端子
の隣接間隔が狭くなったとしても連結部材での外部リー
ド端子の隣接間隔を広いものとなすことができ、その結
果、連結部材に電気的に独立した状態で連結されている
各外部リード端子に電気的検査装置のプローブを正確に
接触させて半導体素子収納用パッケージの容器内部に収
容されている半導体素子の電気特性を正確にチェックす
ることも可能となる。
【０００９】
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図１及び図２は本発明の半導体素子収納用パッケー
ジの一実施例を示し、1 は絶縁基体、2 は蓋体である。
この絶縁基体1 と蓋体2 とで半導体素子3 を収容するた
めの容器4 が構成される。
【００１０】前記絶縁基体1 は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体等の電気絶縁材料から成り、その上面に
凹部1aを有し、該凹部1a底面には半導体素子3 がガラ
ス、樹脂、ロウ材等の接着剤を介して接着固定される。
【００１１】前記酸化アルミニウム質焼結体から成る絶
縁基体1 は例えば、アルミナ(Al 2O 3 ) 、シリカ(SiO
2 ) 、カルシア(CaO) 、マグネシア(MgO) 等の原料粉末
に適当な有機溶剤、溶媒を添加混合して泥漿状となすと
ともにこれを従来周知のドクターブレード法やカレンダ
ーロール法等を採用することによってセラミックグリー
ンシート( セラミック生シート) を得、しかる後、前記
セラミックグリーンシートに適当な打ち抜き加工を施す
とともに複数枚積層し、高温( 約1600℃) で焼成するこ
とによって製作される。
【００１２】また前記絶縁基体1 は凹部1a周辺から外周
縁にかけて複数個のメタライズ配線層5 が被着形成され
ており、該メタライズ配線層5 の凹部1a周辺部には半導
体素子3 の各電極がボンディングワイヤ6 を介して電気
的に接続され、また絶縁基体1 の外周縁に導出された部
位には外部電気回路と接続される外部リード端子7 がそ
の一端を絶縁基体1 の側辺より外側に突出するようにし
て銀ロウ等のロウ材を介して取着されている。
【００１３】前記メタライズ配線層5 はタングステン、
モリブデン、マンガン等の高融点金属粉末から成り、該
タングステン等の高融点金属粉末に適当な有機溶剤、溶
媒を添加混合して得た金属ペーストを絶縁基体1 となる
セラミックグリーンシートに予め従来周知のスクリーン
印刷法により所定パターンに印刷塗布しておくことによ
って絶縁基体1 の凹部1a周辺から外周縁にかけて被着さ
れる。
【００１４】尚、前記メタライズ配線層5 はその露出表
面にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ
性の良い金属をメッキ法により1.0 乃至20.0μm の厚み
に層着させておくとメタライズ配線層5 の酸化腐食を有
効に防止することができるとともにメタライズ配線層5
とボンディングワイヤ6 との接続及びメタライズ配線層
5 への外部リード端子7 の取着を強固となすことができ
る。従って、前記メタライズ配線層5 の酸化腐食を防止
し、メタライズ配線層5 とボンディングワイヤ6 及び外
部リード端子7 との取着を強固とするにはメタライズ配
線層5 の露出表面にニッケル、金等を1.0 乃至20.0μm
の厚みに層着させておくことが好ましい。
【００１５】また前記メタライズ配線層5に銀ロウ等の
ロウ材を介して取着される外部リード端子7は鉄−ニッ
ケル−コバルト合金や鉄−ニッケル合金等の金属材料か
ら成り、外部リード端子7を外部電気回路に接続するこ
とによって絶縁基体1の凹部1a内に収容される半導体素
子3の各電極はメタライズ配線層5及び外部リード端子7
を介して外部電気回路に電気的に接続されることとな
る。
【００１６】前記外部リード端子7は鉄−ニッケル−コ
バルト合金等のインゴット(塊)を圧延加工法や打ち抜き
加工法等、従来周知の金属加工法を採用することによっ
て所定の形状に形成される。
【００１７】前記外部リード端子7 はまたその露出表面
にニッケル、金等の耐蝕性に優れ、且つロウ材と濡れ性
の良い金属をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくと外部リード端子7 の酸化腐食を有効に
防止することができるとともに外部リード端子7 を半田
等のロウ材を介し外部電気回路に強固に接続することが
可能となる。従って、前記外部リード端子7 はその露出
表面にニッケル、金等を1.0 乃至20.0μm の厚みに層着
させておくことが好ましい。
【００１８】更に前記外部リード端子7 は絶縁基体1 の
側辺より外側に突出する一端側が電気絶縁性材料から成
る連結部材8 に各々、電気的に独立した状態で連結され
ており、これによって各外部リード端子7 は隣接する外
部リード端子7 間の間隔が常に一定に維持され、且つ外
力印加よる外部リード端子7 の大きな変形が有効に防止
されて、隣接する外部リード端子7 間の電気的短絡を有
効に阻止することができる。また同時に各外部リード端
子7 は連結部材8 に電気的に独立した状態で支持される
ことから各外部リード端子7 に電気的検査装置のプロー
ブを接触させ、容器4 内部に収容される半導体素子3 の
電気特性をチェックする際、その特性チェックの作業性
が極めて良好なものとなる。
【００１９】また更に前記外部リード端子7 は絶縁基体
1 側辺における隣接間隔に対して連結部材8 における隣
接間隔が広いものとなっている。そのため連結部材8 に
電気的に独立した状態で連結されている各外部リード端
子7 に電気的検査装置のプローブを接触させて容器4 内
部に収容される半導体素子3 の電気特性をチェックする
際、各外部リード端子7 に電気的検査装置のプローブを
正確に接触させて半導体素子3 の電気特性を正確にチェ
ックすることもできる。
【００２０】前記外部リード端子7 を連結する連結部材
8 としては例えば、酸化アルミニウム質焼結体等のセラ
ミックスやガラス等の電気絶縁性材料で形成され、連結
部材8 への外部リード端子7 の連結は各外部リード端子
7 を連結部材にガラスや樹脂、ロウ材等、適当な接着剤
で接着固定することによって行われる。
【００２１】かくして、本発明の半導体素子収納用パッ
ケージによれば絶縁基体1 の凹部1a底面に半導体素子3
をガラス、樹脂、ロウ材等の接着剤を介して接着固定す
るとともに半導体素子3 の各電極をメタライズ配線層5
にボンディングワイヤ6 を介して電気的に接続し、しか
る後、絶縁基体1 の上面に蓋体2 をガラス、樹脂、ロウ
材等から成る封止材を介して接合させ、絶縁基体1 と蓋
体2 とから成る容器4内部に半導体素子3 を気密に収容
することによって製品としての半導体装置が完成する。
【００２２】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能である。
【００２３】
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、半導体素子を収容する容器の側辺より外側に突
出する外部リード端子を電気絶縁性材料より成る連結部
材で連結させたことから隣接する外部リード端子間の間
隔は常に一定に維持され、且つ外力印加よる外部リード
端子の大きな変形が防止されて、隣接する外部リード端
子間の電気的短絡を有効に阻止することが可能となる。
【００２４】また本発明の半導体素子収納用パッケージ
によれば、外部リード端子の連結部材での隣接間隔を容
器側辺での隣接間隔より広いものとなしたことから外部
リード端子の数が急増し、容器側辺での外部リード端子
の隣接間隔が狭くなったとしても連結部材での外部リー
ド端子の隣接間隔を広いものとなすことができ、その結
果、連結部材に電気的に独立した状態で連結されている
各外部リード端子に電気的検査装置のプローブを正確に
接触させて半導体素子収納用パッケージの容器内部に収
容されている半導体素子の電気特性を正確にチェックす
ることも可能となる。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device. 2. Description of the Related Art Conventionally, a package for accommodating a semiconductor element such as an LSI (Large Scale Integrated Circuit) is generally made of aluminum oxide sintered body or the like as shown in FIGS. It is made of an electrically insulating material and has a semiconductor element S
The insulating base 11 having a plurality of metallized wiring layers 12 made of a refractory metal powder such as tungsten, molybdenum, manganese, etc. derived from the concave portion for accommodating the concave portion to the outer peripheral edge thereof, and the respective electrodes of the semiconductor element S An iron-nickel-cobalt alloy attached to the metallized wiring layer 12 via a brazing material such as silver brazing so that one end of the metallized wiring layer 12 projects outside the side of the insulating base 11 for connection to an external electric circuit; The semiconductor device S is composed of a plurality of external lead terminals 13 made of an iron-nickel alloy or the like and a lid 14, and adheres the semiconductor element S to the bottom surface of the concave portion of the insulating base 11 via an adhesive such as glass, resin, or brazing material. At the same time, each electrode of the semiconductor element S is electrically connected to the metallized wiring layer 12 via a bonding wire 15.
Is bonded through a sealing material such as glass, resin, brazing material,
A semiconductor element S is provided inside a container comprising an insulating base 11 and a lid 14.
Is airtightly accommodated to form a semiconductor device as a final product. In the package for housing a semiconductor element, a portion of each external lead terminal 13 projecting outward from the side of the insulating substrate 11 is adjacent to a connecting member 16 made of an electrically insulating material such as ceramic or glass. The connection between the adjacent external lead terminals 13 is uniform, and the distance between the adjacent external lead terminals 13 is kept constant by the connecting member 16 and the external lead terminals 13 are prevented from largely deforming due to the application of external force. The effective short circuit is effectively prevented. Further, the connecting member 16 supports each external lead terminal 13 in an electrically independent state, and makes a probe of an electrical inspection device contact each external lead terminal 13 to improve the electrical characteristics of the semiconductor element S housed inside the container. When checking, the workability of the characteristic check is made favorable. [0004] However, recently,
Semiconductor devices are rapidly becoming denser and more highly integrated, and the number of external lead terminals is also increasing rapidly, and the distance between adjacent external lead terminals is as narrow as 0.5 mm or less. And the conventional semiconductor element storage package has the same distance between adjacent external lead terminals at the connecting member as the adjacent distance at the side of the insulating substrate. The spacing is becoming extremely narrow, less than 0.5mm, so the probe of the electrical inspection device is brought into contact with each external lead terminal that is electrically connected to the connecting member in a state of being electrically independent. When checking the electrical characteristics of a semiconductor device housed inside a container, the probe contacts the adjacent external lead terminal because the space between adjacent external lead terminals is small. The electrical characteristics of the semiconductor element housed in the container Te was lead to disadvantages in that it is impossible to accurately check. SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and has as its object to effectively prevent an electric short circuit between adjacent external lead terminals and to reduce the electric current of a semiconductor element housed therein. It is an object of the present invention to provide a package for accommodating a semiconductor element capable of accurately checking a characteristic. According to the present invention, a plurality of external lead terminals are made to protrude from a side of a container for accommodating a semiconductor element at equal intervals, and each of the protruding external lead terminals is connected to a corresponding one of the terminals. The adjacent gaps are connected equally with an electrically insulating connecting member made of ceramics or glass arranged in parallel with the side for each side, and the adjacent gap in the connecting member of the external lead terminal is defined by the container side. And the lower side of the external lead terminal is adhesively fixed to the connecting member. According to the semiconductor device housing package of the present invention, the external lead terminals projecting outward from the sides of the container housing the semiconductor device are connected by the connecting member made of an electrically insulating material. The distance between adjacent external lead terminals is always kept constant, and large deformation of the external lead terminals due to the application of external force is prevented, so that an electrical short circuit between adjacent external lead terminals can be effectively prevented. . Further, according to the package for accommodating a semiconductor element of the present invention, since the interval between adjacent external lead terminals at the connecting member is wider than the adjacent interval at the side of the container, the number of external lead terminals increases rapidly. Therefore, even if the distance between the adjacent external lead terminals on the side of the container is reduced, the distance between the adjacent external lead terminals on the connecting member can be increased, and as a result, the connecting member can be electrically isolated. It is also possible to accurately check the electrical characteristics of the semiconductor device housed inside the container of the semiconductor device housing package by accurately bringing the probe of the electrical inspection device into contact with each connected external lead terminal. The present invention will be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a package for housing a semiconductor element according to the present invention, wherein 1 is an insulating base and 2 is a lid.
The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3. The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, an aluminum nitride sintered body, and has a concave portion 1a on its upper surface. The semiconductor element 3 is bonded and fixed to the bottom surface of the concave portion 1a via an adhesive such as glass, resin, brazing material or the like. The insulating substrate 1 made of the aluminum oxide sintered body is made of, for example, alumina (Al 2 O 3 ), silica (SiO 2 ).
2 ) Add a suitable organic solvent and solvent to the raw material powders such as calcia (CaO) and magnesia (MgO) to form a slurry by mixing and using a conventionally known doctor blade method or calendar roll method. Thus, a ceramic green sheet (ceramic green sheet) is obtained. Thereafter, the ceramic green sheet is subjected to an appropriate punching process, a plurality of sheets are laminated, and fired at a high temperature (about 1600 ° C.). A plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery of the concave portion 1a to the outer peripheral edge, and each electrode of the semiconductor element 3 is formed around the concave portion 1a of the metallized wiring layer 5. An external lead terminal 7 electrically connected via a bonding wire 6 and connected to an external electric circuit at a portion led out to the outer peripheral edge of the insulating base 1 has one end thereof outside the side of the insulating base 1. It is attached via a brazing material such as silver brazing so as to protrude. The metallized wiring layer 5 is made of tungsten,
A metal paste made of a high melting point metal powder such as molybdenum, manganese or the like, and an appropriate organic solvent or a solvent added to and mixed with the high melting point metal powder such as tungsten is applied to a ceramic green sheet serving as an insulating substrate 1 in a known manner. By printing and applying a predetermined pattern by a screen printing method, the insulating substrate 1 is applied from the periphery of the concave portion 1a to the outer peripheral edge. The metallized wiring layer 5 is coated with a metal having excellent corrosion resistance such as nickel and gold and a good wettability with a brazing material to a thickness of 1.0 to 20.0 μm on an exposed surface thereof by a plating method. And the metallized wiring layer 5 can be effectively prevented from being oxidized and corroded.
Between metallization and bonding wire 6 and metallized wiring layer
The attachment of the external lead terminal 7 to the terminal 5 can be made firm. Therefore, in order to prevent the metallized wiring layer 5 from being oxidized and corroded and to firmly attach the metallized wiring layer 5 to the bonding wires 6 and the external lead terminals 7, nickel, gold, or the like is applied to the exposed surface of the metallized wiring layer 5. 1.0 to 20.0μm
It is preferable that the layer is layered to a thickness of. The external lead terminal 7 attached to the metallized wiring layer 5 via a brazing material such as silver brazing is made of a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy. Are connected to an external electric circuit, each electrode of the semiconductor element 3 housed in the concave portion 1a of the insulating base 1 has a metallized wiring layer 5 and an external lead terminal 7.
Through an external electric circuit. The external lead terminals 7 are formed in a predetermined shape by employing a conventionally known metal working method such as a rolling method or a punching method for an ingot (a lump) such as an iron-nickel-cobalt alloy. The external lead terminal 7 is preferably formed by coating a metal having excellent corrosion resistance such as nickel and gold and having good wettability with a brazing material to a thickness of 1.0 to 20.0 μm on an exposed surface thereof by a plating method. Oxidation and corrosion of the external lead terminal 7 can be effectively prevented, and the external lead terminal 7 can be firmly connected to an external electric circuit via a brazing material such as solder. Therefore, it is preferable that nickel, gold, or the like be layered on the exposed surface of the external lead terminal 7 to a thickness of 1.0 to 20.0 μm. Further, one end of the external lead terminal 7 protruding outward from the side of the insulating base 1 is connected to a connecting member 8 made of an electrically insulating material in an electrically independent state. In the external lead terminals 7, the distance between the adjacent external lead terminals 7 is always kept constant, and large deformation of the external lead terminals 7 due to the application of an external force is effectively prevented. Can be effectively prevented. At the same time, since each external lead terminal 7 is supported by the connecting member 8 in an electrically independent state, the probe of the electrical inspection device is brought into contact with each external lead terminal 7 and the semiconductor element 3 In checking the electrical characteristics of the above, the workability of the characteristic check becomes extremely good. Further, the external lead terminal 7 is an insulating base.
The adjacent space in the connecting member 8 is wider than the adjacent space in one side. Therefore, when the probe of the electrical inspection device is brought into contact with each of the external lead terminals 7 that are electrically connected to the connecting member 8 in an independent state, and the electrical characteristics of the semiconductor element 3 housed in the container 4 are checked, It is also possible to accurately check the electrical characteristics of the semiconductor element 3 by accurately bringing the probe of the electrical inspection device into contact with each external lead terminal 7. A connecting member for connecting the external lead terminals 7
8 is made of an electrically insulating material such as ceramics such as aluminum oxide sintered body or glass, and the external lead terminals 7 are connected to the connecting member 8 by the external lead terminals.
7 is fixed to the connecting member with a suitable adhesive such as glass, resin, brazing material or the like. Thus, according to the package for housing a semiconductor element of the present invention, the semiconductor element 3
Are bonded and fixed via an adhesive such as glass, resin or brazing material, and each electrode of the semiconductor element 3 is
The cover 2 is then electrically connected to the upper surface of the insulating base 1 via a sealing material made of glass, resin, brazing material, or the like. The semiconductor device 3 as a product is completed by hermetically housing the semiconductor element 3 inside the container 4 composed of It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention. According to the semiconductor device housing package of the present invention, the external lead terminals protruding outside the side of the container housing the semiconductor device are connected by the connecting member made of an electrically insulating material. Therefore, the distance between adjacent external lead terminals is always kept constant, and the external lead terminals are prevented from being greatly deformed due to the application of an external force, so that an electrical short circuit between adjacent external lead terminals can be effectively prevented. Becomes Further, according to the package for accommodating a semiconductor element of the present invention, since the adjacent interval between the connecting members of the external lead terminals is made wider than the adjacent interval on the side of the container, the number of the external lead terminals increases rapidly. Therefore, even if the distance between the adjacent external lead terminals on the side of the container is reduced, the distance between the adjacent external lead terminals on the connecting member can be increased, and as a result, the connecting member can be electrically isolated. It is also possible to accurately check the electrical characteristics of the semiconductor device housed inside the container of the semiconductor device housing package by accurately bringing the probe of the electrical inspection device into contact with each connected external lead terminal.
【図面の簡単な説明】
【図１】 本発明の半導体素子収納用パッケージの一実
施例を示す断面図である。
【図２】 図１に示す半導体素子収納用パッケージの絶
縁基体の平面図である。
【図３】 従来の半導体素子収納用パッケージを示す断
面図である。
【図４】 図３に示す半導体素子収納用パッケージの絶
縁基体の平面図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing one embodiment of a package for housing a semiconductor element according to the present invention. FIG. 2 is a plan view of an insulating base of the semiconductor device housing package shown in FIG. FIG. 3 is a cross-sectional view showing a conventional semiconductor element storage package. FIG. 4 is a plan view of an insulating base of the package for housing a semiconductor element shown in FIG. 3;
Claims (1)
個の外部リード端子を隣接間隔を均等として突出させる
とともに、該突出する外部リード端子を各側辺毎に前記
側辺に平行に配置したセラミックスまたはガラスから成
る電気絶縁性の連結部材で隣接間隔を均等として連結さ
せて成り、前記外部リード端子の連結部材での隣接間隔
を容器側辺での隣接間隔より広くして、前記外部リード
端子の下側を前記連結部材に接着固定したことを特徴と
する半導体素子収納用パッケージ。(57) Claims 1. A plurality of external lead terminals are made to protrude from a side of a container accommodating a semiconductor element at equal intervals , and the protruding external lead terminals are connected to each side. Every time
Made of ceramics or glass placed parallel to the side
That adjacent interval connecting member electrically insulating Ri formed by connecting as evenly, adjacent intervals of a connecting member of the external lead terminals
The by wide comb than the adjacent intervals in the container sides, the external lead
A package for accommodating a semiconductor element , wherein a lower side of a terminal is bonded and fixed to the connecting member .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28783794A JP3406710B2 (en) | 1994-11-22 | 1994-11-22 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28783794A JP3406710B2 (en) | 1994-11-22 | 1994-11-22 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08148633A JPH08148633A (en) | 1996-06-07 |
| JP3406710B2 true JP3406710B2 (en) | 2003-05-12 |
Family
ID=17722416
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28783794A Expired - Fee Related JP3406710B2 (en) | 1994-11-22 | 1994-11-22 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3406710B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060220191A1 (en) * | 2005-04-01 | 2006-10-05 | Honeywell International Inc. | Electronic package with a stepped-pitch leadframe |
-
1994
- 1994-11-22 JP JP28783794A patent/JP3406710B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08148633A (en) | 1996-06-07 |
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