JP2678511B2 - Package for storing semiconductor elements - Google Patents

Description

TECHNICAL FIELD The present invention relates to an improvement of a semiconductor element housing package used for a ceramic package or the like for housing a semiconductor integrated circuit element.

[Prior Art] Conventionally, a semiconductor element housing package used as a ceramic package or the like for housing a semiconductor element, particularly a semiconductor integrated circuit element, for example, a leadless package such as a chip carrier is as shown in FIG. A rectangular cavity 24 for accommodating a semiconductor element, which is made of an electrically insulating material such as alumina (Al ₂ O ₃ ) ceramics, and has a metallized layer 25 formed on the bottom surface thereof at a substantially central portion thereof. A recess that has and extends from the bottom surface of the outer peripheral portion to the middle of the side surface
It is composed of an insulating substrate 21 and a lid 22 on which a metallization layer 31 made of a metal powder such as tungsten (W) or molybdenum (Mo) is formed on the inner peripheral surface of the semiconductor element 30 to connect the semiconductor element to an external electric circuit. The semiconductor element 23 is attached and fixed on the metallized layer 25 provided on the bottom surface of the rectangular cavity 24 of the insulating substrate 11, and each electrode of the semiconductor element 23 is wire-connected.
Electrically connected to the metallization layer 26 via 27, then
The lid 22 is bonded to the upper surface of the insulating substrate 21 via an adhesive, and the semiconductor element is hermetically sealed inside, so that a semiconductor device as a final product is completed.

Incidentally, this conventional package for accommodating semiconductor elements is a metallization layer provided on the bottom surface of the rectangular cavity 24 of the insulating base 11.
In order to attach and fix the semiconductor element 23 to 25, and when the metallization layer 31 is brazed to an external electric circuit, the brazing strength is increased to make good electrical connection, and the metallization layer is prevented from being oxidized and corroded. In order to prevent effectively, the outer surfaces of the metallized layers 25, 26, and 31 are plated with gold (Au), nickel (Ni), or the like, which has good bondability with the brazing material and excellent corrosion resistance.

[Problems to be Solved by the Invention] However, in this conventional package for housing a semiconductor element, while the size of a highly integrated semiconductor element increases with the recent miniaturization of electronic devices, the shape of the insulating substrate is Since it is becoming smaller, it occurs due to the difference in thermal expansion coefficient between the insulating substrate and the semiconductor element when the semiconductor element is attached and fixed to the metallized layer provided on the bottom surface of the rectangular cavity of the insulating substrate through the brazing material. The thermal stress is caused by the outermost peripheral edge of the recess provided from the bottom surface of the outer peripheral portion of the insulating substrate to the middle of the side surface as a destruction source to cause cracks or cracks reaching the bottom surface of the rectangular cavity, As a result, the hermetic sealing of the semiconductor element housed inside the semiconductor element housing package is broken, and the semiconductor element is normally operated for a long period of time.
And it was difficult to operate stably.

[Object of the Invention] The present invention has been developed in view of the above-mentioned drawbacks, and an object thereof is to prevent the occurrence of cracks or breaks in an insulating substrate when mounting and fixing a semiconductor element in a rectangular cavity of the insulating substrate. It is an object of the present invention to provide a semiconductor element housing package in which a semiconductor element is hermetically sealed inside a semiconductor element housing package and the semiconductor element can be operated normally and stably for a long period of time.

[Means for Solving the Problems] The present invention provides a package for storing a semiconductor element, which comprises an insulating base body and a lid body in which a plurality of ceramic sheets are laminated and a rectangular cavity having a metallized layer is provided in a substantially central portion, The uppermost outer peripheral edge of the metallization layer provided on the inner peripheral surface of the recess extending from the outer peripheral bottom surface to the middle of the side surface of the insulating base is embedded in the insulating base, and the thickness t and the embedded length l of the embedded portion are t. × l ≧ 1000 However, t and l represent μm and are characterized by satisfying 10 ≦ t ≦ 35 50 ≦ 1.

[Embodiment] Next, a semiconductor element storage package according to the present invention will be described in detail by taking a chip carrier which is a leadless semiconductor element storage package as an example.

FIG. 1 is a perspective view showing an embodiment of a package for accommodating a semiconductor device according to the present invention, and FIG. 2 is a perspective view of an essential part with a part of FIG. 1 cut away.

1 and 2, 1 is an insulating base made of an electrically insulating material such as alumina ceramic, 2 is a lid,
The insulating base body 1 and the lid body 2 constitute a container for housing a semiconductor element.

The insulating base 1 has a rectangular cavity 4 and a stepped portion 14 which forms a space for accommodating the semiconductor element 3 in a substantially central portion of the upper surface thereof, and the bottom surface of the rectangular cavity 4 is metallized. Layer 5 has been deposited. The semiconductor element 3 is attached and fixed on the metallized layer 5 via a brazing material.

A plurality of wiring conductors 6 made of a metallized layer are formed on the upper surface of the stepped portion 14 of the rectangular cavity 4 of the insulating base 1, and the electrodes of the semiconductor element 3 connect the wires 7 to the wiring conductors 6. Electrically connected through. Next, the bottom surface of the base body 1 of the metallization layer 11 provided on the inner peripheral surface of the recess 10 extending from the bottom surface 8 of the outer peripheral portion of the insulating base body 1 to the middle of the side surface 9 is connected to the wiring conductor of the external electric circuit through a brazing material such as solder. It is brazed.

Insulating substrate 1, metallized layers 5, 11 and wiring conductor 6
Is formed by laminating a plurality of unfired ceramic sheets having a surface coated with a metal paste and firing at a temperature of about 1100 to 1600 ° C. in a reducing atmosphere of a mixed gas of hydrogen and nitrogen.

The unfired ceramic sheet is made of alumina (Al ₂ O
₃ ), silica (SiO ₂ ) and other ceramic raw material powders are mixed with an appropriate solvent and a solvent to form a slurry, which is formed into a sheet by a conventionally known doctor blade method. Further, a large number of through-holes are formed in an array by a conventionally known punching method so as to be divided into a plurality of sections on the unfired ceramic sheet, so that a large-area unfired ceramic sheet is suitable for a semiconductor element housing package. The through-hole is used as a passage for routing the metallized layer when electrically connecting the bottom surface of the insulating substrate to the wiring conductor of the external electric circuit.

Similarly, a rectangular cavity for accommodating a semiconductor element is also formed by a conventionally known punching method.

The metal paste is prepared by adding and mixing an appropriate solvent or solvent to a refractory metal powder such as tungsten (W) or molybdenum (Mo), and is prepared from the surface of the unfired ceramic sheet and the inner peripheral surface of the through hole. The lower surface is printed and applied by a conventionally known thick film technique such as screen printing.

Finally, the insulating substrate is manufactured by cutting and separating the fired ceramic body along the section of the arrangement of the through holes to form individual semiconductor element housing packages.

In the package for storing semiconductor elements, the ceramic paste of the insulating base 1 is formed by printing and applying a metal paste on an unfired ceramic green sheet, embedding the uppermost outer peripheral edge 13 of the metallization layer 11 in the insulating base 1, and firing. A stress due to a difference in thermal expansion coefficient is generated between the metallized layer 11 and molybdenum, tungsten or the like, and the stress is inherent in the metallized layer 11 embedded in the insulating substrate 1 as a compressive stress. As a result, the concave portion provided on the outer peripheral portion of the insulating substrate
The vicinity of the outermost peripheral edge 13 of 10 acts to strengthen the compressive stress, and the semiconductor element 3 is attached and fixed onto the metallized layer 5 provided on the bottom surface of the rectangular cavity 4 of the insulating substrate 1 via a brazing material. The thermal stress generated at that time is canceled out.

If the thickness t of the buried portion 12 of the metallized layer 11 buried in the insulating base 1 is less than 10 μm, the insulating base is insufficiently strengthened, and the vicinity of the uppermost peripheral edge 13 of the recess 10 is the starting point. It will cause cracks and breaks, and also the buried part
When the thickness t of 12 exceeds 35 μm, a stacking failure occurs between the outermost peripheral edge 13 of the metallization layer 11 and the ceramic, and the airtightness of the insulating substrate 1 becomes poor. The thickness t of 12 is specified in the range of 10 to 35 μm.

If the embedding length 1 of the metallized layer 11 is less than 50 μm, the insulating substrate will not be sufficiently strengthened and cracks or cracks will be generated as described above. However, the buried length l should be at least 110 μm or more from various wiring conductors adjacent to each other, and a short circuit may occur unless they are separated from each other.

A lid 2 is provided on the upper surface of the insulating substrate 1 containing the semiconductor element 3.
Are bonded by an adhesive, glass, a brazing material, etc., and the semiconductor element 3 is hermetically sealed inside.

FIG. 3 shows another embodiment of the package for accommodating semiconductor elements according to the present invention, in which another unfired ceramic sheet laminated directly below the unfired ceramic sheet has no through holes. A circular metallization layer having a predetermined thickness and diameter is formed in a thick film so as to correspond to the drilled through-holes, laminated, and fired, and then metallized in the insulating substrate 1 with a predetermined thickness t and length l. The layer 11 is buried.

(Example) A rectangular cavity and a large number of through holes are arrayed by punching on an unfired ceramic sheet made of ceramics mainly composed of alumina (Al ₂ O ₃ ), and tungsten (W) powder is used as a main component. And depositing a metal paste to the inner peripheral surface of the through hole, and forming various ring-shaped patterns having a predetermined thickness t and an embedded length 1 of a predetermined dimension on the outer periphery of the through hole. Are laminated and fired at a temperature of about 1500 ° C. to produce an insulating substrate on which a metallized layer as shown in FIGS. 1 and 2 is deposited.

Next, a brazing material made of gold-silicon (Au-Si) and a silicon semiconductor element are placed on the metallized layer of the insulating substrate, and the brazing material is placed on a heater block set at about 450 ° C to heat the brazing material. The semiconductor element is melted and brazed on the metallized layer.

Incidentally, nickel (Ni) and gold (Au) were layered on the outer surface of the metallized layer provided on the insulating substrate by plating in order to improve the bonding between the metallized layer and the semiconductor element.

Then, on the upper surface of the insulating substrate, Kovar (Fe-Ni-
A metallic lid made of a Co alloy) is adhered with an adhesive to hermetically seal the inside of the package.

Each of the 100 evaluation samples thus obtained was used at 0 ° C to 1 ° C.
After applying a temperature cycle of 00 ° C. for 200 cycles, the airtightness of the evaluation sample was examined with a helium leak detector. Table 1 shows the results. It should be noted that in the table, ◯ indicates that all the airtightnesses were maintained, and x indicates that even one airtightness was broken.

As is apparent from Table 1, the thickness t of the buried portion at the outermost peripheral edge of the metallized layer buried in the insulating substrate is less than 10 μm, or the buried length l is less than 50 μm (Sample Nos. 1 and 2). 3, 13, 17, 21, 25), or t × 1 is 10
Any of less than 00 (Sample Nos. 2, 4, 8, 13, 17, 21) or one in which the thickness t of the buried portion exceeds 35 μm (Sample No. 29) has caused poor airtightness. In contrast,
Any of the semiconductor element housing packages of the present invention can be effectively hermetically sealed.

EFFECTS OF THE INVENTION According to the package for accommodating a semiconductor element of the present invention, when the semiconductor element is mounted and fixed in the rectangular cavity of the insulating substrate, no cracks or cracks are generated in the insulating substrate, and the package for accommodating the semiconductor element is provided. The semiconductor device can be normally and stably operated inside the package for a long period of time.

[Brief description of the drawings]

FIG. 1 is a perspective view showing an embodiment of a package for accommodating a semiconductor element according to the present invention, FIG. 2 is a perspective view of an essential part with a part of FIG. 1 cut away, and FIG. 3 is a semiconductor element according to the present invention. FIG. 4 is a perspective view showing a main part of a storage package according to another embodiment of the present invention, in which a part thereof is broken away, and FIG. 1 ... Insulating base 2 ... Lid 4 ... Rectangular cavity 5, 11 ... Metallized layer 8 ... Bottom surface 9 ... Side surface 10 ... Recessed portion 12 ... Embedded portion 13 ... Top outer peripheral edge t ... … Thickness …… Buried length

Claims (1)

(57) [Claims] 1. A package for storing a semiconductor element comprising an insulating base and a lid in which a plurality of ceramic sheets are laminated and a rectangular cavity having a metallized layer is provided at a substantially central portion, and a bottom surface of an outer peripheral portion of the insulating base. To the middle of the side surface, the uppermost outer peripheral edge of the metallized layer provided on the inner peripheral surface of the recess is embedded in the insulating substrate, and the thickness t and the embedded length l of the embedded portion are t × l ≧ 1000 where t, 1 denotes a μm, which satisfies 10 ≦ t ≦ 35 50 ≦ 1.