JP2631397B2 - Package for storing semiconductor elements - Google Patents
Package for storing semiconductor elementsInfo
- Publication number
- JP2631397B2 JP2631397B2 JP63298879A JP29887988A JP2631397B2 JP 2631397 B2 JP2631397 B2 JP 2631397B2 JP 63298879 A JP63298879 A JP 63298879A JP 29887988 A JP29887988 A JP 29887988A JP 2631397 B2 JP2631397 B2 JP 2631397B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- insulating base
- package
- metal layer
- metallized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
- H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
- H01L2224/26175—Flow barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子、特に半導体集積回路素子を収容
するための半導体素子収納用パッケージの改良に関する
ものである。Description: BACKGROUND OF THE INVENTION (Industrial Application Field) The present invention relates to an improvement in a package for accommodating a semiconductor element, particularly a semiconductor element for accommodating a semiconductor integrated circuit element.
（従来の技術） 従来、半導体素子を収容するための半導体素子収納用
パッケージ、例えばリードレスのパッケージ（チップキ
ャリア）は、第２図に示すようにアルミナ（Al2O3）セ
ラミックス等の電気絶縁材料から成り、その上面中央部
に、底面にメタライズ金属層12が被着形成された半導体
素子を収容するための凹部を有し、かつ外周部、即ち側
面及び底面に半導体素子を外部電気回路に接続するため
のタングステン（Ｗ）、モリブデン（Mo）等の金属粉末
から成るメタライズリード13を被着形成した絶縁基体11
と蓋体17とから構成されており、絶縁基体11の凹部底面
に設けたメタライズ金属層12上に半導体素子14を取着固
定するとともに該半導体素子14の各電極をボンディング
ワイヤ15を介しメタライズリード13に電気的に接続し、
しかる後、絶縁基体11の上面に被着された金属枠16に金
属製蓋体17をシームウエルド法により溶接接合させ、内
部に半導体素子を気密に封止することによって最終製品
としての半導体装置が完成する。2. Description of the Related Art Conventionally, a package for accommodating a semiconductor element for accommodating a semiconductor element, for example, a leadless package (chip carrier) is made of an electrically insulating material such as alumina (Al 2 O 3 ) ceramic as shown in FIG. It has a concave portion for accommodating a semiconductor element on which a metallized metal layer 12 is adhered and formed on the bottom surface, and has a semiconductor element on an outer peripheral portion, that is, a side surface and a bottom surface, in an external electric circuit. An insulating substrate 11 on which metallized leads 13 made of a metal powder such as tungsten (W) or molybdenum (Mo) for connection are formed.
And a lid 17. A semiconductor element 14 is fixedly mounted on a metallized metal layer 12 provided on the bottom surface of the concave portion of the insulating base 11, and each electrode of the semiconductor element 14 is metallized through a bonding wire 15. Electrically connected to 13,
Thereafter, a metal lid 17 is welded and joined to a metal frame 16 attached to the upper surface of the insulating base 11 by a seam weld method, and the semiconductor element as a final product is sealed by hermetically sealing the semiconductor element inside. Complete.
尚、この従来の半導体素子収納用パッケージは絶縁基
体11の凹部底面に設けたメタライズ金属層12に半導体素
子14を強固に取着固定するために、またメタライズリー
ド13と外部電気回路との電気的接続を良好とし、かつメ
タライズリードが酸化腐蝕するのを有効に防止するため
に通常、メタライズ金属層12及びメタライズリード13の
外表面にはニッケル（Ni）及び金（Au）等がメッキによ
り層着されている。The conventional semiconductor element housing package is used to firmly attach and fix the semiconductor element 14 to the metallized metal layer 12 provided on the bottom surface of the concave portion of the insulating base 11, and to electrically connect the metallized lead 13 to an external electric circuit. Normally, nickel (Ni) and gold (Au) are deposited on the outer surfaces of the metallized metal layer 12 and the metallized lead 13 by plating to improve the connection and effectively prevent the metallized lead from being oxidized and corroded. Have been.
（発明が解決しようとする課題） しかし乍ら、この従来の半導体素子収納用パッケージ
は、近時の電子機器の小型化に伴い絶縁基体の形状が小
さくなってきていること及び絶縁基体に蓋体を接合さ
せ、内部に半導体素子を気密に封止するのが絶縁基体の
上面に被着させた金属枠に蓋体をシームウエルド法によ
り溶接することにより行っていること等から以下に述べ
る欠点を有する。(Problems to be Solved by the Invention) However, in this conventional package for housing a semiconductor element, the shape of the insulating base has become smaller with the recent miniaturization of electronic devices, and a lid has been provided on the insulating base. And the hermetically sealing the semiconductor element inside is performed by welding the lid to the metal frame attached to the upper surface of the insulating base by the seam welding method. Have.
即ち、絶縁基体の上面に被着させた金属枠に蓋体をシ
ームウエルド法により溶接接合させた場合、該蓋体の溶
接は絶縁基体の上面で行われることから溶接の熱は絶縁
基体の上面部に多量に印加され、絶縁基体の上面部温度
が底面部に比較して高いものとなる。そのため絶縁基体
はその上面部が底面部より大きく膨張し、絶縁基体の凹
部底面外周部に応力が発生して凹部底面外周部にクラッ
クや割れを生じさせ、その結果、パッケージ内部に収容
するする半導体素子の気密封止が容易に破れ、半導体素
子を長期間にわたり正常、 かつ安定に作動させることができないという欠点を有
する。That is, when the lid is welded to the metal frame attached to the upper surface of the insulating substrate by seam welding, the welding of the lid is performed on the upper surface of the insulating substrate. A large amount is applied to the portion, and the upper surface temperature of the insulating base becomes higher than that of the bottom portion. As a result, the upper surface of the insulating substrate expands more than the bottom surface, and stress is generated at the outer peripheral portion of the concave bottom surface of the insulating substrate, causing cracks and cracks at the outer peripheral portion of the concave bottom surface. As a result, the semiconductor housed inside the package There is a disadvantage that the hermetic sealing of the device is easily broken, and the semiconductor device cannot be operated normally and stably for a long period of time.
（発明の目的） 本発明は上記欠点に鑑み案出されたものでその目的
は、絶縁基体に蓋体をシームウエルド法により溶接する
際、絶縁基体にクラックや割れが発生するのを皆無とな
し、パッケージ内部の気密封止を完全として内部に収容
する半導体素子を長期間にわたり正常、かつ安定に作動
させることができる半導体素子収納用パッケージを提供
することにある。(Object of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and an object of the present invention is to eliminate cracks and cracks in an insulating substrate when a lid is welded to the insulating substrate by a seam welding method. It is another object of the present invention to provide a package for housing a semiconductor element which can completely and hermetically seal the inside of the package and can operate the semiconductor element normally and stably for a long period of time.
（課題を解決するための手段） 本発明は半導体素子を収容するための凹部及び該凹部
底面に半導体素子を取着するためのメタライズ金属層を
有する絶縁基体と蓋体とから成る半導体素子収納用パッ
ケージにおいて、前記絶縁基体の凹部底面に設けたメタ
ライズ金属層の外周縁を絶縁基体内に埋入させるととも
に該埋入部の厚みを15乃至45μｍとしたことを特徴とす
るものである。(Means for Solving the Problems) The present invention relates to a semiconductor device housing comprising a cover and an insulating base having a recess for housing the semiconductor device and a metallized metal layer for attaching the semiconductor device to the bottom of the recess. In the package, the outer peripheral edge of the metallized metal layer provided on the bottom surface of the concave portion of the insulating base is embedded in the insulating base, and the thickness of the embedded portion is set to 15 to 45 μm.
（実施例） 次に本発明にかかる半導体素子収納用パッケージをリ
ードレスのパッケージ（チップキャリア）を例に採って
詳細に説明する。(Example) Next, a semiconductor element storage package according to the present invention will be described in detail using a leadless package (chip carrier) as an example.
第１図は本発明の半導体素子収納用パッケージの一実
施例を示し、１はアルミナセラミック等の電気絶縁材料
から成る絶縁基体、２は蓋体である。この絶縁基体１と
蓋体２とで半導体素子を収容するための容器を構成す
る。FIG. 1 shows an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base made of an electrically insulating material such as alumina ceramic, and 2 is a lid. The insulating base 1 and the lid 2 constitute a container for housing a semiconductor element.
前記絶縁基体１はその上面中央部に半導体素子を収容
するための空所を形成する段状の凹部を有しており、該
凹部底面にはメタライズ金属層３が被着形成されてい
る。The insulating base 1 has a stepped recess forming a cavity for accommodating a semiconductor element in the center of the upper surface, and a metallized metal layer 3 is formed on the bottom of the recess.
前記絶縁基体１の凹部底面に設けたメタライズ金属層
３上には半導体素子４がロウ材を介し取着され、固定さ
れる。On the metallized metal layer 3 provided on the bottom surface of the concave portion of the insulating base 1, a semiconductor element 4 is attached via a brazing material and fixed.
また前記絶縁基体１には凹部段状上面から側面を介し
て底面にかけて導出しているメタライズリード５が形成
されており、メタライズリード５の凹部段状上面部には
半導体素子４の電極がボンディングワイヤ６を介し電気
的に接続され、またメタライズリード５の基体１底面部
は外部電気回路の配線導体に半田等のロウ材を介しロウ
付けされる。A metallized lead 5 is formed on the insulating base 1 and extends from the stepped upper surface of the concave portion to the bottom surface via the side surface. The electrode of the semiconductor element 4 is provided with a bonding wire on the stepped upper surface of the concave portion of the metallized lead 5. 6, and the bottom surface of the base 1 of the metallized lead 5 is brazed to a wiring conductor of an external electric circuit via a brazing material such as solder.
前記絶縁基体１、メタライズ金属層３及びメタライズ
リート５は表面に金属ペーストを印刷塗布した未焼成セ
ラミックシート（グリーンシート）を複数枚積層すると
ともに還元性雰囲気中（H2−N2ガス中）、約1400〜1600
℃の高温で焼成することによって形成される。The insulating substrate 1, the metallized metal layer 3 and the metallized reit 5 are formed by laminating a plurality of unfired ceramic sheets (green sheets) each having a surface coated with a metal paste by printing, in a reducing atmosphere (in H 2 -N 2 gas), About 1400-1600
It is formed by firing at a high temperature of ° C.
尚、前記未焼成セラミックシートはアルミナ（Al
2O3）、シリカ（SiO2）等のセラミック原料粉末に適当
な溶剤、溶媒を添加混合して泥漿物を作り、これを従来
周知のドクターブレード法によりシート状となすことに
よって形成され、また金属ペーストはタングステン
（Ｗ）、モリブデン（Mo）、マンガン（Mn）等の高融点
金属粉末に適当な溶剤、溶媒を添加混合することによっ
て作成され、未焼成セラミックシートの表面には従来周
知のスクリーン印刷等の厚膜手法を採用することによっ
て印刷塗布される。The unsintered ceramic sheet is made of alumina (Al
An appropriate solvent and solvent are added to and mixed with ceramic raw material powders such as 2 O 3 ) and silica (SiO 2 ) to form a slurry, which is formed into a sheet by a conventionally known doctor blade method. The metal paste is prepared by adding a suitable solvent and a solvent to a high melting point metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn) and the like, and a conventional well-known screen is formed on the surface of the unfired ceramic sheet. Printing and coating are performed by employing a thick film technique such as printing.
また前記絶縁基体１の凹部底面に被着形成されるメタ
ライズ金属層３はその外周縁が絶縁基体１内に埋入され
ており、メタライズ金属層３の外周縁を絶縁基体１に埋
入させると絶縁基体１内の特に凹部底面周辺に内部応力
が内在し、これが絶縁基体１の上面に蓋体２をシームウ
エルド法により溶接する際の応力を相殺する。The outer peripheral edge of the metallized metal layer 3 formed on the bottom surface of the concave portion of the insulating substrate 1 is embedded in the insulating substrate 1, and the outer peripheral edge of the metallized metal layer 3 is embedded in the insulating substrate 1. Internal stresses are present inside the insulating base 1, particularly around the bottom of the concave portion, and this offsets the stress when the lid 2 is welded to the upper surface of the insulating base 1 by the seam welding method.
即ち、未焼成セラミックシートに金属ペーストを印刷
塗布し、しかる後、焼成してメタライズ金属層３の外周
縁が絶縁基体１内に埋入したものを得る場合、絶縁基体
１のセラミックとメタライズ金属層３のモリブデン、タ
ングステン等とは熱膨張係数が相違することから両者間
に熱膨張係数の相違に起因する応力が発生しこれが絶縁
基体１の内部に内在する。この絶縁基体１内に内在する
応力は絶縁基体の上面部を内側に縮める方向の応力であ
り、後述の絶縁基体１上面に蓋体２をシームウエルド法
により溶接する際、絶縁基体（セラミック体）の上面部
が広がることにより発生する応力とは反対方向の応力で
あることから絶縁基体１内に内在する応力は蓋体２を溶
接する際の応力を相殺することができる。That is, when a metal paste is printed and applied to an unfired ceramic sheet and then fired to obtain a metallized metal layer 3 in which the outer peripheral edge is embedded in the insulating substrate 1, the ceramic of the insulating substrate 1 and the metallized metal layer Since molybdenum, tungsten, and the like have different coefficients of thermal expansion, a stress is generated between the two due to the difference in coefficient of thermal expansion, and this stress is present inside the insulating base 1. The stress existing in the insulating base 1 is a stress in a direction in which the upper surface of the insulating base is shrunk inward. When the lid 2 is welded to the upper surface of the insulating base 1 by a seam welding method as described later, the insulating base (ceramic body) is used. Since the stress is generated in a direction opposite to the stress generated by the spread of the upper surface of the cover 2, the stress existing in the insulating base 1 can cancel the stress when the lid 2 is welded.
尚、前記絶縁基体１内に埋入させるメタライズ金属層
３はその埋入部の厚みが15μｍ未満であると絶縁基体１
内に内在させる応力が小さくなり、蓋体２を溶接する際
の応力を完全に相殺することができず絶縁基体１にクラ
ックや割れを発生してしまい、また厚みが45μｍを超え
ると絶縁基体１の底面外周部におけるメタライズ金属層
３とセラミックとの間に積層不良が発生し絶縁基体１に
気密不良を生じることからメタライズ金属層３の絶縁基
体１内に埋入させる部位の厚みは15乃至45μｍの範囲に
特定される。The metallized metal layer 3 to be embedded in the insulating substrate 1 has a thickness of less than 15 .mu.m.
When the thickness of the insulating substrate 1 exceeds 45 μm, the stress in welding the lid 2 cannot be completely canceled, and the insulating substrate 1 has cracks and cracks. Since the lamination failure occurs between the metallized metal layer 3 and the ceramic at the outer peripheral portion of the bottom surface and the airtight failure occurs in the insulating substrate 1, the thickness of the portion of the metallized metal layer 3 embedded in the insulating substrate 1 is 15 to 45 μm. Specified in the range.
また前記絶縁基体１に設けたメタライズ金属層３及び
メタライズリード５は、メタライズ金属層３上に半導体
素子４を強固に取着固定するために、またメタライズリ
ード５と外部電気回路との電気的接続を良好とし、かつ
メタライズリード５が酸化腐蝕するのを防止するため
に、その外表面にニッケル（Ni）及び金（Au）がメッキ
により層着されている。The metallized metal layer 3 and the metallized lead 5 provided on the insulating base 1 are used to firmly attach and fix the semiconductor element 4 on the metallized metal layer 3 and to provide an electrical connection between the metallized lead 5 and an external electric circuit. In order to make the metallization lead 5 good and to prevent the metallized lead 5 from being oxidized and corroded, nickel (Ni) and gold (Au) are layered on the outer surface thereof by plating.
かくして前記絶縁基体１の凹部底面に設けたメタライ
ズ金属層３に半導体素子４を金−シリコン（Au−Si）等
のロウ材を介し取着固定するとともに半導体素子の各電
極をメタライズリード５にボンディングワイヤ６を介し
て電気的に接続し、しかる後、絶縁基体１の上面に被着
した金属枠７に蓋体２をシームウエルド法により溶接接
合し、容器の内部を気密に封止することによって最終製
品である半導体装置となる。Thus, the semiconductor element 4 is attached and fixed to the metallized metal layer 3 provided on the bottom surface of the concave portion of the insulating base 1 via a brazing material such as gold-silicon (Au-Si), and each electrode of the semiconductor element is bonded to the metallized lead 5. The lid 2 is electrically connected to the metal frame 7 attached to the upper surface of the insulating base 1 by seam welding, and the inside of the container is airtightly sealed. The semiconductor device is the final product.
尚、この場合、絶縁基体１の上面に蓋体２を溶接する
際に絶縁基体１に応力が発生するが、該応力は絶縁基体
１内に内在する応力によって相殺され、絶縁基体１にク
ラックや割れ等を発生することはない。In this case, when the lid 2 is welded to the upper surface of the insulating base 1, stress is generated in the insulating base 1, but the stress is offset by the stress existing in the insulating base 1, and cracks and the like occur in the insulating base 1. No cracking or the like occurs.
また前記絶縁基体１の上面に被着される金属枠７はコ
バール（Fe−Ni−Co合金）等の金属より成り、絶縁基体
１の上面に予め金属層を設けておくとともに該金属層に
銀ロウ等のロウ材を介しロウ付けすることによって絶縁
基体１の上面に被着される。また前記蓋体２はコバー
ル、銅等の金属から成り、絶縁基体１の凹部を塞ぐ大き
さを有している。The metal frame 7 attached to the upper surface of the insulating base 1 is made of a metal such as Kovar (Fe—Ni—Co alloy). A metal layer is provided on the upper surface of the insulating base 1 in advance, and silver is added to the metal layer. By being brazed through a brazing material such as brazing, it is adhered to the upper surface of the insulating base 1. The lid 2 is made of a metal such as Kovar or copper, and has a size to close the concave portion of the insulating base 1.
（実施例） 次ぎに本発明の作用効果を下記に示す実験例に基づい
て説明する。(Examples) Next, the operation and effect of the present invention will be described based on the following experimental examples.
まずアルミナ（Al2O3）セラミックスから成る未焼成
セラミックシートにタングステン（Ｗ）の粉末を用いた
金属ペーストを所定パターンに印刷塗布し、これを複数
枚積層するとともに約1500℃の温度で焼成して第１図に
示す様な凹部底面にメタライズ金属層を被着形成させた
構造の半導体素子収納用パッケージの絶縁基体を作成す
る。First, a metal paste using tungsten (W) powder is printed and applied in a predetermined pattern on an unfired ceramic sheet made of alumina (Al 2 O 3 ) ceramics, and a plurality of these are laminated and fired at a temperature of about 1500 ° C. In this way, an insulating base of a package for housing a semiconductor element having a structure in which a metallized metal layer is formed on the bottom of the concave portion as shown in FIG. 1 is formed.
尚、この際、絶縁基体の凹部底面に被着させたメタラ
イズ金属層はその外周縁を0.3mm絶縁基体内に埋入させ
るとともに該埋入部の厚みを第１表に示す夫々の厚みと
し、これらを100個づつ作って実験試料とした。At this time, the metallized metal layer deposited on the bottom surface of the concave portion of the insulating substrate had its outer peripheral edge buried in the insulating substrate at 0.3 mm, and the thickness of the buried portion was set to each thickness shown in Table 1. Was made as an experimental sample.
次に前記絶縁基体のメタライズ金属層上に金−シリコ
ン（Au−Si）から成るロウ材及びシリコン半導体素子を
載置するとともにこれを450℃に設定されたヒーターブ
ロック上に置き、ロウ材を加熱溶融させて半導体素子を
メタライズ金属層上にロウ付けする。Next, a brazing material made of gold-silicon (Au-Si) and a silicon semiconductor element are placed on the metallized metal layer of the insulating base and placed on a heater block set at 450 ° C. to heat the brazing material. The semiconductor element is melted and brazed on the metallized metal layer.
尚、前記絶縁基体に設けたメタライズ金属層の外表面
には該メタライズ金属層と半導体素子との接合を良好と
するためにニッケル（Ni）及び金（Au）をメッキにより
層着した。In addition, nickel (Ni) and gold (Au) were deposited on the outer surface of the metallized metal layer provided on the insulating substrate by plating in order to improve the bonding between the metallized metal layer and the semiconductor element.
そして次ぎに前記絶縁基体の上面に被着させたコバー
ル（Fe−Ni−Co合金）から成る金属枠にコバール（Fe−
Ni−Co合金）から成る金属製蓋体を載置するとともに蓋
体に電極を当接させ、電極に190A、200Vの電力を印加し
て蓋体を金属枠に溶接し、パッケージの内部を気密に封
止する。Then, Kovar (Fe-Ni-Co alloy) is applied to a metal frame made of Kovar (Fe-Ni-Co alloy) attached on the upper surface of the insulating base.
A metal lid made of Ni-Co alloy) is placed and an electrode is brought into contact with the lid. 190A, 200V power is applied to the electrode, the lid is welded to the metal frame, and the inside of the package is airtight. To seal.
そして最後に前記パッケージ内部の気密性をヘリウム
リークディテクターで検査し、気密が破れているものの
数を数え、これを不良率として算出した。Finally, the hermeticity inside the package was inspected with a helium leak detector, the number of hermetically sealed ones was counted, and this was calculated as a defective rate.
その結果を第１表に示す。 Table 1 shows the results.
（発明の効果） 上記実験結果からも判るように、絶縁基体の凹部底面
に設けたメタライズ金属層の絶縁基体内に埋入させた部
位の厚みが15μｍ未満であるもの（試料番号１）は絶縁
基体内に内在する応力が小であるため絶縁基体に蓋体を
溶接する際の応力を完全に相殺することができず、絶縁
基体にクラックや割れを発生して90％以上のパッケージ
に気密不良を招来し、また厚みが45μｍを超えるもの
（試料番号10）はメタライズ金属層の外周部において積
層不良が発生し、同じく82％以上のパッケージに気密不
良を招来してしまう。 (Effects of the Invention) As can be seen from the above experimental results, the metallized metal layer provided on the bottom surface of the concave portion of the insulating substrate having a thickness of less than 15 μm embedded in the insulating substrate (sample No. 1) was insulated. Since the stress existing in the base is small, the stress when the lid is welded to the insulating base cannot be completely offset, and cracks and cracks occur in the insulating base, resulting in poor airtightness of 90% or more packages. When the thickness exceeds 45 μm (sample No. 10), a lamination failure occurs at the outer peripheral portion of the metallized metal layer, and a 82% or more package also suffers from poor airtightness.
これに対し、本発明のパッケージ、即ち、メタライズ
金属層の絶縁基体内に埋入される部位の厚みが15乃至45
μｍのものは絶縁基体内に内在する応力が適当で、該内
在する応力が蓋体を溶接する際の応力を有効に相殺して
パッケージの気密不良率を26％以下にまで下げる。その
ため本発明のパッケージではその内部に半導体素子を有
効に気密封止することが可能となり、内部に収容する半
導体素子を長期間にわたり正常、且つ安定に作動させる
ことができる。In contrast, the thickness of the package of the present invention, that is, the portion of the metallized metal layer embedded in the insulating base is 15 to 45.
In the case of μm, the stress existing in the insulating base is appropriate, and the inherent stress effectively cancels the stress at the time of welding the lid, thereby lowering the airtight defect rate of the package to 26% or less. Therefore, in the package of the present invention, the semiconductor element can be effectively hermetically sealed therein, and the semiconductor element housed therein can be operated normally and stably for a long period of time.
第１図は本発明にかかる半導体素子収納用パッケージの
一実施例を示す断面図、第２図は従来の半導体素子収納
用パッケージの断面図である。 1:絶縁基体、2:蓋体 3:メタライズ金属層 5:メタライズリード 7:金属枠FIG. 1 is a sectional view showing an embodiment of a package for housing a semiconductor element according to the present invention, and FIG. 2 is a sectional view of a conventional package for housing a semiconductor element. 1: Insulating substrate, 2: Lid 3: Metallized metal layer 5: Metallized lead 7: Metal frame
Claims (1)
部底面に半導体素子を取着するためのメタライズ金属層
を有する絶縁基体と蓋体とから成る半導体素子収納用パ
ッケージにおいて、前記絶縁基体の凹部底面に設けたメ
タライズ金属層の外周縁を絶縁基体内に埋入させるとと
もに該埋入部の厚みを15乃至45μｍとしたことを特徴と
する半導体素子収納用パッケージ。1. A semiconductor element housing package comprising: a lid having a concave portion for accommodating a semiconductor element and a metallized metal layer for attaching the semiconductor element to a bottom surface of the concave portion; and a lid. A package for housing a semiconductor element, wherein an outer peripheral edge of a metallized metal layer provided on a bottom surface of a concave portion is embedded in an insulating base, and a thickness of the embedded portion is 15 to 45 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298879A JP2631397B2 (en) | 1988-11-25 | 1988-11-25 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63298879A JP2631397B2 (en) | 1988-11-25 | 1988-11-25 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02143539A JPH02143539A (en) | 1990-06-01 |
| JP2631397B2 true JP2631397B2 (en) | 1997-07-16 |
Family
ID=17865357
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63298879A Expired - Fee Related JP2631397B2 (en) | 1988-11-25 | 1988-11-25 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2631397B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010074072A (en) * | 2008-09-22 | 2010-04-02 | Nec Corp | Semiconductor device and method of manufacturing semiconductor device |
-
1988
- 1988-11-25 JP JP63298879A patent/JP2631397B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02143539A (en) | 1990-06-01 |
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