JPH0745962Y2 - Package for storing semiconductor devices - Google Patents

Package for storing semiconductor devices

Info

Publication number
JPH0745962Y2
JPH0745962Y2 JP12545489U JP12545489U JPH0745962Y2 JP H0745962 Y2 JPH0745962 Y2 JP H0745962Y2 JP 12545489 U JP12545489 U JP 12545489U JP 12545489 U JP12545489 U JP 12545489U JP H0745962 Y2 JPH0745962 Y2 JP H0745962Y2
Authority
JP
Japan
Prior art keywords
insulating
semiconductor element
insulating substrate
insulating base
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP12545489U
Other languages
Japanese (ja)
Other versions
JPH0363942U (en
Inventor
博司 土岐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP12545489U priority Critical patent/JPH0745962Y2/en
Publication of JPH0363942U publication Critical patent/JPH0363942U/ja
Application granted granted Critical
Publication of JPH0745962Y2 publication Critical patent/JPH0745962Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Description

【考案の詳細な説明】 (産業上の利用分野) 本考案は半導体素子を収容するための半導体素子収納用
パッケージの改良に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to an improvement of a semiconductor element housing package for housing a semiconductor element.

(従来の技術) 従来、LSI(大規模集積回路)等の半導体素子を収容す
るための半導体素子収納用パッケージは第3図及び第4
図に示すようにアルミナセラミックス等の電気絶縁材料
とり成り、上面に半導体素子を収容するための凹部及び
該凹部周辺より側面にかけて導出されたモリブデン(M
o)、タングステン(W)、マンガン(Mn)等の高融点
金属粉末から成るメタライズ金属層12を有する絶縁基体
11と、半導体素子を外部回路に電気的に接続するために
前記メタライズ金属層12に銀ロウ(Ag-Cu合金)等のロ
ウ材を介し取着された外部リード端子13と蓋体14とから
構成されており、絶縁基体11の凹部底面に半導体素子15
を金−シリコン(Au-Si)共晶半田や銀(Ag)系エポキ
シ接着剤等により取着固定し、半導体素子15の各電極を
ボディングワイヤ16を介しメタライズ金属層12に電気的
に接続させると共に、絶縁基体11の上面に蓋体14をガラ
ス、樹脂等の封止材17を介して接合させ、絶縁基体11の
凹部内に半導体素子15を気密に封止することによって半
導体装置となる。
(Prior Art) Conventionally, semiconductor element housing packages for housing semiconductor elements such as LSIs (Large Scale Integrated Circuits) are shown in FIGS.
As shown in the figure, it is made of an electrically insulating material such as alumina ceramics and has a concave portion for accommodating a semiconductor element on the upper surface and molybdenum (M
o), tungsten (W), manganese (Mn), etc. Insulating substrate having metallized metal layer 12 made of high melting point metal powder
11, an external lead terminal 13 and a lid 14 which are attached to the metallized metal layer 12 via a brazing material such as silver brazing (Ag-Cu alloy) for electrically connecting the semiconductor element to an external circuit. The semiconductor element 15 is formed on the bottom surface of the recess of the insulating base 11.
Are fixed and attached using gold-silicon (Au-Si) eutectic solder or silver (Ag) -based epoxy adhesive, etc., and each electrode of the semiconductor element 15 is electrically connected to the metallized metal layer 12 via the bonding wire 16. At the same time, the lid 14 is bonded to the upper surface of the insulating base 11 via the sealing material 17 such as glass or resin, and the semiconductor element 15 is hermetically sealed in the recess of the insulating base 11 to form a semiconductor device. .

かかる従来の半導体素子収納用パッケージは通常、絶縁
基体が以下の方法によって製作される。
In such a conventional package for accommodating semiconductor elements, an insulating substrate is usually manufactured by the following method.

即ち、 まずアルミナ(Al2O3)セラミック等の原料粉末に適当
な有機溶剤、溶媒を添加混合して泥漿状となすと共に、
該泥漿物をドクターブレード法を採用することによって
シート状となし、複数枚のセラミックグリーンシート
(生シート)を得、 次に前記セラミックグリーンシートに所定形状の穴部を
設けると共に、上面にタングステン(W)、モリブデン
(Mo)、マンガン(Mn)等の高融点金属粉末から成る金
属ペーストをスクリーン印刷法により所定パターンに印
刷塗布し、 最後に前記セラミックグリーンシートの複数枚を積層
し、セラミックグリーンシート積層体を得ると共に、該
積層体を還元雰囲気中、約1500℃の温度で焼成し、各セ
ラミックグリーンシートと金属ペーストとを焼結一体化
させ、これによって絶縁基体となる。
That is, first, an appropriate organic solvent and a solvent are added to and mixed with a raw material powder such as alumina (Al 2 O 3 ) ceramic to form a slurry,
The sludge is formed into a sheet by adopting a doctor blade method to obtain a plurality of ceramic green sheets (green sheets). Next, the ceramic green sheets are provided with holes of a predetermined shape and tungsten ( W), molybdenum (Mo), manganese (Mn) and other high melting point metal powders are applied by a screen printing method in a predetermined pattern by printing, and finally a plurality of the ceramic green sheets are laminated to form a ceramic green sheet. At the same time as obtaining the laminated body, the laminated body is fired at a temperature of about 1500 ° C. in a reducing atmosphere to sinter and integrate the respective ceramic green sheets and the metal paste, thereby forming an insulating substrate.

(考案が解決しようとする課題) しかし乍ら、この従来の半導体素子収納用パッケージは
絶縁基体がセラミックグリーンシートを使用することに
よって製作されており、セラミック原料の泥漿物をドク
ターブレード法を採用することによってシート状となし
たセラミックグリーンシートはその表面の中心線平均粗
さ(Ra)がRa≦0.5μmと小さく、該セラミックグリー
ンシートを複数枚積層して得た絶縁基体もその表面の中
心線平均粗さ(Ra)がRa≦0.5μmの極めて平滑なもの
となる。そのためこの絶縁基体に蓋体をガラスや樹脂等
の封止材を介し接合させ、絶縁基体の凹部を気密に封止
した場合、絶縁基体はその表面が平滑であることから絶
縁基体と封止材との接合強度が弱く、絶縁基体と封止材
の間に半導体素子の作動時に発する熱等が繰り返し印加
されるとその熱履歴によって両者間に剥離は発生し、そ
の結果、絶縁基体凹部の気密封止が破れ、凹部内に収容
する半導体素子を長期間にわたり正常、且つ安定に作動
させることができないという欠点を有していた。
(Problems to be solved by the invention) However, in the conventional semiconductor element housing package, the insulating base is manufactured by using the ceramic green sheet, and the sludge of the ceramic raw material is adopted by the doctor blade method. The center line average roughness (Ra) of the surface of the ceramic green sheet formed into a sheet by this is small as Ra ≦ 0.5 μm, and the insulating substrate obtained by laminating a plurality of the ceramic green sheets also has a center line of the surface. The average roughness (Ra) becomes Ra ≦ 0.5 μm and is extremely smooth. Therefore, when the lid is joined to this insulating substrate via a sealing material such as glass or resin to hermetically seal the concave portion of the insulating substrate, the insulating substrate and the sealing material are smooth because the surface of the insulating substrate is smooth. If the heat generated during the operation of the semiconductor element is repeatedly applied between the insulating base and the sealing material due to the weak bonding strength between the insulating base and the sealing base, peeling occurs between the insulating base and the encapsulant. There is a drawback that the tight sealing is broken and the semiconductor element housed in the recess cannot be operated normally and stably for a long period of time.

そこで上記欠点を解消するために、絶縁基体の表面をサ
ンドブラスト処理やエッチング処理等により粗面とし絶
縁基体と封止材との接合面積を増大させることによって
絶縁基体と封止材との接合強度を向上させることが考え
られる。
Therefore, in order to eliminate the above-mentioned drawbacks, the surface of the insulating substrate is roughened by sandblasting or etching to increase the bonding area between the insulating substrate and the sealing material to increase the bonding strength between the insulating substrate and the sealing material. It can be improved.

しかし乍ら、絶縁基体の表面にサンドブラスト処理やエ
ッチング処理等を施すと絶縁基体の封止材が接合する表
面はもちろんのこと絶縁基体に被着させたメタライズ金
属層の露出表面をも粗面となしてしまい、その結果、メ
タライズ金属層にボンディングワイヤを強固に接合させ
ることが不可となって半導体素子の各電極を所定の外部
リード端子に確実に接続することができなくなるという
欠点を誘発する。
However, when the surface of the insulating substrate is subjected to sandblasting or etching, the exposed surface of the metallized metal layer deposited on the insulating substrate is not only a rough surface but also the surface to which the sealing material of the insulating substrate is bonded. As a result, it becomes impossible to firmly bond the bonding wire to the metallized metal layer, which causes a drawback that each electrode of the semiconductor element cannot be reliably connected to a predetermined external lead terminal.

(考案の目的) 本考案は上記欠点に鑑み案出されたもので、その目的は
絶縁基体と封止材との接合強度を大幅に向上させ、絶縁
基体と蓋体とを強固に取着することによって絶縁基体に
設けた凹部の気密封止を完全となし、内部に収納する半
導体素子を長期間にわたり正常、且つ安定に作動させる
ことができる半導体素子収納用パッケージを提供するこ
とにある。
(Purpose of the Invention) The present invention has been devised in view of the above-mentioned drawbacks, and the purpose thereof is to significantly improve the bonding strength between the insulating base and the sealing material, and firmly attach the insulating base and the lid. Thus, the present invention provides a package for accommodating a semiconductor element in which the recess provided in the insulating base is completely hermetically sealed and the semiconductor element accommodated therein can be normally and stably operated for a long period of time.

(課題を解決するための手段) 本考案は、半導体素子を収容するための凹部を有する絶
縁基体と蓋体とから成り、絶縁基体上に該絶縁基体の凹
部を塞ぐよう蓋体を封止材を介し取着するようになした
半導体素子収納用パッケージにおいて、前記絶縁基体の
封止材が接合する表面に絶縁基体と実質的に同一の熱膨
張係数を有し、且つ表面の中心線平均粗さ(Ra)がRa≧
0.65μmである厚膜形成技術により形成される絶縁膜を
被着させたことを特徴とするものである。
(Means for Solving the Problems) The present invention comprises an insulating base having a recess for accommodating a semiconductor element and a lid, and a lid encapsulating material on the insulating base so as to close the recess of the insulating base. In the package for accommodating a semiconductor element adapted to be attached via a sealant, the surface of the insulating base on which the sealing material is bonded has substantially the same coefficient of thermal expansion as the insulating base, and the center line average roughness of the surface is Sa (Ra) is Ra ≧
It is characterized in that an insulating film formed by a thick film forming technique of 0.65 μm is deposited.

(実施例) 次に本考案を添付図面に示す実施例に基づき詳細に説明
する。
(Embodiment) Next, the present invention will be described in detail based on an embodiment shown in the accompanying drawings.

第1図及び第2図は本考案の半導体素子収納用パッケー
ジの一実施例を示し、1はアルミナセラミック等の電気
絶縁材料から成る絶縁基体であり、2は同じく電気絶縁
材料より成る蓋体である。この絶縁基体1と蓋体2とで
半導体素子を収納するための絶縁容器が構成される。
1 and 2 show an embodiment of a package for housing a semiconductor device of the present invention, 1 is an insulating base made of an electrically insulating material such as alumina ceramic, and 2 is a lid made of the same electrically insulating material. is there. The insulating base 1 and the lid 2 constitute an insulating container for housing a semiconductor element.

前記絶縁基体1はその上面中央部に半導体素子を収納す
るための段状の凹部1aが設けてあり、該凹部1a底面には
半導体素子3が金−シリコン(Au-Si)共晶半田や銀(A
g)系エポキシ接着剤等の接着材を介し取着される。
The insulating base 1 is provided with a stepped recess 1a for accommodating a semiconductor element in the center of the upper surface thereof, and the semiconductor element 3 is provided on the bottom surface of the recess 1a with a gold-silicon (Au-Si) eutectic solder or silver. (A
g) Attached via an adhesive such as epoxy adhesive.

前記絶縁基体1は、アルミナセラミックス等の原料粉末
に適当な有機溶剤、溶媒を添加して泥漿状となすと共
に、これをドクターブレード法を採用することによって
セラミックグリーンシート(セラミック生シート)を形
成し、しかる後、前記セラミックグリーンシートに適当
な打ち抜き加工を施すと共に、複数枚積層し、高温(約
1500℃)で焼成することによって製作される。
The insulating substrate 1 is made into a slurry by adding an appropriate organic solvent or solvent to raw material powder such as alumina ceramics, and a ceramic green sheet (ceramic green sheet) is formed by adopting the doctor blade method. After that, the ceramic green sheets are punched appropriately, and a plurality of them are laminated at a high temperature (about
It is manufactured by firing at 1500 ℃.

前記絶縁基体1には凹部1aの段状上面より側面にかけて
導出しているメタライズ金属層4が形成されており、該
メタライズ金属層4の凹部1a段状上面部には半導体素子
3の電極がボンディングワイヤ5を介して電気的に接続
され、またメタライズ金属層4の絶縁基体1側面部には
外部回路と接続される外部リード端子6が銀ロウ(Ag-C
u合金)等のロウ材を介し取着される。
A metallized metal layer 4 is formed on the insulating substrate 1 so as to extend from the stepped upper surface of the recess 1a to the side surface. The electrode of the semiconductor element 3 is bonded to the recessed portion 1a of the metallized metal layer 4 on the stepped upper surface. An external lead terminal 6 electrically connected through a wire 5 and connected to an external circuit is provided on the side surface of the insulating base 1 of the metallized metal layer 4 with silver solder (Ag-C).
u alloy) or other brazing material.

前記メタライズ金属層4はタングステン(W)、モリブ
デン(Mo)、マンガン(Mn)等の高融点金属粉末から成
り、従来周知のスクリーン印刷法等の厚膜手法を採用す
ることによって絶縁基体1の凹部1a段状上面から側面に
かけて被着形成される。
The metallized metal layer 4 is made of a refractory metal powder such as tungsten (W), molybdenum (Mo), manganese (Mn) or the like. 1a Stepped step Adhesion is formed from the upper surface to the side surface.

前記絶縁基体1側面のメタライズ金属層4に取着された
外部リード端子6は内部に収納する半導体素子3を外部
回路に接続する作用を為し、外部リード端子6を外部回
路に電気的に接続することによって内部に収納された半
導体素子3はメタライズ金属層4及び外部リード端子6
を介し外部回路と電気的に接続されることとなる。
The external lead terminals 6 attached to the metallized metal layer 4 on the side surface of the insulating substrate 1 serve to connect the semiconductor element 3 housed inside to an external circuit, and electrically connect the external lead terminals 6 to the external circuit. As a result, the semiconductor element 3 housed inside the metallized metal layer 4 and the external lead terminals 6
It will be electrically connected to an external circuit via.

前記外部リード端子6はコバール(Fe-Ni-Co合金)や42
Alloy(Fe-Ni合金)等の金属から成り、従来周知の金属
加工法により板状の所定形状に形成される。
The external lead terminal 6 is made of Kovar (Fe-Ni-Co alloy) or 42
It is made of a metal such as an alloy (Fe-Ni alloy), and is formed into a predetermined plate-like shape by a conventionally known metal processing method.

尚、前記外部リード端子6の外表面には該外部リード端
子6と外部回路との電気的接続を良好とするために、ま
た外部リード端子6が酸化腐食するのを防止するために
ニッケル(Ni)、金(Au)等から成る良導電性で、且つ
耐蝕性に優れた金属が従来周知のメッキ方法により被着
されている。
In addition, nickel (Ni) is formed on the outer surface of the external lead terminal 6 in order to improve the electrical connection between the external lead terminal 6 and an external circuit and to prevent the external lead terminal 6 from being oxidized and corroded. ), Gold (Au), or the like, which has a good conductivity and is excellent in corrosion resistance, is deposited by a conventionally known plating method.

また前記絶縁基体1はその上面に絶縁基体1と実質的に
同じ熱膨張係数を有し、かつ表面の中心線平均粗さ(R
a)がRaが≧0.65μmである厚膜形成技術により形成さ
れる絶縁膜7が被着されている。
The insulating substrate 1 has a coefficient of thermal expansion substantially the same as that of the insulating substrate 1 on its upper surface, and the center line average roughness (R
In a), the insulating film 7 formed by the thick film forming technique with Ra ≧ 0.65 μm is deposited.

前記絶縁膜7は絶縁基体1上に、例えば絶縁基体1と同
じ材質であるアルミナセラミックス粉末に適当な有機溶
剤、溶媒を添加混合して得た泥漿物をスクリーン印刷等
の厚膜手法により印刷塗布し、しかる後、これを還元雰
囲気中、高温で焼成することによって絶縁基体1上に被
着される。
The insulating film 7 is applied onto the insulating base 1 by printing a sludge obtained by adding and mixing an alumina ceramic powder, which is the same material as the insulating base 1, with an appropriate organic solvent and a solvent by a thick film method such as screen printing. Then, after that, it is deposited on the insulating substrate 1 by firing at high temperature in a reducing atmosphere.

前記絶縁膜7は厚膜形成技術により形成されることから
絶縁基体1上に強固に接合し、同時にその表面の中心線
平均粗さ(Ra)をRa≧0.65μmの粗いものとなすことか
ら後述する蓋体2を絶縁基体1上に封止材を介して取着
する際、絶縁基体1と封止材との接合面積が大となって
両者は強固に接合し、これによって絶縁基体1上に蓋体
2を極めて強固に取着することが可能となる。
Since the insulating film 7 is formed by the thick film forming technique, it is firmly bonded onto the insulating substrate 1, and at the same time, the center line average roughness (Ra) of its surface is set to be Ra ≧ 0.65 μm. When the lid body 2 is attached to the insulating base 1 via the sealing material, the insulating base 1 and the sealing material have a large bonding area and are firmly bonded to each other. It becomes possible to attach the lid body 2 extremely firmly.

なお、前記絶縁膜7表面の中心線平均粗さ(Ra)がRa<
0.65μmとなると従来の半導体素子収納用パッケージと
同様、絶縁膜7の表面が平滑となり、絶縁膜7上に蓋体
2を強固に取着するのが困難になるため絶縁膜7表面の
中心線平均粗さ(Ra)はRa≧0.65μmの粗いものに特定
される。
The center line average roughness (Ra) of the surface of the insulating film 7 is Ra <
When the thickness is 0.65 μm, the surface of the insulating film 7 becomes smooth, and it becomes difficult to firmly attach the lid 2 onto the insulating film 7 as in the case of the conventional semiconductor element housing package. The average roughness (Ra) is specified as Ra ≧ 0.65 μm.

また前記絶縁膜7はその材質が絶縁基体1と同じ材質よ
り成ることから絶縁基体1と絶縁膜7とは熱膨張係数が
同じとなり、両者に半導体素子3等の発する熱が印加さ
れたとしても両者間に大きな熱応力が発生することはな
く、該熱応力によって絶縁膜7が絶縁基体1より剥離す
ることはない。
Further, since the insulating film 7 is made of the same material as the insulating substrate 1, the insulating substrate 1 and the insulating film 7 have the same coefficient of thermal expansion, and even if heat generated by the semiconductor element 3 or the like is applied to them. No large thermal stress is generated between them, and the insulating film 7 is not separated from the insulating substrate 1 by the thermal stress.

尚、前記絶縁膜7の材質は絶縁基体1と全く同じ材質に
する必要はなく、絶縁基体1との間に熱応力が発生しな
いような絶縁基体1と熱膨張係数が近似するものであれ
ば如何なる材質であってもよい。
The insulating film 7 does not have to be made of the same material as the insulating substrate 1 as long as it has a thermal expansion coefficient similar to that of the insulating substrate 1 so that thermal stress does not occur between the insulating substrate 1 and the insulating substrate 1. Any material may be used.

前記絶縁基体1上面には蓋体2が封止材8を介し取着さ
れ、これによって絶縁基体1の凹部1aはその内部が気密
に封止される。
The lid 2 is attached to the upper surface of the insulating substrate 1 via the sealing material 8, whereby the inside of the recess 1a of the insulating substrate 1 is hermetically sealed.

前記蓋体2は例えば、アルミナセラミックス等の電気絶
縁材料から成り、アルミナセラミックスの粉末を従来周
知のプレス成形法を採用することによって平板状に成形
すると共に、これを約1600℃の温度で焼成することによ
って形成される。
The lid 2 is made of, for example, an electrically insulating material such as alumina ceramics, and alumina ceramic powder is formed into a flat plate shape by adopting a conventionally known press forming method, and is baked at a temperature of about 1600 ° C. Formed by.

前記蓋体2は、その下面に予め封止材8が被着されてお
り、該封止材8は絶縁基体1と蓋体2を接合させ、絶縁
基体に設けた凹部1aを気密に封止する作用を為す。この
封止材8はエポキシ樹脂や低融点ガラス粉末に有機溶
剤、溶媒を添加混合した材料からなり、従来周知のスク
リーン印刷等の厚膜手法を採用することによって蓋体2
の下面に被着される。
The lid 2 has a lower surface to which a sealing material 8 is applied in advance. The sealing material 8 joins the insulating base 1 and the lid 2 to hermetically seal the recess 1a provided in the insulating base. Make the action. The sealing material 8 is made of a material obtained by adding and mixing an organic solvent and a solvent to an epoxy resin or a low melting point glass powder, and by adopting a conventionally known thick film technique such as screen printing, the lid body 2 is formed.
Is attached to the lower surface of.

かくして、絶縁基体1の凹部1a底面に半導体素子3を接
着剤を介し取着すると共に、半導体素子3の各電極をメ
タライズ金属層4にボンディングワイヤ5を介して電気
的に接続させ、しかる後、絶縁基体1の上面に蓋体2を
ガラス、樹脂等の封止材7により取着し、絶縁基体1の
凹部1aを塞ぐことによって最終製品である半導体装置と
なる。
Thus, the semiconductor element 3 is attached to the bottom surface of the concave portion 1a of the insulating substrate 1 with an adhesive agent, and each electrode of the semiconductor element 3 is electrically connected to the metallized metal layer 4 via the bonding wire 5, and thereafter, The lid 2 is attached to the upper surface of the insulating base 1 with a sealing material 7 such as glass or resin, and the recess 1a of the insulating base 1 is closed to complete the semiconductor device as a final product.

(考案の効果) 本考案の半導体素子収納用パッケージによれば絶縁基体
の封止材が接合する表面に絶縁基体と実質的に同一の熱
膨張係数を有し、且つ表面の中心線平均粗さ(Ra)がRa
≧0.65μmである厚膜形成技術により形成される絶縁膜
を被着させたことから絶縁基体上に蓋体を封止材を介し
て取着した場合、絶縁基体と封止材の接合強度を極めて
強いものとなすことができ、絶縁基体と封止材との間に
半導体素子が作動時等に発する熱が繰り返し印加された
としても両者間に剥離を発生することは皆無となり、そ
の結果、絶縁基体に設けた凹部の気密封止を完全として
該凹部内に収納される半導体素子を長期間にわたり正
常、かつ安定に作動させることが可能となる。
(Effects of the Invention) According to the package for housing a semiconductor device of the present invention, the surface of the insulating substrate on which the encapsulant is bonded has substantially the same coefficient of thermal expansion as the insulating substrate, and the center line average roughness of the surface. (Ra) is Ra
Since the insulating film formed by the thick film forming technique of ≧ 0.65 μm is applied, the bonding strength between the insulating base and the sealing material can be improved when the lid is mounted on the insulating base via the sealing material. It can be made extremely strong, and even if heat generated during operation of the semiconductor element is repeatedly applied between the insulating substrate and the sealing material, no peeling occurs between the two, and as a result, By completely hermetically sealing the recess provided in the insulating base, the semiconductor element housed in the recess can be normally and stably operated for a long period of time.

【図面の簡単な説明】[Brief description of drawings]

第1図は本考案の半導体素子収納用パッケージの一実施
例を示す断面図、第2図は第1図に示す半導体素子収納
用パッケージの絶縁基体の平面図、第3図は従来の半導
体素子収納用パッケージの断面図、第4図は第3図に示
すパッケージの絶縁基体の平面図である。 1:絶縁基体、1a:凹部 2:蓋体、4:メタライズ金属層 6:外部リード端子、7:絶縁膜 8:封止材
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device housing package of the present invention, FIG. 2 is a plan view of an insulating substrate of the semiconductor device housing package shown in FIG. 1, and FIG. 3 is a conventional semiconductor device. FIG. 4 is a sectional view of the storage package, and FIG. 4 is a plan view of the insulating base of the package shown in FIG. 1: Insulating substrate, 1a: Recessed part 2: Lid, 4: Metallized metal layer 6: External lead terminal, 7: Insulating film 8: Sealing material

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 【請求項1】半導体素子を収容するための凹部を有する
絶縁基体と蓋体とから成り、絶縁基体上に該絶縁基体の
凹部を塞ぐよう蓋体を封止材を介し取着するようになし
た半導体素子収納用パッケージにおいて、前記絶縁基体
の少なくとも封止材が接合する表面に絶縁基体と実質的
に同一の熱膨張係数を有し、且つ厚膜形成技術により形
成される表面の中心線平均粗さ(Ra)がRa≧0.65μmで
ある絶縁膜を被着させたことを特徴とする半導体素子収
納用パッケージ。
1. An insulating base having a recess for accommodating a semiconductor element and a lid, wherein the lid is attached to the insulating base via a sealing material so as to close the recess of the insulating base. In the package for accommodating a semiconductor element, at least the surface of the insulating substrate to which the sealing material is bonded has a coefficient of thermal expansion substantially the same as that of the insulating substrate, and the center line average of the surface formed by the thick film forming technique. A package for accommodating a semiconductor element, characterized in that an insulating film having a roughness (Ra) of Ra ≧ 0.65 μm is applied.
JP12545489U 1989-10-26 1989-10-26 Package for storing semiconductor devices Expired - Lifetime JPH0745962Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12545489U JPH0745962Y2 (en) 1989-10-26 1989-10-26 Package for storing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12545489U JPH0745962Y2 (en) 1989-10-26 1989-10-26 Package for storing semiconductor devices

Publications (2)

Publication Number Publication Date
JPH0363942U JPH0363942U (en) 1991-06-21
JPH0745962Y2 true JPH0745962Y2 (en) 1995-10-18

Family

ID=31673324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12545489U Expired - Lifetime JPH0745962Y2 (en) 1989-10-26 1989-10-26 Package for storing semiconductor devices

Country Status (1)

Country Link
JP (1) JPH0745962Y2 (en)

Also Published As

Publication number Publication date
JPH0363942U (en) 1991-06-21

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