JP2828531B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP2828531B2
JP2828531B2 JP30452891A JP30452891A JP2828531B2 JP 2828531 B2 JP2828531 B2 JP 2828531B2 JP 30452891 A JP30452891 A JP 30452891A JP 30452891 A JP30452891 A JP 30452891A JP 2828531 B2 JP2828531 B2 JP 2828531B2
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring layer
metallized wiring
package
noise
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP30452891A
Other languages
Japanese (ja)
Other versions
JPH05144961A (en
Inventor
千尋 牧原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP30452891A priority Critical patent/JP2828531B2/en
Publication of JPH05144961A publication Critical patent/JPH05144961A/en
Application granted granted Critical
Publication of JP2828531B2 publication Critical patent/JP2828531B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a semiconductor device housing package for housing a semiconductor device.

【0002】[0002]

【従来の技術】従来、コンピューター等の情報処理装置
には半導体素子を半導体素子収納用パッケージ内に気密
に収容した半導体装置が使用されている。
2. Description of the Related Art Conventionally, a semiconductor device in which a semiconductor element is hermetically housed in a semiconductor element housing package is used for an information processing apparatus such as a computer.

【0003】かかる情報処理装置に使用される半導体装
置は通常、図2に示すように、先ずアルミナセラミック
ス等の電気絶縁材料から成り、その上面略中央部に半導
体素子を収容するための凹部21a及び該凹部21a周
辺から外周部にかけて導出されたタングステン、モリブ
デン、マンガン等の高融点金属粉末から成る多数のメタ
ライズ配線層22を有する絶縁基体21と、半導体素子
を外部電気回路に電気的に接続するために前記メタライ
ズ配線層22に銀ロウ等のロウ材を介して取着された外
部リード端子23と、蓋体24とで構成される半導体素
子収納用パッケージを準備し、次に前記半導体素子収納
用パッケージの絶縁基体21の凹部21a底面に半導体
素子25をガラス、樹脂、ロウ材等の接着剤を介して載
置固定するとともに該半導体素子25の各電極をボンデ
ィングワイヤ26を介してメタライズ配線層22に電気
的に接続させ、しかる後、前記絶縁基体21の上面に蓋
体24をガラス、樹脂等の封止材を介して接合させ、絶
縁基体21と蓋体24とから成る容器内部に半導体素子
25を気密に封止することによって製作される。
As shown in FIG. 2, a semiconductor device used in such an information processing apparatus is generally made of an electrically insulating material such as alumina ceramics, and has a recess 21a for accommodating a semiconductor element at a substantially central portion of the upper surface thereof. In order to electrically connect the semiconductor element to an external electric circuit, the insulating base 21 has a large number of metallized wiring layers 22 made of a high melting point metal powder such as tungsten, molybdenum, manganese or the like drawn out from the periphery of the concave portion 21a to the outer peripheral portion. Then, a semiconductor device housing package including an external lead terminal 23 attached to the metallized wiring layer 22 via a brazing material such as silver brazing and a lid 24 is prepared, and then the semiconductor device housing package is prepared. The semiconductor element 25 is mounted and fixed on the bottom surface of the concave portion 21a of the insulating base 21 of the package via an adhesive such as glass, resin, or brazing material. Each electrode of the semiconductor element 25 is electrically connected to the metallized wiring layer 22 via a bonding wire 26, and then the lid 24 is placed on the upper surface of the insulating base 21 via a sealing material such as glass or resin. It is manufactured by joining and sealingly sealing the semiconductor element 25 inside a container including the insulating base 21 and the lid 24.

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置に使
用されている半導体素子収納用パッケージでは絶縁基体
を構成するアルミナセラミック等の電気絶縁材料のノイ
ズに対するシールド効果が低いこと、及び近時半導体素
子は高速、且つ低電圧駆動が行われるようになってきて
おり、半導体装置の外部からメタライズ配線層を介して
浸入する高調波ノイズの影響を受けやすいと同時にメタ
ライズ配線層を伝搬する信号に含まれる高調波ノイズが
半導体装置の外部に放出され易いものとなってきている
等から、半導体装置の外部近接位置にノイズ発生源があ
ると絶縁基体に被着形成されたメタライズ配線層を伝搬
する信号にノイズが極めて容易に入り込み、これがその
まま半導体素子に伝搬されて半導体素子を誤動作させて
しまったり、あるいは半導体装置の外部近接位置にノイ
ズに対して影響を受け易い電子機器等があると半導体装
置より放出されたノイズが該電子機器等に悪影響を及ぼ
してしまうという欠点を招来した。
In a package for housing a semiconductor element used in a conventional semiconductor device, an electric insulating material such as alumina ceramic constituting an insulating base has a low shielding effect against noise. Is driven at a high speed and at a low voltage, and is susceptible to harmonic noise entering from outside the semiconductor device via the metallization wiring layer and is included in a signal propagating through the metallization wiring layer. Harmonic noise is becoming more likely to be emitted to the outside of the semiconductor device. If there is a noise source at a position close to the outside of the semiconductor device, a signal propagating through the metallized wiring layer formed on the insulating base will be affected. Noise enters very easily, and this propagates to the semiconductor element as it is, causing the semiconductor element to malfunction, or It was lead to disadvantage external proximity position easily electronic devices sensitive to noise is there when released from the semiconductor device to the noise of the semiconductor device adversely affects the electronic equipment and the like.

【0005】[0005]

【発明の目的】本発明は前記欠点に鑑み案出されたもの
でその目的は、メタライズ配線層を伝搬する信号からの
ノイズを有効に除去し、半導体素子を正常、且つ安定に
作動させるとともに半導体装置の外部に対してノイズを
放出しにくい半導体素子収納用パッケージを提供するこ
とにある。
SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned disadvantages, and has as its object to effectively remove noise from a signal propagating through a metallized wiring layer, to operate a semiconductor element normally and stably, and to provide a semiconductor device. An object of the present invention is to provide a package for housing a semiconductor element which does not easily emit noise to the outside of the device.

【0006】[0006]

【課題を解決するための手段】本発明は、半導体素子が
載置固定される載置部及び該半導体素子の各電極を外部
電気回路に接続するためのメタライズ配線層を有する絶
縁基体と蓋体とから成る半導体素子収納用パッケージで
あって、前記メタライズ配線層の少なくとも一部がフェ
ライトからなる被覆層で覆われていることを特徴とする
ものである。
SUMMARY OF THE INVENTION The present invention relates to an insulating base and a cover having a mounting portion on which a semiconductor element is mounted and fixed, and a metallized wiring layer for connecting each electrode of the semiconductor element to an external electric circuit. Wherein at least a part of the metallized wiring layer is covered with a coating layer made of ferrite.

【0007】[0007]

【実施例】次に本発明を添付図面に基づき詳細に説明す
る。
BRIEF DESCRIPTION OF THE DRAWINGS FIG.

【0008】図1は本発明の半導体素子収納用パッケー
ジの一実施例を示し、1はアルミナセラミックス等の電
気絶縁材料から成る絶縁基体、2は同じく電気絶縁材料
から成る蓋体である。この絶縁基体1と蓋体2とで半導
体素子4を収容するための容器3が構成される。
FIG. 1 shows an embodiment of a package for accommodating a semiconductor element according to the present invention, wherein 1 is an insulating base made of an electrically insulating material such as alumina ceramics, and 2 is a lid made of the same electrically insulating material. The insulating base 1 and the lid 2 constitute a container 3 for housing the semiconductor element 4.

【0009】前記絶縁基体1はその上面中央部に半導体
素子4を収容するための空所を形成する段状の凹部1a
が設けてあり、該凹部1a底面には半導体素子4がエポ
キシ樹脂等の接着剤を介して載置固定される。
The insulating base 1 has a stepped recess 1a in the center of the upper surface thereof to form a space for accommodating the semiconductor element 4.
The semiconductor element 4 is placed and fixed on the bottom surface of the concave portion 1a via an adhesive such as epoxy resin.

【0010】前記絶縁基体1は例えば、アルミナセラミ
ックス等の電気絶縁材料より成り、アルミナ(Al2 O
3 )、シリカ(SiO2 )、カルシア(CaO)、マグ
ネシア(MgO)等の原料粉末に適当な有機溶剤、溶媒
を添加混合して泥漿状となすとともにこれを従来周知の
ドクターブレード法を採用することによってセラミック
グリーンシート(セラミック生シート)を形成し、しか
る後、前記セラミックグリーンシートに適当な打ち抜き
加工を施すとともに複数枚積層し、高温(約1600
℃)で焼成することによって製作される。
The insulating substrate 1 is made of, for example, an electrically insulating material such as alumina ceramics, and is made of alumina (Al 2 O).
3) A raw material powder such as silica (SiO2), calcia (CaO), magnesia (MgO) or the like is mixed with an appropriate organic solvent and solvent to form a slurry, which is formed by a conventionally known doctor blade method. Then, a ceramic green sheet (ceramic green sheet) is formed, and after that, the ceramic green sheet is subjected to an appropriate punching process and a plurality of sheets are laminated, and a high temperature (about 1600) is obtained.
C).

【0011】また、前記絶縁基体1には凹部1aの段状
上面から容器3の外部に導出するメタライズ配線層5が
形成されており、該メタライズ配線層5の凹部1a段状
上面部には半導体素子4の各電極がボンディングワイヤ
ー6を介して電気的に接続され、また容器3の外部に導
出された部位には外部電気回路と接続される外部リード
端子7が銀ロウ等のロウ材を介し取着される。
A metallized wiring layer 5 extending from the stepped upper surface of the concave portion 1a to the outside of the container 3 is formed on the insulating base 1, and a semiconductor upper surface is formed on the stepped upper surface of the concave portion 1a of the metallized wiring layer 5. Each electrode of the element 4 is electrically connected via a bonding wire 6, and an external lead terminal 7 connected to an external electric circuit is provided at a portion led out of the container 3 via a brazing material such as silver brazing. Be attached.

【0012】前記メタライズ配線層5はタングステン
(W)、モリブデン(Mo)、マンガン(Mn)高融点
金属粉末から成り、該高融点金属粉末に適当な有機溶
剤、溶媒を添加混合して得た金属ペーストを従来周知の
スクリーン印刷法等の厚膜手法を採用し、絶縁基体1と
なるセラミックグリーンシートに予め被着させておくこ
とによって絶縁基体1の凹部1a段状上面から容器3の
外部に導出するように被着形成される。
The metallized wiring layer 5 is made of tungsten (W), molybdenum (Mo), manganese (Mn) refractory metal powder, and a metal obtained by adding an appropriate organic solvent and solvent to the refractory metal powder. The paste is applied to a ceramic green sheet serving as the insulating substrate 1 in advance by employing a conventionally known thick film method such as a screen printing method, so that the paste is led out of the container 3 from the stepped upper surface of the concave portion 1a of the insulating substrate 1. Is formed.

【0013】尚、前記メタライズ配線層5はその露出す
る外表面にニッケル、金等の良導電性で、且つ耐食性に
優れた金属をメッキ法により1.0乃至20.0μmの
厚みに層着させておくと、メタライズ配線層5の酸化腐
食を有効に防止することができるとともにメタライズ配
線層5とボンディングワイヤー6との接続及びメタライ
ズ配線層5と外部リード端子7とのロウ付け取着が極め
て強固なものとなる。
The metallized wiring layer 5 is formed by plating a metal having good conductivity and excellent corrosion resistance, such as nickel or gold, on the exposed outer surface to a thickness of 1.0 to 20.0 μm by plating. By doing so, the oxidation corrosion of the metallized wiring layer 5 can be effectively prevented, and the connection between the metallized wiring layer 5 and the bonding wire 6 and the brazing and attachment between the metallized wiring layer 5 and the external lead terminals 7 are extremely strong. It becomes something.

【0014】従って、前記メタライズ配線層5の酸化腐
食を防止し、メタライズ配線層5とボンディングワイヤ
ー6との接続及びメタライズ配線層5と外部リード端子
7とのロウ付けを強固なものとなすにはメタライズ配線
5の露出外表面にニッケル、金等を1.0乃至20.0
μmの厚みに層着させておくことが好ましい。
Therefore, in order to prevent the metallized wiring layer 5 from being oxidized and corroded, and to make the connection between the metallized wiring layer 5 and the bonding wire 6 and the brazing between the metallized wiring layer 5 and the external lead terminals 7 robust. Nickel, gold, or the like is applied to the exposed outer surface of the metallized wiring 5 from 1.0 to 20.0.
It is preferable to coat the layer to a thickness of μm.

【0015】また、前記メタライズ配線層5は凹部1a
の段状上面部の一部がフェライトから成る被覆層9で覆
われており、該フェライトから成る被覆層9は高透磁率
を有することから、高調波等の高い周波数成分に対して
高インピーダンスを有し、内部に収容する半導体素子4
が高速駆動し、高調波ノイズを含んだ信号がメタライズ
配線層5を伝搬したとしても、その伝搬信号中のノイズ
は前記フェライトからなる被覆層9によって選択的に吸
収除去され、ノイズが半導体素子4に伝搬されたり、外
部に放出されることはない。従って、内部に収容する半
導体素子4には常に正確な信号がメタライズ配線層5を
介して伝搬されることとなり、半導体素子4を正常、且
つ安定に作動させることが可能となるとともに半導体装
置の外部に対してノイズを放出することもない。
Further, the metallized wiring layer 5 has a concave portion 1a.
Is covered with a coating layer 9 made of ferrite, and the coating layer 9 made of ferrite has a high magnetic permeability, so that it has a high impedance with respect to high frequency components such as harmonics. Semiconductor element 4 having and housed inside
Is driven at high speed, and even if a signal containing harmonic noise propagates through the metallized wiring layer 5, noise in the propagated signal is selectively absorbed and removed by the coating layer 9 made of ferrite, and the noise is reduced. Is not transmitted to the outside or emitted outside. Therefore, an accurate signal is always propagated to the semiconductor element 4 housed therein through the metallization wiring layer 5, so that the semiconductor element 4 can be operated normally and stably, and the semiconductor device 4 can be operated externally. No noise is emitted.

【0016】前記被覆層9を構成するフェライトはMn
−Zn系フェライト、Ni−Zn系フェライト、Mg−
Mn系フェライトが使用され、フェライト粉末に適当な
有機溶剤、溶媒を添加混合して得たフェライトペースト
を従来周知のスクリーン印刷法等の厚膜手法を採用して
メタライズ配線層5の一部表面に印刷塗布し、しかる
後、これを焼成することによって絶縁基体1の凹部1a
段状上面に位置するメタライズ配線層5表面に該メタラ
イズ配線層5を覆うごとく被着される。
The ferrite constituting the coating layer 9 is Mn.
-Zn ferrite, Ni-Zn ferrite, Mg-
A Mn-based ferrite is used, and a ferrite paste obtained by adding and mixing an appropriate organic solvent and a solvent to the ferrite powder is applied to a part of the surface of the metallized wiring layer 5 by employing a conventionally known thick film method such as a screen printing method. After printing and coating, and then firing, the concave portion 1a of the insulating substrate 1 is formed.
The metallized wiring layer 5 is disposed on the surface of the metallized wiring layer 5 located on the stepped upper surface so as to cover the metallized wiring layer 5.

【0017】また、前記被覆層9はメタライズ配線層5
の表面で内部に収容する半導体素子4にできる限り近い
位置に被着させておくとメタライズ配線層5を伝搬する
信号にノイズが入り込んだとしてもそのノイズを半導体
素子4に伝搬される直前に全て吸収除去することができ
る。従って、前記被覆層9はメタライズ配線層5の表面
で内部に収容する半導体素子4にできる限り近い位置に
被覆させておくことが好ましい。
The covering layer 9 is formed of a metallized wiring layer 5.
If the noise is introduced into the signal propagating through the metallization wiring layer 5, the noise is applied immediately before the noise is propagated to the semiconductor element 4. Can be absorbed and removed. Therefore, it is preferable that the coating layer 9 is coated on the surface of the metallized wiring layer 5 as close as possible to the semiconductor element 4 housed therein.

【0018】一方、前記メタライズ配線層5にロウ付け
される外部リード端子7は内部に収容する半導体素子4
を外部電気回路に接続する作用を為し、外部リード端子
7を外部電気回路に接続させることによって内部に収容
される半導体素子4はメタライズ配線層5及び外部リー
ド端子7を介して外部電気回路と電気的に接続されるこ
ととなる。
On the other hand, the external lead terminals 7 brazed to the metallized wiring layer 5 have semiconductor elements 4 housed therein.
By connecting the external lead terminal 7 to the external electric circuit, the semiconductor element 4 housed therein is connected to the external electric circuit via the metallized wiring layer 5 and the external lead terminal 7. It will be electrically connected.

【0019】前記外部リード端子7は42アロイ(Fe
−Ni合金)、コバール(Fe−Ni−Co合金)等の
金属から成り、42アロイ等のインゴット(塊)を圧延
加工法や打ち抜き等、従来周知の金属加工を施すことに
よって所定の板状に形成される。
The external lead terminal 7 is made of a 42 alloy (Fe
-Ni alloy), Kovar (Fe-Ni-Co alloy), etc., into a predetermined plate shape by subjecting an ingot (lumps) such as 42 alloy to a conventionally known metal working such as a rolling method or punching. It is formed.

【0020】尚、前記外部リード端子7はその外表面に
ニッケル、金等の耐食性に優れ、且つ良電導性の金属を
メッキにより1.0乃至20.0μmの厚みに層着させ
ておくと外部リード端子7の酸化腐食を有効に防止する
とともに外部リード端子7と外部電気回路との電気的接
続を良好なものとなすことができる。そのため外部リー
ド端子7はその外表面にニッケル、金等をメッキにより
1.0乃至20.0μmの厚みに層着させておくことが
好ましい。
The external lead terminal 7 may be formed by plating a metal having excellent corrosion resistance, such as nickel and gold, and good conductivity on the outer surface thereof to a thickness of 1.0 to 20.0 μm by plating. Oxidative corrosion of the lead terminal 7 can be effectively prevented, and good electrical connection between the external lead terminal 7 and the external electric circuit can be achieved. Therefore, it is preferable that the external lead terminal 7 be plated with nickel, gold, or the like on the outer surface to a thickness of 1.0 to 20.0 μm by plating.

【0021】前記絶縁基体1はまたその上面にメタライ
ズ金属層10が被着されており、該メタライズ金属層1
0には蓋体2が封止材Aを介して接合され、これによっ
て容器3の内部に半導体素子4が気密に封止される。
The insulating substrate 1 has a metallized metal layer 10 on its upper surface.
The lid 2 is bonded to the cover 2 via a sealing material A, whereby the semiconductor element 4 is hermetically sealed inside the container 3.

【0022】前記メタライズ金属層10はタングステ
ン、モリブデン、マンガン、銀 パラジウム等の金属粉
末から成り、該金属粉末に適当な有機溶剤、溶媒を添加
混合して得た金属ペーストを絶縁基体1の上面に従来周
知のスクリーン印刷法等の厚膜手法を採用して印刷塗布
し、しかる後、これを高温で焼き付けることによって絶
縁基体1の上面に被着される。
The metallized metal layer 10 is made of a metal powder such as tungsten, molybdenum, manganese, silver and palladium. A metal paste obtained by adding a suitable organic solvent and a solvent to the metal powder is applied to the upper surface of the insulating substrate 1. Print coating is performed by employing a conventionally known thick film method such as a screen printing method, and thereafter, the resultant is baked at a high temperature to be adhered to the upper surface of the insulating substrate 1.

【0023】また、前記絶縁基体1の上面に接合される
蓋体2はアルミナセラミックス等の電気絶縁材料から成
り、その下面外周部に予めメタライズ金属層11を被着
させておき、該メタライズ金属層11を絶縁基体1上面
のメタライズ金属層10に封止材Aを介し接合させるこ
とによって蓋体2は絶縁基体1に接合されることとな
る。
The lid 2 joined to the upper surface of the insulating base 1 is made of an electrically insulating material such as alumina ceramics, and a metallized metal layer 11 is previously applied to the outer peripheral portion of the lower surface. The lid 2 is joined to the insulating base 1 by joining the base 11 to the metallized metal layer 10 on the upper surface of the insulating base 1 via the sealing material A.

【0024】尚、前記蓋体2は、例えばアルミナ(Al
2 O3 )、シリカ(CaO2 )、カルシア(CaO)、
マグネシア(MgO)等の原料粉末を図1に示すような
蓋体2に対応した形状を有するプレス型内に充填させる
とともに一定圧力を印加して形成し、その後これを約1
500℃の温度で焼成することによって製作され、また
下面外周部に被着されるメタライズ金属層11はタング
ステン、モリブデン、マンガン、銀 パラジウム等の金
属粉末から成り、該金属粉末に適当な有機溶剤、溶媒を
添加混合して得た金属ペーストを蓋体2下面外周部に従
来周知のスクリーン印刷法等の厚膜手法を採用して印刷
塗布し、しかる後、これを高温で焼き付けることによっ
て蓋体2の下面外周部に被着される。
The lid 2 is made of, for example, alumina (Al).
2 O3), silica (CaO2), calcia (CaO),
A raw material powder such as magnesia (MgO) is filled in a press mold having a shape corresponding to the lid 2 as shown in FIG. 1 and is formed by applying a constant pressure.
The metallized metal layer 11 which is manufactured by firing at a temperature of 500 ° C. and which is deposited on the outer peripheral portion of the lower surface is made of a metal powder such as tungsten, molybdenum, manganese, silver, palladium, etc. A metal paste obtained by adding and mixing a solvent is printed and applied to the outer peripheral portion of the lower surface of the lid 2 by employing a conventionally known thick film method such as a screen printing method, and thereafter, the resultant is baked at a high temperature to thereby form the lid 2. Is attached to the outer peripheral portion of the lower surface of the.

【0025】また、前記絶縁基体1の上面に蓋体2を接
合させる封止材Aは例えば、融点が低く、接合時の熱に
よって半導体素子4の特性に影響を与えることが少ない
半田が使用され、該半田から成る封止材Aは絶縁基体1
と蓋体2との接合の作業性を容易とするために蓋体2に
被着させたメタライズ金属層11に予め被着されてい
る。
The sealing material A for joining the lid 2 to the upper surface of the insulating base 1 is, for example, a solder having a low melting point and little affecting the characteristics of the semiconductor element 4 due to heat at the time of joining. The sealing material A made of the solder is the insulating base 1
In order to facilitate the workability of joining the cover and the cover 2, the cover is previously attached to the metallized metal layer 11 attached to the cover 2.

【0026】かくして、本発明の半導体素子収納用パッ
ケージによれば絶縁基体1の凹部1a底面に半導体素子
4を接着剤を介して搭載固定するとともに半導体素子4
の各電極をメタライズ配線層5にボンディングワイヤー
6を介して電気的に接続し、しかる後、絶縁基体1の上
面に蓋体2を半田等から成る封止材Aを介して接合し、
容器3の内部に半導体素子4を気密に封入することによ
って最終製品としての半導体装置となる。
Thus, according to the semiconductor device housing package of the present invention, the semiconductor device 4 is mounted and fixed on the bottom surface of the concave portion 1a of the insulating base 1 with an adhesive.
Are electrically connected to the metallized wiring layer 5 via bonding wires 6, and then the lid 2 is joined to the upper surface of the insulating base 1 via a sealing material A made of solder or the like.
A semiconductor device as a final product is obtained by hermetically sealing the semiconductor element 4 in the container 3.

【0027】[0027]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、半導体素子の各電極を外部電気回路に接続する
メタライズ配線層の一部にフェライトから成る被覆層を
被着させたことから、メタライズ配線層を伝搬する信号
にノイズが入り込んだとしても該ノイズは被覆層によっ
て吸収除去され、半導体素子に伝搬されることはなく、
また半導体装置の外部に放出されることもない。従って
内部に収容する半導体素子を常に正常、且つ安定に作動
させることが可能となると同時に半導体装置の外部に対
して有害なノイズを放出することを防止できる。
According to the package for housing a semiconductor element of the present invention, since a coating layer made of ferrite is applied to a part of a metallized wiring layer for connecting each electrode of the semiconductor element to an external electric circuit, the metallized layer is formed. Even if noise enters a signal propagating through the wiring layer, the noise is absorbed and removed by the covering layer, and is not propagated to the semiconductor element.
In addition, there is no emission to the outside of the semiconductor device. Therefore, it is possible to always and normally operate the semiconductor element housed therein, and to prevent emission of harmful noise to the outside of the semiconductor device.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a semiconductor element storage package according to the present invention.

【図2】従来の半導体素子収納用パッケージの断面図で
ある。
FIG. 2 is a cross-sectional view of a conventional semiconductor element storage package.

【符号の説明】[Explanation of symbols]

1・・・絶縁基体 1a・・凹部 2・・・蓋体 4・・・半導体素子 5・・・メタライズ配線層 7・・・外部リード端子 9・・・被覆層 A・・・封止材 DESCRIPTION OF SYMBOLS 1 ... Insulating base 1a ... Depression 2 ... Lid 4 ... Semiconductor element 5 ... Metallized wiring layer 7 ... External lead terminal 9 ... Coating layer A ... Sealing material

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体素子が載置固定される載置部及び該
半導体素子の各電極を外部電気回路に接続するためのメ
タライズ配線層を有する絶縁基体と蓋体とから成る半導
体素子収納用パッケージであって、前記メタライズ配線
層の少なくとも一部がフェライトからなる被覆層で覆わ
れていることを特徴とする半導体素子収納用パッケー
ジ。
1. A semiconductor element storage package comprising: a mounting portion on which a semiconductor element is mounted and fixed; an insulating base having a metallized wiring layer for connecting each electrode of the semiconductor element to an external electric circuit; and a lid. Wherein at least a part of the metallized wiring layer is covered with a coating layer made of ferrite.
JP30452891A 1991-11-20 1991-11-20 Package for storing semiconductor elements Expired - Fee Related JP2828531B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30452891A JP2828531B2 (en) 1991-11-20 1991-11-20 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30452891A JP2828531B2 (en) 1991-11-20 1991-11-20 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH05144961A JPH05144961A (en) 1993-06-11
JP2828531B2 true JP2828531B2 (en) 1998-11-25

Family

ID=17934099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30452891A Expired - Fee Related JP2828531B2 (en) 1991-11-20 1991-11-20 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP2828531B2 (en)

Also Published As

Publication number Publication date
JPH05144961A (en) 1993-06-11

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