JPH05326740A - Package for housing semiconductor element - Google Patents
Package for housing semiconductor elementInfo
- Publication number
- JPH05326740A JPH05326740A JP12861392A JP12861392A JPH05326740A JP H05326740 A JPH05326740 A JP H05326740A JP 12861392 A JP12861392 A JP 12861392A JP 12861392 A JP12861392 A JP 12861392A JP H05326740 A JPH05326740 A JP H05326740A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- metallized wiring
- wiring layer
- metallized
- wiring layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージの改良に関するもので
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor element housing package for housing a semiconductor element.
【０００２】[0002]
【従来の技術】従来、コンピューター等の情報処理装置
には半導体素子を半導体素子収納用パッケージ内に気密
に収容した半導体装置が実装されている。2. Description of the Related Art Conventionally, a semiconductor device in which a semiconductor element is hermetically housed in a semiconductor element housing package is mounted on an information processing apparatus such as a computer.
【０００３】かかる情報処理装置に実装される半導体装
置は通常、図３に示すように、先ずアルミナセラミック
ス等の電気絶縁材料から成り、その上面略中央部に半導
体素子を収容するための凹部21a 及び該凹部21a 周辺か
ら外周部にかけて導出されたタングステン、モリブデ
ン、マンガン等の高融点金属粉末から成る複数個のメタ
ライズ配線層22を有する絶縁基体21と、半導体素子を外
部電気回路に電気的に接続するために前記メタライズ配
線層22に銀ロウ等のロウ材を介して取着された外部リー
ド端子23と、蓋体24とで構成される半導体素子収納用パ
ッケージを準備し、次に前記半導体素子収納用パッケー
ジの絶縁基体21の凹部21a 底面に半導体素子25をガラ
ス、樹脂、ロウ材等の接着剤を介して載置固定するとと
もに該半導体素子25の各電極をボンディングワイヤ26を
介してメタライズ配線層22に電気的に接続させ、しかる
後、前記絶縁基体21の上面に蓋体24をガラス、樹脂等の
封止材を介して接合させ、絶縁基体21と蓋体24とから成
る容器内部に半導体素子25を気密に封止することによっ
て製作される。As shown in FIG. 3, a semiconductor device mounted on such an information processing apparatus is usually made of an electrically insulating material such as alumina ceramics, and has a recess 21a for accommodating a semiconductor element in a substantially central portion of its upper surface. An insulating substrate 21 having a plurality of metallized wiring layers 22 made of a refractory metal powder such as tungsten, molybdenum, or manganese, which is led out from the periphery of the recess 21a to the outer periphery, and a semiconductor element are electrically connected to an external electric circuit. For this purpose, a package for storing a semiconductor element, which is composed of an external lead terminal 23 attached to the metallized wiring layer 22 via a brazing material such as silver solder, and a lid 24 is prepared. The semiconductor element 25 is mounted and fixed on the bottom surface of the concave portion 21a of the insulating base body 21 of the package for use with an adhesive such as glass, resin, or brazing material, and each electrode of the semiconductor element 25 is bonded to It is electrically connected to the metallized wiring layer 22 via a bonding wire 26, and then the lid 24 is bonded to the upper surface of the insulating base 21 via a sealing material such as glass or resin to cover the insulating base 21. It is manufactured by hermetically sealing a semiconductor element 25 inside a container including a body 24.
【０００４】しかしながら、近時、コンピューター等の
情報処理装置は情報の高速処理化が急激に進んでおり、
該情報処理装置に情報を高速処理させるために半導体素
子を高速で駆動させた場合、半導体素子より高調波ノイ
ズが発生し、これが電気信号とともにメタライズ配線層
を伝播して外部電気回路に接続されている他の半導体装
置に入り込み、他の半導体装置に誤動作を起こさせて情
報処理装置を正常に作動させることができないという欠
点を有していた。However, recently, in information processing devices such as computers, high-speed processing of information is rapidly progressing,
When a semiconductor element is driven at high speed for the information processing apparatus to process information at high speed, harmonic noise is generated from the semiconductor element and propagates through the metallized wiring layer together with an electric signal and is connected to an external electric circuit. It has a drawback that it cannot enter into another semiconductor device that is present and malfunctions the other semiconductor device to normally operate the information processing device.
【０００５】そこで上記欠点を解消するためにメタライ
ズ配線層に抵抗値が数百Ωの抵抗体を直列に接続し、メ
タライズ配線層を伝播する高調波ノイズを抵抗体で減衰
させて他の半導体装置へのノイズの入り込みを有効に防
止することが考えられる。Therefore, in order to solve the above-mentioned drawbacks, a resistor having a resistance value of several hundreds Ω is connected in series to the metallized wiring layer, and the harmonic noise propagating through the metallized wiring layer is attenuated by the resistor so that another semiconductor device can be obtained. It can be considered to effectively prevent noise from entering the.
【０００６】[0006]
【発明が解決しようとする課題】しかしながら、メタラ
イズ配線層に抵抗値が数百Ω以上の抵抗体を直列に接続
し、該抵抗体によって高調波ノイズを減衰させた場合、
抵抗体の抵抗値が数百Ω以上と大きいためメタライズ配
線層を伝播する電気信号も同時に大きく減衰されてしま
い、その結果、半導体素子に出し入れされる電気信号が
小さくなり、半導体素子を正常、且つ安定に作動させる
ことが不可となってしまう欠点を誘発した。However, when a resistor having a resistance value of several hundreds Ω or more is connected in series to the metallized wiring layer and harmonic noise is attenuated by the resistor,
Since the resistance value of the resistor is as large as several hundreds of Ω or more, the electric signal propagating through the metallized wiring layer is also greatly attenuated at the same time, and as a result, the electric signal which is taken in and out of the semiconductor element is reduced, and the semiconductor element is normally It caused a defect that it became impossible to operate stably.
【０００７】[0007]
【発明の目的】本発明は上記諸欠点に鑑み案出されたも
ので、その目的は内部に収容する半導体素子の発するノ
イズがメタライズ配線層を介して外部電気回路に伝播さ
れるのを有効に防止し、該ノイズによって外部電気回路
に接続されている他の半導体装置に誤動作を起こさせる
のを皆無とした半導体素子収納用パッケージを提供する
ことにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above drawbacks, and it is an object of the present invention to effectively propagate noise generated by a semiconductor element housed inside to an external electric circuit through a metallized wiring layer. Another object of the present invention is to provide a package for housing a semiconductor element, which prevents the noise and causes no malfunction of other semiconductor devices connected to an external electric circuit.
【０００８】[0008]
【発明が解決しようとする課題】本発明は半導体素子の
各電極を外部電気回路に接続する複数個のメタライズ配
線層を有する絶縁基体と蓋体とから成り、内部に半導体
素子を収容するための空所を有する半導体素子収納用パ
ッケージであって、前記メタライズ配線層に抵抗値が50
Ω以下の抵抗体を直列に接続させ、且つ絶縁基体内に接
地用メタライズ金属層を配設するとともに該メタライズ
金属層と前記メタライズ配線層との間に1.0pF 以上の静
電容量を形成させたことを特徴とするものである。SUMMARY OF THE INVENTION The present invention comprises an insulating substrate having a plurality of metallized wiring layers for connecting each electrode of a semiconductor element to an external electric circuit, and a lid body for accommodating the semiconductor element therein. A package for accommodating a semiconductor device having a void, wherein the metallized wiring layer has a resistance value of 50
Resistors of Ω or less were connected in series, a metallization metal layer for grounding was arranged in the insulating substrate, and a capacitance of 1.0 pF or more was formed between the metallization metal layer and the metallization wiring layer. It is characterized by that.
【０００９】[0009]
【作用】本発明の半導体素子収納用パッケージによれ
ば、半導体素子の各電極が接続されるメタライズ配線層
に抵抗値が50Ω以下の抵抗体を直列に接続し、且つ絶縁
基体内に接地用メタライズ金属層を配設するとともに該
メタライズ金属層と前記メタライズ配線層との間に1.0p
F 以上の静電容量を形成させたことから半導体素子が駆
動時に発生したノイズのメタライズ配線層の伝播は抵抗
体で減衰を受けるとともに静電容量によって完全に遮断
され、その結果、ノイズが外部電気回路に伝播され、該
外部電気回路に接続されている他の半導体装置に入り込
むことは皆無となる。According to the package for accommodating a semiconductor element of the present invention, a resistor having a resistance value of 50Ω or less is connected in series to a metallized wiring layer to which each electrode of the semiconductor element is connected, and a metallization for grounding is provided in an insulating substrate. A metal layer is provided and 1.0 p is provided between the metallized metal layer and the metallized wiring layer.
Since the electrostatic capacitance of F or more is formed, the propagation of noise generated when the semiconductor element is driven in the metallized wiring layer is attenuated by the resistor and completely blocked by the electrostatic capacitance. There is no possibility of being propagated to a circuit and entering another semiconductor device connected to the external electric circuit.
【００１０】[0010]
【実施例】次に本発明を添付図面に基づき詳細に説明す
る。図１及び図２は本発明の半導体素子収納用パッケー
ジの一実施例を示し、1 は電気絶縁材料から成る絶縁基
体であり、2 は同じく電気絶縁材料から成る蓋体であ
る。この絶縁基体1 と蓋体2 とで半導体素子4 を収容す
るための容器3 が構成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to the accompanying drawings. 1 and 2 show an embodiment of a package for accommodating a semiconductor element of the present invention, 1 is an insulating base made of an electrically insulating material, and 2 is a lid made of the same electrically insulating material. The insulating base 1 and the lid 2 form a container 3 for housing the semiconductor element 4.
【００１１】前記絶縁基体1 はその上面中央部に半導体
素子4 を収容するための空所を形成する凹部1aが設けて
あり、該凹部1a底面には半導体素子4 が樹脂、ガラス、
ロウ材等の接着剤を介して載置固定される。The insulating substrate 1 is provided with a recess 1a in the center of the upper surface thereof which forms a space for accommodating the semiconductor element 4, and the semiconductor element 4 is provided on the bottom surface of the recess 1a with resin, glass,
It is placed and fixed via an adhesive such as a brazing material.
【００１２】前記絶縁基体1 は例えば、アルミナセラミ
ックス等から成り、アルミナ(Al 2O 3 ) シリカ(SiO2 )
、カルシア(CaO) 、マグネシア(MgO) 等の原料粉末に
適当な有機溶剤、溶媒を添加混合して泥漿状となすとと
もにこれを従来周知のドクターブレード法やカレンダー
ロール法を採用することによってセラミックグリーンシ
ート( セラミック生シート) を形成し、しかる後、前記
セラミックグリーンシートに適当な打ち抜き加工を施す
とともに複数枚積層し、高温( 約1600℃) で焼成するこ
とによって製作される。The insulating substrate 1 is made of, for example, alumina ceramics, and is made of alumina (Al 2 O 3 ) silica (SiO 2 ).
, Calcia (CaO), magnesia (MgO), etc. are mixed by adding an appropriate organic solvent and solvent to form a sludge, and by applying the well-known doctor blade method and calender roll method to ceramic green A sheet (ceramic green sheet) is formed, and thereafter, the ceramic green sheet is appropriately punched, laminated with a plurality of sheets, and fired at a high temperature (about 1600 ° C.).
【００１３】また前記絶縁基体1 には凹部1aの周辺から
容器3 の外部に導出する複数個のメタライズ配線層5 が
形成されており、該メタライズ配線層5 の凹部1a周辺部
には半導体素子4 の各電極がボンディングワイヤ6 を介
して電気的に接続され、また容器3 の外部に導出された
部位には外部電気回路と接続される外部リード端子7が
銀ロウ等のロウ材を介し取着されている。A plurality of metallized wiring layers 5 extending from the periphery of the recess 1a to the outside of the container 3 are formed on the insulating base 1, and the semiconductor element 4 is formed around the recess 1a of the metallized wiring layer 5. Each of the electrodes is electrically connected via a bonding wire 6, and an external lead terminal 7 connected to an external electric circuit is attached to a portion led out of the container 3 via a brazing material such as silver solder. Has been done.
【００１４】前記メタライズ配線層5 はタングステン
(W) 、モリブデン(Mo)、マンガン(Mn)等の高融点金属粉
末から成り、該高融点金属粉末に適当な有機溶剤、溶媒
を添加混合して得た金属ペーストを従来周知のスクリー
ン印刷法等の厚膜手法を採用し、絶縁基体1 となるセラ
ミックグリーンシートに予め被着させておくことによっ
て絶縁基体1 の凹部1a周辺から容器3 の外部に導出する
ように被着形成される。The metallized wiring layer 5 is made of tungsten.
(W), molybdenum (Mo), manganese (Mn) and other high-melting point metal powder, a suitable organic solvent to the high-melting point metal powder, a metal paste obtained by adding and mixing a solvent is a conventionally known screen printing method. A thick film method such as the above is adopted, and the ceramic green sheet to be the insulating substrate 1 is pre-deposited, so that it is formed so as to be led out from the periphery of the recess 1a of the insulating substrate 1 to the outside of the container 3.
【００１５】尚、前記メタライズ配線層5 はその露出す
る外表面にニッケル、金等の良導電性で、且つ耐蝕性に
優れた金属をメッキ法により1.0 乃至20.0μm の厚みに
層着させておくと、メタライズ配線層5 の酸化腐食を有
効に防止することができるとともにメタライズ配線層5
とボンディングワイヤ6 との接続及びメタライズ配線層
5 と外部リード端子7 とのロウ付け取着が極めて強固な
ものとなる。従って、前記メタライズ配線層5 の酸化腐
食を防止し、メタライズ配線層5 とボンディングワイヤ
6 との接続及びメタライズ配線層5 と外部リード端子7
とのロウ付けを強固なものとなすにはメタライズ配線層
5 の露出外表面にニッケル、金等を1.0乃至20.0μm の
厚みに層着させておくことが好ましい。The metallized wiring layer 5 is formed by depositing a metal such as nickel or gold, which has good conductivity and corrosion resistance, on the exposed outer surface to a thickness of 1.0 to 20.0 μm by a plating method. The metallized wiring layer 5 can be effectively prevented from being oxidized and corroded.
And bonding wire 6 and metallized wiring layer
The brazing attachment of 5 and the external lead terminal 7 becomes extremely strong. Therefore, the metallized wiring layer 5 and the bonding wire are prevented from being oxidized and corroded.
6 and metallized wiring layer 5 and external lead terminals 7
Metallized wiring layer for strong brazing with
It is preferable to deposit nickel, gold or the like on the exposed outer surface of layer 5 to a thickness of 1.0 to 20.0 μm.
【００１６】また前記メタライズ配線層5 にロウ付けさ
れる外部リード端子7 は内部に収容する半導体素子4 を
外部電気回路に接続する作用を為し、外部リード端子7
を外部電気回路に接続させることによって内部に収容さ
れる半導体素子4 はメタライズ配線層5 及び外部リード
端子7 を介して外部電気回路と電気的に接続されること
となる。The external lead terminals 7 brazed to the metallized wiring layer 5 serve to connect the semiconductor element 4 housed therein to an external electric circuit,
When the semiconductor element 4 is connected to an external electric circuit, the semiconductor element 4 housed inside is electrically connected to the external electric circuit via the metallized wiring layer 5 and the external lead terminal 7.
【００１７】前記外部リード端子7 はコバール金属(Fe-
Ni-Co 合金) や４２アロイ(Fe-Ni合金) 等の金属から成
り、コバール金属等のインゴット( 塊) を圧延加工法や
打ち抜き加工法等、従来周知の金属加工を施すことによ
って所定の板状に形成される。The external lead terminal 7 is made of Kovar metal (Fe-
Ni-Co alloy) or 42 alloy (Fe-Ni alloy) and other metals. Ingots (lumps) of Kovar metal etc. are subjected to well-known metal working such as rolling and punching, and then a predetermined plate Formed into a shape.
【００１８】尚、前記外部リード端子7 はその外表面に
ニッケル、金等の良導電性で、且つ耐蝕性に優れた金属
をメッキ法により1.0 乃至20.0μm の厚みに層着させて
おくと、外部リード端子7 の酸化腐食を有効に防止する
とともに外部リード端子7 と外部電気回路との電気的接
続を良好なものとなすことができる。従って、前記外部
リード端子7 はその外表面にニッケル、金等を1.0 乃至
20.0μm の厚みに層着させておくことが好ましい。It should be noted that the external lead terminal 7 is formed by depositing a metal such as nickel or gold, which has good conductivity and corrosion resistance, on the outer surface of the external lead terminal 7 by plating to a thickness of 1.0 to 20.0 μm. Oxidation and corrosion of the external lead terminals 7 can be effectively prevented, and the electrical connection between the external lead terminals 7 and the external electric circuit can be improved. Therefore, the external lead terminals 7 should be coated with nickel, gold, etc. at 1.0 to
It is preferable to layer them to a thickness of 20.0 μm.
【００１９】また前記半導体素子4 の各電極が接続さ
れ、一端に外部リード端子7 がロウ付けされているメタ
ライズ配線層5 はその一部に抵抗値を50Ω以下とした抵
抗体8が直列に接続されており、該抵抗体8 はメタライ
ズ配線層5 を伝播する半導体素子4 が作動時に発したノ
イズを減衰させる作用を為す。この場合、前記抵抗体8
はメタライズ配線層5 を伝播する電気信号を同時に減衰
させるものの抵抗体8 の抵抗値は50Ω以下であるためメ
タライズ配線層5 を伝播する電気信号は前記抵抗体8 で
大きく減衰することはなく、その結果、半導体素子4 に
出し入れされる電気信号を大きなものとして半導体素子
4 を正常、且つ安定に作動させることができる。The metallized wiring layer 5 to which each electrode of the semiconductor element 4 is connected and the external lead terminal 7 is brazed at one end is connected in series with a resistor 8 having a resistance value of 50Ω or less. The resistor 8 has a function of attenuating noise generated during operation of the semiconductor element 4 propagating through the metallized wiring layer 5. In this case, the resistor 8
Although the electrical signal propagating through the metallized wiring layer 5 is attenuated at the same time, the resistance value of the resistor 8 is 50 Ω or less, so the electrical signal propagating through the metallized wiring layer 5 is not significantly attenuated by the resistor 8, and As a result, the electric signal input to and output from the semiconductor element 4 is regarded as a large one, and
4 can be operated normally and stably.
【００２０】尚、前記抵抗体8 はその抵抗値が50Ωを越
えるとメタライズ配線層5 を伝播する電気信号を減衰さ
せ、半導体素子4 に出し入れされる電気信号を小さなも
のとして半導体素子4 を正常、且つ安定に作動させるこ
とができなくなる。従って、前記抵抗体8 はその抵抗値
を50Ω以下としたものに特定される。When the resistance value of the resistor 8 exceeds 50 Ω, the electric signal propagating in the metallized wiring layer 5 is attenuated, and the electric signal which is taken in and out of the semiconductor element 4 is made small so that the semiconductor element 4 is normally operated. And it becomes impossible to operate stably. Therefore, the resistor 8 is specified to have a resistance value of 50Ω or less.
【００２１】また前記メタライズ配線層5 に直列に接続
される抵抗体8 は例えば、タングステンーレニウム粉末
から成り、該タングステンーレニウム粉末に適当な有機
溶剤、溶媒を添加混合して得た抵抗ペーストを従来周知
のスクリーン印刷法等の厚膜手法を採用し、絶縁基体1
となるセラミックグリーンシートにメタライズ配線層5
となる金属ペーストを印刷塗布する際に同時に印刷塗布
しておくことによってメタライズ配線層5 の一部に直列
に接続される。The resistor 8 connected in series to the metallized wiring layer 5 is made of, for example, tungsten-rhenium powder, and a resistance paste obtained by adding and mixing an appropriate organic solvent and solvent to the tungsten-rhenium powder is used. The insulating base 1
Metallized wiring layer 5 on the ceramic green sheet
It is connected in series to a part of the metallized wiring layer 5 by printing and applying at the same time when the metal paste to be formed is applied by printing.
【００２２】一方、前記絶縁基体1 にはその内部に接地
用メタライズ金属層9 が配設されており、該接地用メタ
ライズ金属層9 はメタライズ配線層5 との間に1.0pF 以
上の静電容量を形成するとともにその静電容量をメタラ
イズ配線層5 に並列に接続させている。On the other hand, a grounding metallized metal layer 9 is disposed inside the insulating substrate 1, and the metallized metal layer 9 for grounding has a capacitance of 1.0 pF or more between it and the metallized wiring layer 5. And the capacitance is connected to the metallized wiring layer 5 in parallel.
【００２３】前記メタライズ配線層5 と接地用メタライ
ズ金属層9 との間に形成される静電容量はノイズがメタ
ライズ配線層5 を伝播するのを遮断する作用を為し、こ
れによって半導体素子4 が駆動時にノイズを発生し、該
ノイズがメタライズ配線層5を伝播しようとしてもその
伝播は抵抗体8 で減衰されるとともに静電容量によって
完全に遮断され、外部電気回路に出ていくことはない。The capacitance formed between the metallized wiring layer 5 and the metallized metal layer 9 for grounding functions to block noise from propagating through the metallized wiring layer 5, whereby the semiconductor element 4 is prevented. Even if noise is generated at the time of driving and the noise tries to propagate through the metallized wiring layer 5, the propagation is attenuated by the resistor 8 and completely blocked by the electrostatic capacitance, and does not go out to the external electric circuit.
【００２４】尚、前記接地用メタライズ金属層9 はタン
グステン、モリブデン、マンガン等の高融点金属粉末か
ら成り、該高融点金属粉末に適当な有機溶剤、溶媒を添
加混合して得た金属ペーストを従来周知のスクリーン印
刷法等の厚膜手法を採用し、絶縁基体1 となるセラミッ
クグリーンシートに予め印刷塗布しておくことによって
絶縁基体1 の内部に形成される。The grounding metallized metal layer 9 is made of a refractory metal powder such as tungsten, molybdenum or manganese, and a metal paste obtained by adding and mixing an appropriate organic solvent or solvent to the refractory metal powder is conventionally used. A thick film technique such as a well-known screen printing method is used, and the ceramic green sheet to be the insulating substrate 1 is printed and applied in advance to form the inside of the insulating substrate 1.
【００２５】また前記接地用メタライズ金属層9 とメタ
ライズ配線層5 との間に形成される静電容量はその値が
1.0pF 未満となるとノイズのメタライズ配線層5 におけ
る伝播を完全に遮断することができず、ノイズが外部電
気回路に出ていってしまう。The value of the capacitance formed between the metallized metal layer 9 for grounding and the metallized wiring layer 5 has a value
If it is less than 1.0 pF, it is not possible to completely block the propagation of noise in the metallized wiring layer 5, and noise is emitted to the external electric circuit.
【００２６】従って、前記接地用メタライズ金属層9 と
メタライズ配線層5 との間に形成される静電容量はその
値を1.0pF 以上としておく必要がある。Therefore, the capacitance formed between the grounding metallized metal layer 9 and the metallized wiring layer 5 must have a value of 1.0 pF or more.
【００２７】更に前記接地用メタライズ金属層9 とメタ
ライズ配線層5 との間に形成される静電容量を1.0pF 以
上とするにはメタライズ配線層5 とメタライズ金属層9
との間隔を小さいものとしたり、メタライズ配線層5 の
うち抵抗体8 が接続される領域の幅を若干広くし、メタ
ライズ配線層5 とメタライズ金属層9 の対向面積をひろ
げることによって得られる。Further, in order to make the capacitance formed between the ground metallized metal layer 9 and the metallized wiring layer 5 1.0 pF or more, the metallized wiring layer 5 and the metallized metal layer 9
This can be obtained by reducing the distance between the metallized wiring layer 5 and the metallized wiring layer 5 or by slightly widening the width of the region of the metallized wiring layer 5 to which the resistor 8 is connected.
【００２８】かくして、本発明の半導体素子収納用パッ
ケージによれば絶縁基体1 の凹部1a底面に半導体素子4
を接着剤を介して搭載固定するとともに半導体素子4 の
各電極をメタライズ配線層5 にボンディングワイヤ6 を
介して電気的に接続し、しかる後、絶縁基体1 の上面に
蓋体2 を封止材を介して接合させ、容器3 の内部に半導
体素子4 を気密に収容させることによって最終製品とし
ての半導体装置となる。Thus, according to the semiconductor element housing package of the present invention, the semiconductor element 4 is formed on the bottom surface of the recess 1a of the insulating base 1.
Is mounted and fixed via an adhesive and each electrode of the semiconductor element 4 is electrically connected to the metallized wiring layer 5 via a bonding wire 6, and then the lid 2 is attached to the upper surface of the insulating base 1 as a sealing material. A semiconductor device as a final product is obtained by joining the semiconductor element 4 and the semiconductor element 4 in an airtight manner inside the container 3 through the above.
【００２９】[0029]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、半導体素子の各電極が接続されるメタライズ配
線層に抵抗値が50Ω以下の抵抗体を直列に接続し、且つ
絶縁基体内に接地用メタライズ金属層を配設するととも
に該メタライズ金属層と前記メタライズ配線層と間に1.
0pF 以上の静電容量を形成させたことから半導体素子が
駆動時に発生したノイズのメタライズ配線層の伝播は抵
抗体で減衰を受けるとともに静電容量によって完全に遮
断され、その結果、ノイズが外部電気回路に伝播され、
該外部電気回路に接続されている他の半導体装置に入り
込んで他の半導体装置に誤動作を起こさせることは皆無
となる。According to the package for accommodating a semiconductor element of the present invention, a resistor having a resistance value of 50Ω or less is connected in series to a metallized wiring layer to which each electrode of the semiconductor element is connected, and the insulating substrate is grounded. And a metallized metal layer for the metallized metal layer between the metallized metal layer and the metallized wiring layer.
Since the electrostatic capacitance of 0 pF or more is formed, the propagation of the noise generated when the semiconductor element is driven in the metallized wiring layer is attenuated by the resistor and completely blocked by the electrostatic capacitance. Propagated to the circuit,
There is no possibility of entering another semiconductor device connected to the external electric circuit and causing the other semiconductor device to malfunction.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of a semiconductor element housing package of the present invention.
【図２】図１に示す半導体素子収納用パッケージの絶縁
基体の一部破断平面図である。FIG. 2 is a partially cutaway plan view of an insulating base of the semiconductor element housing package shown in FIG.
【図３】従来の半導体素子収納用パッケージの断面図で
ある。FIG. 3 is a cross-sectional view of a conventional semiconductor element housing package.
１・・・・・絶縁基体 ２・・・・・蓋体 ４・・・・・半導体素子 ５・・・・・メタライズ配線層 ７・・・・・外部リード端子 ８・・・・・抵抗体 ９・・・・・接地用メタライズ金属層 1 ... Insulating substrate 2 ... Lid 4 ... Semiconductor element 5 ... Metallized wiring layer 7 ... External lead terminal 8 ... Resistor 9 ... Metallized metal layer for grounding
Claims (1)
する複数個のメタライズ配線層を有する絶縁基体と蓋体
とから成り、内部に半導体素子を収容するための空所を
有する半導体素子収納用パッケージであって、前記メタ
ライズ配線層に抵抗値が50Ω以下の抵抗体を直列に接続
させ、且つ絶縁基体内に接地用メタライズ金属層を配設
するとともに該メタライズ金属層と前記メタライズ配線
層との間に1.0 pF以上の静電容量を形成させたことを特
徴とする半導体素子収納用パッケージ。1. A semiconductor element housing comprising an insulating substrate having a plurality of metallized wiring layers for connecting respective electrodes of the semiconductor element to an external electric circuit and a lid, and having a space for housing the semiconductor element therein. And a metallization wiring layer in which a resistor having a resistance value of 50Ω or less is connected in series, and a metallization metal layer for grounding is disposed in an insulating substrate, and the metallization metal layer and the metallization wiring layer. A package for storing semiconductor devices, characterized in that a capacitance of 1.0 pF or more is formed between them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4128613A JP2738622B2 (en) | 1992-05-21 | 1992-05-21 | Package for storing semiconductor elements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4128613A JP2738622B2 (en) | 1992-05-21 | 1992-05-21 | Package for storing semiconductor elements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05326740A true JPH05326740A (en) | 1993-12-10 |
| JP2738622B2 JP2738622B2 (en) | 1998-04-08 |
Family
ID=14989120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4128613A Expired - Fee Related JP2738622B2 (en) | 1992-05-21 | 1992-05-21 | Package for storing semiconductor elements |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2738622B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3136187A1 (en) * | 1981-09-12 | 1983-04-28 | Kernforschungszentrum Karlsruhe Gmbh, 7500 Karlsruhe | METHOD AND DEVICE FOR CLEANING THE INTERNAL WALL OF METAL PIPING SYSTEMS BY ELECTROPOLISHING WITH ELECTRODES MOVED |
| US5668033A (en) * | 1995-05-18 | 1997-09-16 | Nippondenso Co., Ltd. | Method for manufacturing a semiconductor acceleration sensor device |
| US7449773B2 (en) | 2003-05-22 | 2008-11-11 | Texas Instruments Incorporated | Microelectromechanical device packages with integral heaters |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01214051A (en) * | 1988-02-22 | 1989-08-28 | Sumitomo Electric Ind Ltd | Package for integrated circuit |
-
1992
- 1992-05-21 JP JP4128613A patent/JP2738622B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01214051A (en) * | 1988-02-22 | 1989-08-28 | Sumitomo Electric Ind Ltd | Package for integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3136187A1 (en) * | 1981-09-12 | 1983-04-28 | Kernforschungszentrum Karlsruhe Gmbh, 7500 Karlsruhe | METHOD AND DEVICE FOR CLEANING THE INTERNAL WALL OF METAL PIPING SYSTEMS BY ELECTROPOLISHING WITH ELECTRODES MOVED |
| US5668033A (en) * | 1995-05-18 | 1997-09-16 | Nippondenso Co., Ltd. | Method for manufacturing a semiconductor acceleration sensor device |
| US7449773B2 (en) | 2003-05-22 | 2008-11-11 | Texas Instruments Incorporated | Microelectromechanical device packages with integral heaters |
| US7872338B2 (en) | 2003-05-22 | 2011-01-18 | Texas Instruments Incorporated | Microelectromechanical device packages with integral heaters |
| US9056764B2 (en) | 2003-05-22 | 2015-06-16 | Texas Instruments Incorporated | Microelectromechanical device packages with integral heaters |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2738622B2 (en) | 1998-04-08 |
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| LAPS | Cancellation because of no payment of annual fees |