JP2000183208A - Package for housing electronic component - Google Patents

Package for housing electronic component

Info

Publication number
JP2000183208A
JP2000183208A JP10351906A JP35190698A JP2000183208A JP 2000183208 A JP2000183208 A JP 2000183208A JP 10351906 A JP10351906 A JP 10351906A JP 35190698 A JP35190698 A JP 35190698A JP 2000183208 A JP2000183208 A JP 2000183208A
Authority
JP
Japan
Prior art keywords
wiring layer
electronic component
ground wiring
ground
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10351906A
Other languages
Japanese (ja)
Other versions
JP3766556B2 (en
Inventor
Masanao Kabumoto
正尚 株元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP35190698A priority Critical patent/JP3766556B2/en
Publication of JP2000183208A publication Critical patent/JP2000183208A/en
Application granted granted Critical
Publication of JP3766556B2 publication Critical patent/JP3766556B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a package for housing an electronic component for reducing the adverse influence of a noise generated from a ground wiring layer connected with an electronic component housed inside, and for normally and stably operating the electronic component housed in the inside over a long term. SOLUTION: This package for housing an electronic component is constituted of a substrate 1 having a signal wiring layer 2, plural ground wiring layers 4 and 5 interposing this from the upper and lower parts, and placing part for an electronic component 6 and a cover body 7 having a recessed part for housing the electronic component 6 inside. The plural ground wiring layers 4 and 5 are constituted of the first ground wiring layer 4, with which the ground of the electronic component 6 is electrically connected and the second ground wiring layer 5 positioned outside the first ground wiring layer 4, and a metal layer 8 which is the conductive inner wall of the cover body 7 is electrically connected with the second ground wiring layer 5. Thus, the electronic component 6 can be completely sealed by the second group wiring layer 5 in a stable ground state and the metal layer 8, and there will be no adverse influence of a noise generated from the first ground wiring layer 4 on the electronic component 6 or the outside device.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は電子部品を収納する
ための電子部品収納用パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component storage package for storing electronic components.

【0002】[0002]

【従来の技術】従来の電子部品収納用パッケージは、内
部に互いに絶縁層を介して上下に配置された信号配線層
・グランド配線層・電源配線層を有し、かつ上面に電子
部品を搭載する搭載部を有する酸化アルミニウム質焼結
体等の電気絶縁材料より成る基体と、同じく酸化アルミ
ニウム質焼結体等の電気絶縁材料より成り、基体の搭載
部に搭載される半導体素子等の電子部品を収容する空所
を形成するための凹部を有する蓋体とから構成されてい
る。そして、基体の搭載部に半導体素子等の電子部品を
搭載固定するとともに、この電子部品の各端子を基体に
設けた信号配線層・グランド配線層・電源配線層にボン
ディングワイヤや半田バンプ等を介して電気的に接続
し、しかる後、基体上に蓋体を内部に電子部品を収容す
るようにして銀−エポキシ樹脂や半田等の導電性接着剤
から成る封止材により接合させる。これによって最終製
品としての電子装置が完成する。
2. Description of the Related Art A conventional package for storing electronic parts has a signal wiring layer, a ground wiring layer, and a power supply wiring layer which are disposed vertically above and below each other with an insulating layer therebetween, and mounts the electronic parts on the upper surface. A base made of an electrically insulating material such as an aluminum oxide sintered body having a mounting portion, and an electronic component such as a semiconductor element also made of an electrically insulating material such as an aluminum oxide sintered body and mounted on the mounting portion of the base. And a lid having a concave portion for forming a space for housing. Then, an electronic component such as a semiconductor element is mounted and fixed on a mounting portion of the base, and each terminal of the electronic component is connected to a signal wiring layer, a ground wiring layer, and a power supply wiring layer provided on the base via a bonding wire or a solder bump. After that, the lid is attached on the base by a sealing material made of a conductive adhesive such as silver-epoxy resin or solder so that the electronic component is housed inside. Thus, an electronic device as a final product is completed.

【0003】しかしながら、この従来の電子部品収納用
パッケージは、基体や蓋体に使用されている酸化アルミ
ニウム質焼結体はノイズに対するシールド効果が低いこ
と、および近時の半導体素子等の電子部品は高速駆動が
行なわれるようになってきておりノイズの影響を受け易
いものとなってきていること等から、外部の近接位置に
ノイズ発生源があると内部に収容する半導体素子等の電
子部品や基体に設けた信号線にノイズが極めて容易に侵
入し、その結果、侵入したノイズによって半導体素子等
の電子部品に誤動作を発生させてしまうという欠点を有
していた。
However, this conventional package for housing electronic parts has a problem that the aluminum oxide sintered body used for the base and the lid has a low shielding effect against noise, and recently, electronic parts such as semiconductor elements have not been used. Since high-speed driving has been performed and it has become susceptible to noise, etc., if there is a noise source at an external proximity position, electronic components such as semiconductor elements and substrates to be housed inside However, there is a drawback that noise enters the signal line provided in the electronic device very easily, and as a result, malfunctions occur in electronic components such as semiconductor elements due to the entered noise.

【0004】また、高速駆動を行なう電子部品はそれ自
体がノイズを発生し易く、電子部品が発生したノイズは
他の装置に入り込んで誤動作等の悪影響を与えるという
問題も有していた。
[0004] Further, there is a problem that an electronic component that performs high-speed driving is liable to generate noise by itself, and the noise generated by the electronic component enters another device to cause adverse effects such as malfunction.

【0005】そこで、このような欠点を解消するため
に、基体に形成されている信号配線層を間に絶縁層を介
してグランド配線層で挟み、かつ蓋体の凹部内壁に金属
層を被着させるとともにこの金属層を基体のグランド配
線層に電気的に接続させた電子部品収納用パッケージが
提案されている。
Therefore, in order to solve such a drawback, a signal wiring layer formed on a base is sandwiched between ground wiring layers with an insulating layer interposed therebetween, and a metal layer is formed on the inner wall of the concave portion of the lid. In addition, there has been proposed an electronic component housing package in which the metal layer is electrically connected to a ground wiring layer of a base.

【0006】このような電子部品収納用パッケージの例
を図2に示す。
FIG. 2 shows an example of such an electronic component storage package.

【0007】図2に示す電子部品収納用パッケージにお
いて、31は基体、32は信号配線層、33はグランド配線
層、34は電源配線層、35は半導体素子、36は蓋体、37は
蓋体36の内壁に形成された導電性の金属層、38は外部リ
ード端子である。41は電子部品収納用パッケージが実装
される配線基板、42は配線基板41内部の電源配線層、43
は配線基板41内部のグランド配線層であり、信号配線層
32と配線基板41の信号配線層(図示せず)およびグラン
ド配線層33と43、電源配線層34と42はそれぞれ外部リー
ド端子38を介して電気的に接続される。
In the electronic component housing package shown in FIG. 2, 31 is a base, 32 is a signal wiring layer, 33 is a ground wiring layer, 34 is a power supply wiring layer, 35 is a semiconductor element, 36 is a lid, and 37 is a lid. A conductive metal layer formed on the inner wall of 36, and 38 is an external lead terminal. 41 is a wiring board on which an electronic component storage package is mounted, 42 is a power supply wiring layer inside the wiring board 41, 43
Is a ground wiring layer inside the wiring board 41, and is a signal wiring layer.
The signal wiring layer 32 (not shown) of the wiring board 41, the ground wiring layers 33 and 43, and the power supply wiring layers 34 and 42 are electrically connected via external lead terminals 38, respectively.

【0008】基体31には、その内部および表面に信号配
線層32・グランド配線層33ならびに電源配線層34が配設
されている。そして、基体31の上面中央部は半導体素子
35や容量素子等の電子部品を搭載するための搭載部とな
っており、この搭載部には半導体素子35や容量素子等の
電子部品が搭載される。
The base 31 is provided with a signal wiring layer 32, a ground wiring layer 33, and a power supply wiring layer 34 inside and on the surface thereof. The central portion of the upper surface of the base 31 is a semiconductor element.
It is a mounting portion for mounting electronic components such as 35 and a capacitor, and electronic components such as a semiconductor device 35 and a capacitor are mounted on this mounting portion.

【0009】このパッケージでは信号配線層32は基体31
の平面方向に延びる帯状のパターンであり、グランド配
線層33は基体31の平面方向に広がり、少なくとも信号配
線層32に対向した、より広い面積のパターンである。そ
して、信号配線層32および電源配線層34をグランド配線
層33で上下から挟むことにより信号配線層32および電源
配線層34を電磁的にシールドしている。
In this package, the signal wiring layer 32 is formed of a base 31.
The ground wiring layer 33 extends in the plane direction of the base 31 and is a pattern having a larger area facing at least the signal wiring layer 32. The signal wiring layer 32 and the power wiring layer 34 are sandwiched from above and below by the ground wiring layer 33, thereby electromagnetically shielding the signal wiring layer 32 and the power wiring layer 34.

【0010】また、信号配線層32・グランド配線層33・
電源配線層34からは貫通導体(32a)・33a・34aがそ
れぞれ各層間を電気的に接続するとともに基体31上面の
搭載部に延びており、これら貫通導体(32a)・33a・
34aの搭載部に導出した部位には、半導体素子35や容量
素子等の電子部品の各電極と電気的に接続される接続用
パッドが形成されている。そして、これらの接続用パッ
ドには半導体素子35や容量素子等の電子部品の各電極が
ボンディングワイヤ39を介して接続される。
The signal wiring layer 32, the ground wiring layer 33,
From the power supply wiring layer 34, through conductors (32a), 33a, and 34a electrically connect the respective layers and extend to a mounting portion on the upper surface of the base 31, and these through conductors (32a), 33a, and 33a.
A connection pad electrically connected to each electrode of an electronic component such as the semiconductor element 35 and the capacitance element is formed in a portion led out to the mounting portion 34a. Each electrode of electronic components such as the semiconductor element 35 and the capacitor is connected to these connection pads via the bonding wire 39.

【0011】さらに、信号配線層32・グランド配線層33
および電源配線層34からは、貫通導体32a・33a・34a
がそれぞれ基体31下面にも延びており、これら貫通導体
32a・33a・34aの基体31下面に導出した部位には、外
部リード端子38が取着される端子用パッドが形成されて
いる。そして、各端子用パッドには外部リード端子38が
取着されている。
Further, the signal wiring layer 32 and the ground wiring layer 33
And from the power supply wiring layer 34, the through conductors 32a, 33a, 34a
Extend also to the lower surface of the base 31, respectively, and these through conductors
Terminal pads to which the external lead terminals 38 are attached are formed on the portions of the bases 32a, 33a, and 34a that extend to the lower surface of the base 31. An external lead terminal 38 is attached to each terminal pad.

【0012】またさらに、基体31の上面外周部の蓋体36
が接合される部位には枠状の封止用金属層が被着されて
おり、この封止用金属層とグランド配線層33とが貫通導
体33aにより電気的に接続されている。
Further, a cover 36 on the outer peripheral portion of the upper surface of the base 31 is provided.
A frame-shaped metal layer for sealing is adhered to a portion where is bonded, and the metal layer for sealing and the ground wiring layer 33 are electrically connected by the through conductor 33a.

【0013】一方、蓋体36には凹部内壁から下面にかけ
て金属層37が被着されており、この金属層37と基体31の
封止用金属層とを銀−エポキシ樹脂や半田等の導電性接
着剤から成る封止材40を介して接合することにより、蓋
体36が基体31上面に接合されるとともに導電性の内壁で
ある金属層37がグランド配線層33に電気的に接続され
る。
On the other hand, a metal layer 37 is attached to the lid 36 from the inner wall of the recess to the lower surface. The metal layer 37 and the metal layer for sealing the base 31 are formed of a conductive material such as silver-epoxy resin or solder. By joining via a sealing material 40 made of an adhesive, the lid 36 is joined to the upper surface of the base 31, and the metal layer 37, which is a conductive inner wall, is electrically connected to the ground wiring layer 33.

【0014】かかる電子部品収納用パッケージによれ
ば、基体31内部の信号配線層32を上下からグランド配線
層33で挟み、かつ蓋体36の凹部の導電性の内壁である金
属層37を基体31のグランド配線層33に電気的に接続させ
ていることから、基体31に形成した信号配線層32および
パッケージ内部に収容する半導体素子35等の電子部品は
グランド配線層33および金属層37で電磁的にシールドさ
れ、いわゆるEMI(Electro-Magnetic Interference
:電磁波妨害)シールドが施されることとなって、基
体31に形成した信号配線層32およびパッケージ内部に収
容する半導体素子35等の電子部品への外部ノイズの侵入
を有効に抑制することができる。その結果、内部に収容
する半導体素子35等の電子部品を正常かつ安定に作動さ
せることが可能となる。また同時に、内部に収容する半
導体素子35等の電子部品等が発生するノイズの外部への
漏出が有効に抑制されるので、近接して配置される他の
装置に誤動作等の悪影響を与えることもない。
According to this electronic component storage package, the signal wiring layer 32 inside the base 31 is sandwiched between the ground wiring layers 33 from above and below, and the metal layer 37 which is the conductive inner wall of the concave portion of the lid 36 is connected to the base 31. Electronic components such as the signal wiring layer 32 formed on the base 31 and the semiconductor element 35 housed inside the package are electromagnetically connected to the ground wiring layer 33 and the metal layer 37. EMI (Electro-Magnetic Interference)
(Electromagnetic wave interference) Shielding can effectively prevent external noise from entering the electronic components such as the signal wiring layer 32 formed on the base 31 and the semiconductor element 35 housed inside the package. . As a result, electronic components such as the semiconductor element 35 housed therein can be operated normally and stably. At the same time, the leakage of noise generated by electronic components such as the semiconductor element 35 housed inside to the outside is effectively suppressed, which may adversely affect other devices arranged in the vicinity such as malfunction. Absent.

【0015】[0015]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の電子部品収納用パッケージにおいては、基体
31の上下方向および蓋体36の外周側からの基体31内部へ
のノイズの侵入の防止についてはほぼ完全であるもの
の、半導体素子35の作動時のスイッチング等によって半
導体素子35のグランドに導通している基体31内部のグラ
ンド配線層33が不安定となって、このグランド配線層33
からEMIノイズが発生するという問題点があった。こ
のため、十分なEMIシールドの効果が得られず、内部
に収容する半導体素子35等の電子部品や外部に近接して
配置される他の装置に誤動作等の悪影響を与えることと
なり、これらを正常かつ安定に作動させることが困難と
なるという解決すべき課題を有していた。
However, in such a conventional package for storing electronic parts, the substrate
Although the prevention of noise from entering the inside of the base 31 from the vertical direction of the lid 31 and the outer peripheral side of the lid 36 is almost complete, it is conducted to the ground of the semiconductor element 35 by switching at the time of operation of the semiconductor element 35 or the like. The ground wiring layer 33 inside the base 31 becomes unstable, and this ground wiring layer 33
This causes a problem that EMI noise is generated. For this reason, a sufficient EMI shielding effect cannot be obtained, which adversely affects the electronic components such as the semiconductor element 35 housed therein and other devices arranged close to the outside, such as malfunctions, which may cause a malfunction. In addition, there is a problem to be solved that it is difficult to operate stably.

【0016】これに対して、この電子部品収納用パッケ
ージの全体を金属シールドで覆い、この金属シールドを
配線基板41のグランド配線層43と電気的に接続してグラ
ンドをとることによってEMI対策を施すことも考えら
れる。しかし、この場合には電子部品収納用パッケージ
の周囲に金属シールドを配置する空間が余分に必要とな
り、小型化を図ることができないという問題点があっ
た。
On the other hand, the entire electronic component housing package is covered with a metal shield, and the metal shield is electrically connected to the ground wiring layer 43 of the wiring board 41 to take a ground to take EMI measures. It is also possible. However, in this case, an extra space for disposing the metal shield around the electronic component storage package is required, and there has been a problem that the size cannot be reduced.

【0017】本発明は上記のような従来技術の問題点に
鑑みて案出されたものであり、その目的は、内部に収容
する電子部品と接続されたグランド配線層から発生する
ノイズの悪影響を抑え、内部に収容する電子部品を長期
間にわたり正常かつ安定に作動させることができる電子
部品収納用パッケージを提供することにある。
The present invention has been devised in view of the above-mentioned problems of the prior art, and has as its object to reduce the adverse effect of noise generated from a ground wiring layer connected to electronic components housed therein. It is an object of the present invention to provide an electronic component storage package that can suppress the electronic components contained therein and operate normally and stably for a long period of time.

【0018】[0018]

【課題を解決するための手段】本発明の電子部品収納用
パッケージは、内部に信号配線層およびこの信号配線層
を上下から挟む複数のグランド配線層を有するとともに
上面に電子部品を搭載するための搭載部を有する基体
と、前記搭載部に搭載される前記電子部品を内部に収容
するための凹部を有する蓋体とから成り、前記基体と前
記蓋体とを封止材を介して接合することによって内部に
前記電子部品を気密に収容するようになした電子部品収
納用パッケージであって、前記複数のグランド配線層
は、前記電子部品のグランドが電気的に接続される第1
のグランド配線層と、この第1のグランド配線層の外側
に位置する第2のグランド配線層とから成り、かつ前記
蓋体の内壁を導電性となすとともにこの内壁を前記第2
のグランド配線層に電気的に接続させたことを特徴とす
るものである。
The electronic component housing package of the present invention has a signal wiring layer and a plurality of ground wiring layers sandwiching the signal wiring layer from above and below, and mounts the electronic component on the upper surface. Consisting of a base having a mounting portion and a lid having a recess for accommodating the electronic component mounted on the mounting portion inside, and joining the base and the lid via a sealing material. An electronic component housing package for hermetically housing the electronic component therein, wherein the plurality of ground wiring layers are electrically connected to a ground of the electronic component.
And a second ground wiring layer located outside the first ground wiring layer. The inner wall of the lid is made conductive and the inner wall is formed of the second ground wiring layer.
And electrically connected to the ground wiring layer.

【0019】本発明の電子部品収納用パッケージによれ
ば、基体の信号配線層を複数のグランド配線層で挟むと
ともに、これら複数のグランド配線層を、電子部品のグ
ランドが電気的に接続される第1のグランド配線層と、
基板の内部でこの第1のグランド配線層の外側に位置す
る、第1のグランド配線層とは別個に接地された第2の
グランド配線層から成るものとし、この第2のグランド
配線層を蓋体の導電性の内壁と電気的に接続させたこと
から、電子部品の作動時にこの電子部品のグランドが電
気的に接続された第1のグランド配線層から発生するE
MIノイズが、安定したグランド状態の第2のグランド
配線層および蓋体の内壁により完全にシールドされるこ
ととなる。その結果、内部に収容する電子部品や外部に
近接して配置される他の装置に誤動作等の悪影響を与え
ることがなくなり、これらを正常かつ安定に作動させる
ことができるものとなる。
According to the electronic component storage package of the present invention, the signal wiring layer of the base is sandwiched between the plurality of ground wiring layers, and the plurality of ground wiring layers are electrically connected to the ground of the electronic component. One ground wiring layer,
A second ground wiring layer located outside the first ground wiring layer inside the substrate and grounded separately from the first ground wiring layer is provided, and the second ground wiring layer is covered with a cover. Since the electronic component is electrically connected to the conductive inner wall of the body, the ground of the electronic component is generated from the first ground wiring layer electrically connected to the electronic component when the electronic component is operated.
The MI noise is completely shielded by the stable second ground wiring layer and the inner wall of the lid. As a result, adverse effects such as malfunctions are not exerted on electronic components housed inside or other devices arranged close to the outside, and these can be normally and stably operated.

【0020】[0020]

【発明の実施の形態】次に、本発明を添付の図面に基づ
き詳細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings.

【0021】図1は本発明の電子部品収納用パッケージ
として電子部品である半導体素子を収容する半導体素子
収納用パッケージを例に示す断面図である。図1に示す
電子部品収納用パッケージにおいて、1は基体、2は信
号配線層、3は電源配線層、4は第1のグランド配線
層、5は第2のグランド配線層、6は電子部品としての
半導体素子、7は蓋体、8は蓋体7の内壁に形成された
導電性の金属層、9は外部リード端子である。
FIG. 1 is a cross-sectional view showing an example of a package for housing a semiconductor element as a package for storing an electronic component according to the present invention. In the electronic component housing package shown in FIG. 1, 1 is a base, 2 is a signal wiring layer, 3 is a power wiring layer, 4 is a first ground wiring layer, 5 is a second ground wiring layer, and 6 is an electronic component. 7 is a lid, 8 is a conductive metal layer formed on the inner wall of the lid 7, and 9 is an external lead terminal.

【0022】12は電子部品収納用パッケージが実装され
る配線基板、13は配線基板12内部の電源配線層、14は配
線基板12内部のグランド配線層である。また、信号配線
層(図示せず)が配線基板12の上面および下面に形成さ
れている。そして、信号配線層2と配線基板12の信号配
線層、電源配線層3と電源配線層13、および第1のグラ
ンド配線層4・第2のグランド配線層5とグランド配線
層14はそれぞれ外部リード端子9を介して電気的に接続
される。
Reference numeral 12 denotes a wiring board on which an electronic component storage package is mounted, 13 denotes a power supply wiring layer inside the wiring board 12, and 14 denotes a ground wiring layer inside the wiring board 12. In addition, signal wiring layers (not shown) are formed on the upper and lower surfaces of the wiring board 12. The signal wiring layer 2 and the signal wiring layer of the wiring board 12, the power wiring layer 3 and the power wiring layer 13, the first ground wiring layer 4, the second ground wiring layer 5, and the ground wiring layer 14 are connected to external leads, respectively. It is electrically connected via the terminal 9.

【0023】基体1は、概ね四角形の板状の部材であ
り、酸化アルミニウム質焼結体やムライト質焼結体・窒
化アルミニウム質焼結体・炭化珪素質焼結体・ガラスセ
ラミックス等の無機電気絶縁材料や、各種の有機電気絶
縁材料あるいは有機絶縁樹脂中に無機絶縁粉末を分散含
有させた複合電気絶縁材料で構成されている。
The base 1 is a substantially rectangular plate-like member, and is made of an inorganic electric material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, or a glass ceramic. It is composed of an insulating material, various kinds of organic electric insulating materials, or a composite electric insulating material in which an inorganic insulating powder is dispersed and contained in an organic insulating resin.

【0024】また、基体1の上面中央部には半導体素子
6や容量素子等の電子部品を搭載する搭載部が形成され
ており、この搭載部には半導体素子6が半田等を介して
取着固定される。
A mounting portion for mounting electronic components such as a semiconductor element 6 and a capacitor is formed at the center of the upper surface of the base 1, and the semiconductor element 6 is attached to this mounting portion via solder or the like. Fixed.

【0025】基体1は、例えば酸化アルミニウム質焼結
体から成る場合であれば、酸化アルミニウムおよび酸化
珪素・酸化マグネシウム・酸化カルシウム等の原料粉末
に適当な有機バインダおよび溶剤・可塑剤等を添加混合
して泥漿状となすとともに、この泥漿物をドクターブレ
ード法やカレンダーロール法等によりシート状に成形し
て複数枚のグリーンシート(生シート)を得て、しかる
後、このグリーンシートに適当な打ち抜き加工を施すと
ともに所定の順に積層してグリーンシート積層体とな
し、最後にこのグリーンシート積層体を還元雰囲気中、
約1600℃の温度で焼成することによって製作される。
When the substrate 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder, a solvent, a plasticizer and the like are added to aluminum oxide and raw material powders of silicon oxide, magnesium oxide, calcium oxide and the like. The resulting slurry is formed into a sheet by a doctor blade method, a calendar roll method, or the like to obtain a plurality of green sheets (raw sheets). Processed and laminated in a predetermined order to form a green sheet laminate, and finally this green sheet laminate in a reducing atmosphere,
It is manufactured by firing at a temperature of about 1600 ° C.

【0026】基体1はまた、その内部および上下面に信
号配線層2・電源配線層3・第1のグランド配線層4・
第2のグランド配線層5が配設されている。これらの信
号配線層2・電源配線層3・第1のグランド配線層4・
第2のグランド配線層5は、半導体素子6の各電極(信
号電極・グランド電極・電源電極)を配線基板12の信号
配線層(図示せず)・電源配線層13・グランド配線層14
等の外部電気回路に接続するための導電路として機能す
る。
The base 1 also has a signal wiring layer 2, a power supply wiring layer 3, a first ground wiring layer 4,
A second ground wiring layer 5 is provided. These signal wiring layer 2, power supply wiring layer 3, first ground wiring layer 4,
The second ground wiring layer 5 connects each electrode (signal electrode, ground electrode, power supply electrode) of the semiconductor element 6 to a signal wiring layer (not shown) of the wiring board 12, a power supply wiring layer 13, and a ground wiring layer 14.
Etc. function as a conductive path for connection to an external electric circuit.

【0027】信号配線層2は基体1の平面方向に延びる
細い帯状のパターンである。第1のグランド配線層4・
第2のグランド配線層5および電源配線層3は基体1の
平面方向に広がる広面積のパターンである。第1のグラ
ンド配線層4は少なくとも信号配線層2に対向してそれ
より広い面積を有しており、パッケージに収容される半
導体素子6のグランドが電気的に接続される。また、第
2のグランド配線層5は基体1内で第1のグランド配線
層4の外側に位置して第1のグランド配線層4と対向
し、それより広い面積を有しており、第1のグランド配
線層4とは別に外部電気回路のグランドと電気的に接続
されるとともに、蓋体7の導電性の内壁である金属層8
と電気的に接続されている。
The signal wiring layer 2 is a thin band-shaped pattern extending in the plane direction of the base 1. First ground wiring layer 4
The second ground wiring layer 5 and the power supply wiring layer 3 are wide-area patterns extending in the plane direction of the base 1. The first ground wiring layer 4 has at least a larger area facing the signal wiring layer 2 and is electrically connected to the ground of the semiconductor element 6 housed in the package. Further, the second ground wiring layer 5 is located outside the first ground wiring layer 4 in the base 1 and faces the first ground wiring layer 4 and has a larger area than the first ground wiring layer 4. Is electrically connected to the ground of an external electric circuit separately from the ground wiring layer 4 and the metal layer 8 which is a conductive inner wall of the lid 7.
Is electrically connected to

【0028】そして、信号配線層2は第1のグランド配
線層4および第2のグランド配線層5で上下から挟まれ
ているとともに、第1のグランド配線層4は第2のグラ
ンド配線層5で上下から挟まれており、これにより信号
配線層2と第1のグランド配線層4ならびに半導体素子
6がそれぞれ電磁的にシールドされている。
The signal wiring layer 2 is sandwiched between the first ground wiring layer 4 and the second ground wiring layer 5 from above and below, and the first ground wiring layer 4 is sandwiched by the second ground wiring layer 5. The signal wiring layer 2, the first ground wiring layer 4, and the semiconductor element 6 are electromagnetically shielded from each other.

【0029】そのため、信号配線層2に上下からノイズ
が入り込もうとしてもそのノイズは上下のグランド配線
層4・5で遮断され、信号配線層2にノイズが入り込ん
で半導体素子6を誤動作させることはない。
Therefore, even if noise enters the signal wiring layer 2 from above and below, the noise is cut off by the upper and lower ground wiring layers 4 and 5, and it is possible that the noise enters the signal wiring layer 2 and causes the semiconductor element 6 to malfunction. Absent.

【0030】さらに、半導体素子6の作動時にそのグラ
ンドが電気的に接続された第1のグランド配線層4が不
安定となってノイズが発生したとしても、このノイズは
第1のグランド配線層4の外側に位置する安定したグラ
ンド状態の第2のグランド配線層5によってシールドさ
れるため、このノイズが半導体素子6自身や外部に近接
して配置される他の装置に誤動作等の悪影響を与えるこ
とがない。
Further, even if the first ground wiring layer 4 to which the ground is electrically connected becomes unstable when the semiconductor element 6 operates and noise occurs, the noise is generated by the first ground wiring layer 4. Is shielded by the second ground wiring layer 5 in a stable ground state located outside the semiconductor device 6, so that this noise may adversely affect the semiconductor element 6 itself or other devices arranged close to the outside such as malfunction. There is no.

【0031】信号配線層2・電源配線層3・第1のグラ
ンド配線層4・第2のグランド配線層5からはそれぞれ
貫通導体2a・3a・4a・5aがパッケージの仕様に
応じて各層間ならびに基体1の上面および下面等に延び
ている。この貫通導体2a・3a・4aの基体1上面に
導出した部分には、半導体素子6や容量素子等の電子部
品の各電極と電気的に接続される接続用パッドが形成さ
れている。
From the signal wiring layer 2, the power supply wiring layer 3, the first ground wiring layer 4, and the second ground wiring layer 5, through conductors 2a, 3a, 4a, and 5a are formed in respective layers according to the specification of the package. It extends to the upper surface, the lower surface, etc. of the base 1. At the portions of the through conductors 2a, 3a, and 4a extending to the upper surface of the base 1, connection pads that are electrically connected to electrodes of electronic components such as the semiconductor element 6 and the capacitance element are formed.

【0032】そして、これらの接続パッドには半導体素
子6の各電極(信号電極・グランド電極・電源電極)や
容量素子等の各電極(グランド電極・電源電極)がボン
ディングワイヤ10等を介して接続される。なお、ボンデ
ィングワイヤ10に代えて半田バンプ等を用い、いわゆる
フリップチップ実装構造としてもよい。
Each electrode (signal electrode, ground electrode, power supply electrode) of the semiconductor element 6 and each electrode (ground electrode / power supply electrode) of the capacitance element and the like are connected to these connection pads via bonding wires 10 and the like. Is done. Note that a so-called flip-chip mounting structure may be used instead of the bonding wire 10 using a solder bump or the like.

【0033】ここで半導体素子6とともに搭載部に搭載
される容量素子は、第1のグランド配線層4および電源
配線層3を介して半導体素子6と電気的に接続され、グ
ランド電位や電源電位が過渡的に変動した場合にこの容
量素子から半導体素子6に電荷を供給することにより、
これらの電位の変動による半導体素子6の誤動作を防止
するためのものである。
Here, the capacitive element mounted on the mounting portion together with the semiconductor element 6 is electrically connected to the semiconductor element 6 via the first ground wiring layer 4 and the power supply wiring layer 3, and the ground potential and the power supply potential are changed. By supplying a charge to the semiconductor element 6 from this capacitance element when it fluctuates transiently,
This is to prevent a malfunction of the semiconductor element 6 due to these potential fluctuations.

【0034】さらに、信号配線層2・電源配線層3・第
1のグランド配線層4・第2のグランド配線層5から
は、それぞれ貫通導体2a・3a・4a・5aがそれぞ
れ基体1下面に延びており、これら貫通導体2a・3a
・4a・5aで基体1下面に導出した部位には、外部リ
ード端子9が取着された端子用パッドが形成されてい
る。
Further, through conductors 2a, 3a, 4a, and 5a extend from the signal wiring layer 2, the power wiring layer 3, the first ground wiring layer 4, and the second ground wiring layer 5 to the lower surface of the base 1, respectively. And these through conductors 2a and 3a
A terminal pad to which the external lead terminal 9 is attached is formed at a portion led out to the lower surface of the base 1 at 4a and 5a.

【0035】なお、外部リード端子9に代えて例えば半
田ボール等のバンプ電極として、この電子部品収納用パ
ッケージを配線基板12にいわゆるフリップチップ実装し
てもよい。
It is to be noted that the electronic component housing package may be mounted on the wiring board 12 in a so-called flip-chip manner as a bump electrode such as a solder ball instead of the external lead terminal 9.

【0036】また、第2のグランド配線層5から基体1
上面の外周部に導出された貫通導体5aには、基体1に
蓋体7を接合するための封止用金属層が形成され、この
封止用金属層には蓋体7が導電性接着剤等から成る封止
材11を介して接合される。これにより、蓋体7の凹部内
壁から下面にかけて被着された金属層8が第2のグラン
ド配線層5に電気的に接続される。
The second ground wiring layer 5 to the base 1
A sealing metal layer for joining the lid 7 to the base 1 is formed on the through conductor 5a led out to the outer peripheral portion of the upper surface, and the lid 7 is formed of a conductive adhesive on the sealing metal layer. It is joined via a sealing material 11 made of the same. As a result, the metal layer 8 applied from the inner wall to the lower surface of the concave portion of the lid 7 is electrically connected to the second ground wiring layer 5.

【0037】信号配線層2・電源配線層3・第1のグラ
ンド配線層4・第2のグランド配線層5は、例えばタン
グステンやモリブデン・銅・銀・金等の金属粉末メタラ
イズ等によって形成されている。これらは、例えばタン
グステン等の金属粉末に適当な有機溶剤・溶媒を添加混
合して得た金属ペーストを基体1となるグリーンシート
の表面ならびにグリーンシート積層体の側面に従来周知
のスクリーン印刷法等の厚膜手法を採用して印刷塗布し
ておくことによって、基体1の内部および上下面ならび
に側面に被着形成される。
The signal wiring layer 2, power supply wiring layer 3, first ground wiring layer 4, and second ground wiring layer 5 are formed by, for example, metal powder metalization of tungsten, molybdenum, copper, silver, gold, or the like. I have. For example, a metal paste obtained by adding a suitable organic solvent and a solvent to a metal powder such as tungsten is mixed on a surface of a green sheet as a substrate 1 and a side surface of a green sheet laminate by a conventionally known screen printing method or the like. By printing and applying the thick film method, the substrate 1 is adhered and formed on the inside, the upper and lower surfaces, and the side surfaces.

【0038】さらに基体1は、その上面に蓋体7が銀−
エポキシ樹脂等の導電性接着剤から成る封止材11を介し
て接合され、これによって基体1と蓋体7とから成る容
器内部に半導体素子6等の電子部品が気密に封止され
る。
Further, the base 1 has a cover 7 on its upper surface formed of silver-based material.
The electronic components such as the semiconductor element 6 are hermetically sealed in a container formed by the base 1 and the lid 7 through a sealing material 11 made of a conductive adhesive such as an epoxy resin.

【0039】蓋体7は、例えば酸化アルミニウム質焼結
体やムライト質焼結体・窒化アルミニウム質焼結体・炭
化珪素質焼結体・ガラスセラミックス焼結体等の電気絶
縁材料から成り、その下面中央部に半導体素子6を内部
に収容する空所を形成するための凹部が形成された椀状
となっている。
The lid 7 is made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, an aluminum nitride sintered body, a silicon carbide sintered body, a glass ceramic sintered body, etc. It has a bowl shape in which a concave portion for forming a space for accommodating the semiconductor element 6 therein is formed in the center of the lower surface.

【0040】蓋体7は、例えば酸化アルミニウム質焼結
体から成る場合であれば、酸化アルミニウムおよび酸化
珪素・酸化マグネシウム・酸化カルシウム等の原料粉末
に適当な有機バインダおよび溶剤等を添加混合して得た
原料粉末を所定形状のプレス金型内に充填するとともに
一定圧力を印加して形成し、しかる後、この形成品を約
1500℃の温度で焼成することによって製作される。
If the lid 7 is made of, for example, an aluminum oxide sintered body, a suitable organic binder and a solvent are added to aluminum oxide and raw material powder such as silicon oxide, magnesium oxide and calcium oxide. The obtained raw material powder is filled into a press die of a predetermined shape and is formed by applying a constant pressure.
It is manufactured by firing at a temperature of 1500 ° C.

【0041】蓋体7はまた、その凹部の内壁から基体1
との接合面にかけて銀−パラジウム等の金属から成る金
属層8が形成されており、この金属層8は基体1の上面
外周部に被着された封止用金属層に銀−エポキシ樹脂等
の導電性接着剤から成る封止材11を介して電気的に接続
されている。この場合、内部に収容される半導体素子6
は、基体1に設けた第1のグランド配線層4および第2
のグランド配線層5とこの第2のグランド配線層5に電
気的に接続する蓋体7の金属層8とで完全にシールドさ
れ、外部ノイズが蓋体7を介して入り込むことはなく、
内部に収容する半導体素子6を正常かつ安定に作動させ
ることが可能となる。同時に、内部に収容する半導体素
子6が発生するノイズが蓋体7を介して外部に漏れるこ
ともなくなり、外部の装置に悪影響を与えることもな
い。
The lid 7 is also provided on the base 1 from the inner wall of the recess.
A metal layer 8 made of a metal such as silver-palladium is formed on the bonding surface of the base 1, and the metal layer 8 is formed on a sealing metal layer adhered to the outer peripheral portion of the upper surface of the base 1 by a silver-epoxy resin or the like. They are electrically connected via a sealing material 11 made of a conductive adhesive. In this case, the semiconductor element 6 housed inside
Are the first ground wiring layer 4 provided on the base 1 and the second ground wiring layer 4.
Is completely shielded by the ground wiring layer 5 and the metal layer 8 of the lid 7 electrically connected to the second ground wiring layer 5, so that external noise does not enter through the lid 7,
The semiconductor element 6 housed therein can be operated normally and stably. At the same time, noise generated by the semiconductor element 6 housed therein does not leak to the outside through the lid 7 and does not adversely affect external devices.

【0042】金属層8は、銀粉末およびパラジウム粉末
に適当な有機バインダおよび溶剤を添加混合することに
よって得た金属ペーストを蓋体7の凹部の内壁および基
体1との接合面に従来周知のスクリーン印刷法により塗
布させ、しかる後、これを900 ℃の温度で焼き付けるこ
とによって蓋体7の凹部の内壁および基体1との接合面
に被着される。
The metal layer 8 is formed by adding a metal paste obtained by adding and mixing an appropriate organic binder and a solvent to silver powder and palladium powder on the inner wall of the concave portion of the lid 7 and the joint surface with the substrate 1 by a well-known screen. It is applied by a printing method, and thereafter, it is baked at a temperature of 900 ° C. to be attached to the inner wall of the concave portion of the lid 7 and the joint surface with the base 1.

【0043】なお、蓋体7は全体を金属等の導電性材料
で構成することによってその内壁を導電性としてもよ
く、この場合にも同様に密封容器の蓋体であって電磁波
シールドとして機能させることができる。このような蓋
体7用の金属材料としては、鉄−ニッケル合金や鉄−ニ
ッケル−コバルト合金等を用いればよい。
The lid 7 may be made entirely of a conductive material such as metal to make the inner wall conductive. In this case, the lid 7 is also a lid of a sealed container and functions as an electromagnetic wave shield. be able to. As such a metal material for the lid 7, an iron-nickel alloy, an iron-nickel-cobalt alloy, or the like may be used.

【0044】かくして上述の電子部品収納用パッケージ
によれば、基体1の搭載部に半導体素子6等の電子部品
を取着搭載した後、半導体素子6等の電子部品の各電極
を基体1に形成した信号配線層2・電源配線層3・第1
のグランド配線層4にボンディングワイヤ10を介して電
気的に接続し、最後に基体1の上面に蓋体7を、この蓋
体7の凹部の導電性の内壁である金属層8が基体1の上
面外周部に第2のグランド配線層5と電気的に接続して
形成された封止用金属層と電気的に接続するようにして
銀−エポキシ樹脂等の導電性接着剤から成る封止材11を
介して接合させ、基体1と蓋体7とから成る容器内部に
半導体素子6を気密に封止することによって、最終製品
としての半導体装置となる。
Thus, according to the above-mentioned electronic component storage package, after mounting the electronic component such as the semiconductor element 6 on the mounting portion of the base 1, each electrode of the electronic component such as the semiconductor element 6 is formed on the base 1. Signal wiring layer 2, power supply wiring layer 3, first
Is electrically connected to the ground wiring layer 4 via a bonding wire 10. Finally, a lid 7 is provided on the upper surface of the base 1, and a metal layer 8 which is a conductive inner wall of a concave portion of the lid 7 is provided on the base 1. A sealing material made of a conductive adhesive such as silver-epoxy resin so as to be electrically connected to a sealing metal layer formed by being electrically connected to the second ground wiring layer 5 on the outer peripheral portion of the upper surface. Then, the semiconductor device 6 is hermetically sealed in a container formed of the base 1 and the lid 7 so as to obtain a semiconductor device as a final product.

【0045】なお、本発明は上述の実施の形態の一例に
限定されるものではなく、本発明の要旨を逸脱しない範
囲であれば種々の変更は可能である。例えば、上述の例
では蓋体7に被着させた金属層8を銀−パラジウムの金
属粉末で形成したが、これをタングステンやモリブデン
等の他の金属粉末で形成してもよい。
Note that the present invention is not limited to the above-described embodiment, and various changes can be made without departing from the scope of the present invention. For example, in the above-described example, the metal layer 8 attached to the lid 7 is formed of a silver-palladium metal powder, but may be formed of another metal powder such as tungsten or molybdenum.

【0046】さらに、上述の例では半導体素子収納用パ
ッケージを例にとって説明したが、本発明の電子部品収
納用パッケージは水晶振動子やSAWフィルタ等の他の
種類の電子部品を収容するパッケージにも適用可能であ
る。
Further, in the above-described example, the package for housing a semiconductor element has been described as an example. However, the package for housing an electronic component of the present invention can be applied to a package for housing other types of electronic components such as a crystal unit and a SAW filter. Applicable.

【0047】[0047]

【発明の効果】本発明の電子部品収納用パッケージによ
れば、基体の信号配線層を基体の信号配線層を複数のグ
ランド配線層で挟むとともに、これら複数のグランド配
線層を、電子部品のグランドが電気的に接続される第1
のグランド配線層と、基板の内部でこの第1のグランド
配線層の外側に位置する、第1のグランド配線層とは別
個に接地された第2のグランド配線層から成るものと
し、この第2のグランド配線層を蓋体の導電性の内壁と
電気的に接続させたことから、電子部品の作動時にこの
電子部品のグランドが電気的に接続された第1のグラン
ド配線層から発生するEMIノイズが、安定したグラン
ド状態の第2のグランド配線層および蓋体の内壁により
完全にシールドされることとなる。その結果、内部に収
容する電子部品や外部に近接して配置される他の装置に
誤動作等の悪影響を与えることがなくなり、これらを正
常かつ安定に作動させることができるものとなる。
According to the electronic component storage package of the present invention, the signal wiring layer of the base is sandwiched between the signal wiring layers of the base by a plurality of ground wiring layers, and the plurality of ground wiring layers are connected to the ground of the electronic component. Is electrically connected to the first
And a second ground wiring layer located inside the substrate and outside the first ground wiring layer and grounded separately from the first ground wiring layer. EMI noise generated from the first ground wiring layer to which the ground of the electronic component is electrically connected when the electronic component is operated, since the ground wiring layer of the electronic component is electrically connected to the conductive inner wall of the lid. Is completely shielded by the second ground wiring layer and the inner wall of the lid in a stable ground state. As a result, adverse effects such as malfunctions are not exerted on electronic components housed inside or other devices arranged close to the outside, and these can be normally and stably operated.

【0048】以上のように本発明によれば、内部に収容
する電子部品と接続されたグランド配線層から発生する
ノイズの悪影響を抑え、内部に収容する電子部品を長期
間にわたり正常かつ安定に作動させることができる電子
部品収納用パッケージを提供することができた。
As described above, according to the present invention, the adverse effects of noise generated from the ground wiring layer connected to the electronic components housed therein are suppressed, and the electronic components housed therein operate normally and stably for a long period of time. An electronic component storage package that can be provided can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の電子部品収納用パッケージの実施の形
態の一例を示す断面図である。
FIG. 1 is a cross-sectional view illustrating an example of an embodiment of an electronic component storage package according to the present invention.

【図2】従来の電子部品収納用パッケージの例を示す断
面図である。
FIG. 2 is a cross-sectional view illustrating an example of a conventional electronic component storage package.

【符号の説明】[Explanation of symbols]

1・・・・・・基体 2・・・・・・信号配線層 3・・・・・・電源配線層 4・・・・・・第1のグランド配線層 5・・・・・・第2のグランド配線層 6・・・・・・半導体素子(電子部品) 7・・・・・・蓋体 8・・・・・・金属層(導電性の内壁) DESCRIPTION OF SYMBOLS 1 ... Base 2 ... Signal wiring layer 3 ... Power supply wiring layer 4 ... 1st ground wiring layer 5 ... 2nd Ground wiring layer 6: Semiconductor element (electronic component) 7: Lid 8: Metal layer (conductive inner wall)

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 内部に信号配線層および該信号配線層を
上下から挟む複数のグランド配線層を有するとともに上
面に電子部品を搭載するための搭載部を有する基体と、
前記搭載部に搭載される前記電子部品を内部に収容する
ための凹部を有する蓋体とから成り、前記基体と前記蓋
体とを封止材を介して接合することによって内部に前記
電子部品を気密に収容するようになした電子部品収納用
パッケージであって、前記複数のグランド配線層は、前
記電子部品のグランドが電気的に接続される第1のグラ
ンド配線層と、該第1のグランド配線層の外側に位置す
る第2のグランド配線層とから成り、かつ前記蓋体の内
壁を導電性となすとともに該内壁を前記第2のグランド
配線層に電気的に接続させたことを特徴とする電子部品
収納用パッケージ。
A base having a signal wiring layer and a plurality of ground wiring layers sandwiching the signal wiring layer from above and below, and having a mounting portion for mounting an electronic component on an upper surface;
A lid having a concave portion for accommodating the electronic component mounted on the mounting portion, the electronic component being internally formed by joining the base and the lid via a sealing material. An electronic component storage package adapted to be hermetically stored, wherein the plurality of ground wiring layers include a first ground wiring layer electrically connected to a ground of the electronic component, and a first ground. A second ground wiring layer located outside the wiring layer, wherein the inner wall of the lid is made conductive and the inner wall is electrically connected to the second ground wiring layer. Electronic component storage package.
JP35190698A 1998-12-10 1998-12-10 Electronic component storage package and semiconductor device using the same Expired - Fee Related JP3766556B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35190698A JP3766556B2 (en) 1998-12-10 1998-12-10 Electronic component storage package and semiconductor device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35190698A JP3766556B2 (en) 1998-12-10 1998-12-10 Electronic component storage package and semiconductor device using the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2005350622A Division JP4164089B2 (en) 2005-12-05 2005-12-05 Electronic component storage package and semiconductor device using the same

Publications (2)

Publication Number Publication Date
JP2000183208A true JP2000183208A (en) 2000-06-30
JP3766556B2 JP3766556B2 (en) 2006-04-12

Family

ID=18420434

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35190698A Expired - Fee Related JP3766556B2 (en) 1998-12-10 1998-12-10 Electronic component storage package and semiconductor device using the same

Country Status (1)

Country Link
JP (1) JP3766556B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158080A (en) * 2005-12-06 2007-06-21 Nec Electronics Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158080A (en) * 2005-12-06 2007-06-21 Nec Electronics Corp Semiconductor device

Also Published As

Publication number Publication date
JP3766556B2 (en) 2006-04-12

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