JP2001185675A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2001185675A JP2001185675A JP36510799A JP36510799A JP2001185675A JP 2001185675 A JP2001185675 A JP 2001185675A JP 36510799 A JP36510799 A JP 36510799A JP 36510799 A JP36510799 A JP 36510799A JP 2001185675 A JP2001185675 A JP 2001185675A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- opening
- semiconductor
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73207—Bump and wire connectors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子を搭載
するための半導体素子搭載用基板に複数の半導体素子を
重ねて搭載して成る半導体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of semiconductor elements mounted on a semiconductor element mounting substrate for mounting semiconductor elements.
【０００２】[0002]
【従来の技術】従来、半導体素子を搭載するための半導
体素子搭載用基板に複数個の半導体素子を重ねて搭載し
て成る半導体装置として、例えば図７に断面図で示すよ
うに、略四角平板状の絶縁基板64の上面に半導体素子を
搭載するための搭載部64ａおよび半導体素子の各電極が
電気的に接続される半導体素子接続用パッド65ａを有す
るとともに、この絶縁基板64の下面に半導体素子接続用
パッド65ａに電気的に接続された外部接続用パッド65ｂ
を有する半導体素子搭載用基板61と、この半導体素子搭
載用基板61の搭載部64ａに搭載され、その上面外周部に
半導体素子接続用パッド65ａにボンディングワイヤ78を
介して電気的に接続された第一電極72ａおよびこの第一
電極72ａの内側に設けられた第二電極72ｂを有する第一
半導体素子72と、この第一半導体素子72の上面に搭載さ
れ、その下面に第二電極72ｂに金属バンプ76を介してフ
リップチップ接続により電気的に接続された第三電極73
ａを有する第二半導体素子73と、半導体素子搭載用基板
61の上面に第一半導体素子７２および第二半導体素子７
３の電極形成面を保護するように固着された樹脂製封止
材77とを具備して成る半導体装置が知られている。この
ような半導体素子搭載用基板61上に半導体素子72および
73を積み重ねて搭載して成る従来の半導体装置は、外部
接続用パッド65ｂを例えば半田を介して外部電気回路基
板の配線導体に接合することによって外部電気回路基板
に実装される。そして、このような半導体装置では、半
導体素子搭載用基板61上に複数の半導体素子72・73を積
み重ねて搭載することから、外部電気回路基板への実装
密度を高いものとすることができる。2. Description of the Related Art Conventionally, as a semiconductor device in which a plurality of semiconductor elements are stacked and mounted on a semiconductor element mounting substrate for mounting semiconductor elements, for example, as shown in a sectional view of FIG. A mounting portion 64a for mounting the semiconductor element on the upper surface of the insulating substrate 64 and a semiconductor element connection pad 65a to which each electrode of the semiconductor element is electrically connected, and a semiconductor element on the lower surface of the insulating substrate 64 External connection pad 65b electrically connected to connection pad 65a
A semiconductor element mounting substrate 61 having a semiconductor element mounting substrate 61 and a semiconductor element mounting pad 64a mounted on the mounting portion 64a of the semiconductor element mounting substrate 61 and electrically connected to a semiconductor element connection pad 65a via a bonding wire 78 on an upper peripheral portion thereof. A first semiconductor element 72 having one electrode 72a and a second electrode 72b provided inside the first electrode 72a, and mounted on the upper surface of the first semiconductor element 72, and a metal bump on the second electrode 72b on the lower surface. Third electrode 73 electrically connected by flip-chip connection via 76
a second semiconductor element 73 having a and a semiconductor element mounting substrate
The first semiconductor element 72 and the second semiconductor element 7
A semiconductor device comprising a resin sealing material 77 fixed so as to protect the electrode forming surface of No. 3 is known. On such a semiconductor element mounting substrate 61, the semiconductor element 72 and
A conventional semiconductor device having a stack of 73 mounted thereon is mounted on an external electric circuit board by bonding the external connection pad 65b to a wiring conductor of the external electric circuit board via, for example, solder. In such a semiconductor device, since the plurality of semiconductor elements 72 and 73 are stacked and mounted on the semiconductor element mounting substrate 61, the mounting density on the external electric circuit board can be increased.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、この従
来の半導体装置によれば、半導体素子搭載用基板61上に
第一半導体素子72および第二半導体素子73を積み重ねて
搭載して成ることから、その高さが半導体素子搭載用基
板61とその上に搭載された第一半導体素子72および第二
半導体素子73とを合わせた極めて高いものとなり、この
ような半導体装置を利用した電子機器の薄型化に対して
障害となるという問題点を有していた。However, according to this conventional semiconductor device, the first semiconductor element 72 and the second semiconductor element 73 are stacked and mounted on the semiconductor element mounting substrate 61. The height becomes extremely high in combination with the semiconductor element mounting substrate 61 and the first semiconductor element 72 and the second semiconductor element 73 mounted thereon, and it is possible to reduce the thickness of electronic equipment using such a semiconductor device. However, it has a problem that it becomes an obstacle.
【０００４】本発明は、かかる従来の問題点に鑑み案出
されたものであり、その目的は、複数の半導体素子が積
み重ねられた薄型の半導体装置を提供することにある。The present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a thin semiconductor device in which a plurality of semiconductor elements are stacked.
【０００５】[0005]
【課題を解決するための手段】本発明の半導体装置は、
中央部に開口を有する絶縁基板の上面に複数の半導体素
子接続用パッドが形成され、下面にこの半導体素子接続
用パッドに電気的に接続された複数の外部接続用パッド
が形成されて成る半導体素子搭載用基板と、この半導体
素子搭載用基板の上面に開口を覆うようにして半導体素
子接続用パッドにフリップチップ接続されて搭載された
第一半導体素子と、この第一半導体素子の下面に電気的
に接続されて搭載され、開口内に収容された第二半導体
素子とを具備することを特徴とするものである。According to the present invention, there is provided a semiconductor device comprising:
A semiconductor element comprising: a plurality of semiconductor element connection pads formed on an upper surface of an insulating substrate having an opening in a central portion; and a plurality of external connection pads electrically connected to the semiconductor element connection pads on a lower surface. A mounting substrate, a first semiconductor element mounted flip-chip connected to a semiconductor element connection pad so as to cover an opening on the upper surface of the semiconductor element mounting substrate, and an electric lower surface of the first semiconductor element. And a second semiconductor element mounted in the opening and accommodated in the opening.
【０００６】本発明の半導体装置によれば、半導体素子
搭載用基板の上面に開口を覆うようにして搭載された第
一半導体素子の下面に、第二半導体素子が開口内に収容
されるようにして搭載されていることから、その高さが
半導体素子搭載用基板とこれに搭載された第一半導体素
子とを合わせた高さとなり、従って薄型化が可能であ
る。According to the semiconductor device of the present invention, the second semiconductor element is accommodated in the opening on the lower surface of the first semiconductor element mounted on the upper surface of the semiconductor element mounting substrate so as to cover the opening. Since the semiconductor element is mounted on the substrate, the height thereof is the total height of the semiconductor element mounting substrate and the first semiconductor element mounted on the substrate, and therefore, the thickness can be reduced.
【０００７】[0007]
【発明の実施の形態】次に、本発明を添付の図面を基に
説明する。図１は、本発明の半導体装置の実施形態の一
例を示す断面図であり、図１において、１は半導体素子
搭載用基板、２は第一半導体素子、３は第二半導体素子
である。Next, the present invention will be described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an example of a semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a substrate for mounting a semiconductor element, 2 denotes a first semiconductor element, and 3 denotes a second semiconductor element.
【０００８】半導体素子搭載用基板１は、その中央部に
略四角形の開口Ａを有する略四角枠状の絶縁基板４と、
この絶縁基板４の上面から内部を介して下面にかけて被
着形成された複数の配線導体５とから構成されている。The substrate 1 for mounting a semiconductor element has a substantially square frame-shaped insulating substrate 4 having a substantially square opening A at the center thereof.
The insulating substrate 4 is composed of a plurality of wiring conductors 5 formed from the upper surface to the lower surface through the inside.
【０００９】絶縁基板４は、酸化アルミニウム質焼結体
や窒化アルミニウム質焼結体・ムライト質焼結体・炭化
珪素質焼結体・窒化珪素質焼結体・ガラスセラミックス
等の電気絶縁材料から成り、第一半導体素子２および第
二半導体素子３を支持するための支持部材として機能す
る。そして、例えば酸化アルミニウム質焼結体から成る
場合であれば、主原料としての酸化アルミニウム粉末に
焼結助剤としての酸化珪素粉末・酸化マグネシウム粉末
・酸化カルシウム粉末および適当な有機バインダ・溶剤
を添加混合して得たセラミックスラリを従来周知のドク
ターブレード法を採用してシート状に形成して複数枚の
セラミックグリーンシートを得、しかる後、これらのセ
ラミックグリーンシートに適当な打ち抜き加工を施すと
ともに積層して生セラミック成形体となし、最後にこの
生セラミック成形体を約1600℃の高温で焼成することに
よって製作される。The insulating substrate 4 is made of an electrically insulating material such as a sintered body of aluminum oxide, a sintered body of aluminum nitride, a sintered body of mullite, a sintered body of silicon carbide, a sintered body of silicon nitride, and glass ceramics. Thus, it functions as a supporting member for supporting the first semiconductor element 2 and the second semiconductor element 3. For example, in the case of an aluminum oxide sintered body, a silicon oxide powder, a magnesium oxide powder, a calcium oxide powder and a suitable organic binder and a solvent as sintering aids are added to aluminum oxide powder as a main raw material. The ceramic slurry obtained by mixing is formed into a sheet by employing a conventionally known doctor blade method to obtain a plurality of ceramic green sheets. Thereafter, these ceramic green sheets are subjected to appropriate punching and laminated. Then, the green ceramic molded body is formed, and finally, the green ceramic molded body is fired at a high temperature of about 1600 ° C.
【００１０】また、絶縁基板４に被着形成された配線導
体５は、タングステンやモリブデン・銅・銀等の金属粉
末メタライズ等の導電性材料から成り、第一半導体素子
２の各電極を外部電気回路基板に電気的に接続するため
の導電路として機能し、絶縁基板４の上面に露出した部
位が半導体素子接続用パッド５ａを形成しているととも
に、絶縁基板４の下面に露出した部位が外部接続用パッ
ド５ｂを形成している。The wiring conductor 5 formed on the insulating substrate 4 is made of a conductive material such as metal powder of tungsten, molybdenum, copper, silver or the like. The portion exposed on the upper surface of the insulating substrate 4 functions as a conductive path for electrically connecting to the circuit board, and the semiconductor element connection pad 5a is formed. The portion exposed on the lower surface of the insulating substrate 4 is external. The connection pad 5b is formed.
【００１１】そして、半導体素子接続用パッド５ａには
第一半導体素子２が金や半田から成るバンプ６ａを介し
てフリップチップ接続により接続されており、外部接続
用パッド５ｂを図示しない外部電気回路基板の配線導体
に半田を介して接続することにより第一半導体素子２が
配線導体５を介して外部電気回路に電気的に接続され
る。The first semiconductor element 2 is connected to the semiconductor element connection pad 5a by flip-chip connection via a bump 6a made of gold or solder, and the external connection pad 5b is connected to an external electric circuit board (not shown). The first semiconductor element 2 is electrically connected to an external electric circuit via the wiring conductor 5 by connecting to the wiring conductor of FIG.
【００１２】なお、配線導体５は、例えばタングステン
メタライズから成る場合であれば、タングステン粉末に
適当な有機バインダ・溶剤を添加混合して得た金属ペー
ストを絶縁基板４となるセラミックグリーンシートにス
クリーン印刷法を採用して所定パターンに印刷塗布し、
これを絶縁基板４となる生セラミック成形体とともに焼
成することによって絶縁基板４の上面から内部を介して
下面に導出するようにして被着形成される。また、配線
導体５の露出表面には配線導体５が酸化腐食するのを防
止するとともに半導体素子接続用パッド５ａとバンプ６
ａとの接続および外部接続用パッド５ｂと半田との接続
を良好なものとするために、通常であれば、１〜10μｍ
程度の厚みのニッケルめっきと0.1 〜３μｍ程度の厚み
の金めっきとが順次施されている。If the wiring conductor 5 is made of, for example, tungsten metallization, a metal paste obtained by adding and mixing an appropriate organic binder and solvent to tungsten powder is screen-printed on a ceramic green sheet serving as the insulating substrate 4. Printing and applying in a predetermined pattern by adopting the method,
This is fired together with the green ceramic molded body to be the insulating substrate 4 so that the insulating substrate 4 is adhered and formed so as to be led out from the upper surface to the lower surface via the inside. On the exposed surface of the wiring conductor 5, the wiring conductor 5 is prevented from being oxidized and corroded, and the semiconductor element connection pads 5a and the bumps 6 are formed.
In order to improve the connection with the a and the connection between the external connection pad 5b and the solder, it is usually 1 to 10 μm.
Nickel plating having a thickness of about 0.1 μm and gold plating having a thickness of about 0.1 to 3 μm are sequentially applied.
【００１３】また、この半導体素子搭載用基板１の上面
には、第一半導体素子２が開口Ａを覆うようにして搭載
されている。第一半導体素子２は、その下面外周部で半
導体素子接続用パッド５ａと相対向する位置に複数の第
一電極２ａを有しており、この第一電極２ａが半導体素
子接続用パッド５ａに金や半田から成るバンプ６ａを介
してフリップチップ接続されている。A first semiconductor element 2 is mounted on the upper surface of the semiconductor element mounting substrate 1 so as to cover the opening A. The first semiconductor element 2 has a plurality of first electrodes 2a at positions facing the semiconductor element connection pads 5a at the outer periphery of the lower surface, and the first electrodes 2a are connected to the semiconductor element connection pads 5a by gold. It is flip-chip connected via a bump 6a made of metal or solder.
【００１４】なお、第一電極２ａと半導体素子接続用パ
ッド５ａとのバンプ６ａを介した接続は、例えばバンプ
６ａが金から成る場合であれば、第一電極２ａの下面に
金から成るバンプ６ａを予め取着させておくとともに、
このバンプ６ａを半導体素子接続用パッド５ａに熱圧着
する方法が採用され得る。The connection between the first electrode 2a and the pad 5a for connecting the semiconductor element via the bump 6a is performed, for example, when the bump 6a is made of gold, the bump 6a made of gold is formed on the lower surface of the first electrode 2a. Is attached in advance,
A method of thermocompression bonding the bump 6a to the semiconductor element connection pad 5a can be adopted.
【００１５】さらに、第一半導体素子２の下面で、開口
Ａ内には、第二電極２ｂが形成されているとともに、こ
の第二電極２ｂに金や半田から成るバンプ６ｂを介して
フリップチップ接続された第三電極３ａを有する第二半
導体素子３が開口Ａ内に収容されるようにして搭載され
ている。Further, a second electrode 2b is formed in the opening A on the lower surface of the first semiconductor element 2, and the second electrode 2b is flip-chip connected to the second electrode 2b via a bump 6b made of gold or solder. The second semiconductor element 3 having the formed third electrode 3a is mounted so as to be accommodated in the opening A.
【００１６】この場合、第二半導体素子３は、開口Ａ内
に収容されるようにして第一半導体素子２の下面に搭載
されていることから、半導体装置の高さは半導体素子搭
載用基板１と第一半導体素子２とを合わせた高さと成
り、したがって、薄型の半導体装置となる。なお、第二
電極２ｂと第三電極３ａとのバンプ６ｂを介した接続
は、例えばバンプ６ｂが半田から成る場合であれば、第
二電極２ｂ・第三電極３ａの一方に半田から成るバンプ
６ｂを予め取着させておくとともに、これを他方に熱圧
着や溶着により接合する方法が採用される。In this case, since the second semiconductor element 3 is mounted on the lower surface of the first semiconductor element 2 so as to be accommodated in the opening A, the height of the semiconductor device is reduced by the semiconductor element mounting substrate 1. And the first semiconductor element 2 together, and thus a thin semiconductor device. The connection between the second electrode 2b and the third electrode 3a via the bump 6b is performed, for example, when the bump 6b is made of solder, the bump 6b made of solder is connected to one of the second electrode 2b and the third electrode 3a. Is attached in advance, and this is joined to the other by thermocompression bonding or welding.
【００１７】また、半導体素子搭載用基板１の上面と第
一半導体素子２との間、および第一半導体素子２と第二
半導体素子３との間には、エポキシ樹脂等の熱硬化性樹
脂から成る樹脂製封止材７が充填固着されている。樹脂
製封止材７は、第一半導体素子２および第二半導体素子
３の電極形成面ならびにバンプ６ａ・６ｂを外部環境か
ら保護するための保護部材として機能するとともに、半
導体素子搭載用基板１と第一半導体素子２との接合およ
び第一半導体素子２と第二半導体素子３との接合を強固
なものとなす接着剤として機能し、液状の未硬化樹脂を
半導体素子搭載用基板１の上面と第一半導体素子２との
間、および第一半導体素子２と第二半導体素子３との間
に注入するとともにこれを熱硬化させることによって半
導体素子搭載用基板１の上面と第一半導体素子２との
間、および第一半導体素子２と第二半導体素子３との間
に充填固着される。A thermosetting resin such as an epoxy resin is provided between the upper surface of the semiconductor element mounting substrate 1 and the first semiconductor element 2 and between the first semiconductor element 2 and the second semiconductor element 3. Is filled and fixed. The resin sealing material 7 functions as a protection member for protecting the electrode formation surfaces of the first semiconductor element 2 and the second semiconductor element 3 and the bumps 6a and 6b from the external environment, and the semiconductor element mounting substrate 1 A liquid uncured resin that functions as an adhesive for bonding the first semiconductor element 2 and the first semiconductor element 2 and the second semiconductor element 3 to each other is made strong. Injection is performed between the first semiconductor element 2 and between the first semiconductor element 2 and the second semiconductor element 3 and the thermosetting of the first semiconductor element 2 and the second semiconductor element 3. And between the first semiconductor element 2 and the second semiconductor element 3.
【００１８】かくして、本発明の半導体装置によれば、
複数の半導体素子が積み重ねられた薄型の半導体装置を
提供することができる。Thus, according to the semiconductor device of the present invention,
A thin semiconductor device in which a plurality of semiconductor elements are stacked can be provided.
【００１９】なお、本発明は、上述の実施の形態例に限
定されるものではなく、本発明の要旨を逸脱しない範囲
であれば種々の変更は可能であることは言うまでもな
い。例えば図２に断面図で示すように、上述の実施形態
例で用いたのと同様の半導体素子搭載用基板１の上面
に、第一半導体素子12を開口Ａを覆うようにしてフリッ
プチップ接続により搭載するとともに、この第一半導体
素子12の下面に第二半導体素子13を開口Ａ内に収容され
るようにしてフリップチップ接続により搭載し、さらに
この第二半導体素子13の下面に第三半導体素子14を開口
Ａ内に収容されるようにして搭載してもよい。この例の
場合、第三半導体素子14の下面に電極が形成されている
とともに、この電極と第一半導体素子12の電極とがボン
ディングワイヤ18を介して接続されている。そして、半
導体素子搭載用基板１と第一半導体素子12との間および
開口Ａ内に樹脂製封止材17が充填固着されている。この
例においては第二半導体素子13および第三半導体素子14
が開口Ａ内に収容されていることから更なる高密度実装
が可能となる。It should be noted that the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the scope of the present invention. For example, as shown in the cross-sectional view of FIG. 2, the first semiconductor element 12 is formed on the upper surface of the semiconductor element mounting substrate 1 similar to that used in the above-described embodiment by flip-chip connection so as to cover the opening A. At the same time, the second semiconductor element 13 is mounted on the lower surface of the first semiconductor element 12 by flip-chip connection so as to be accommodated in the opening A, and the third semiconductor element 13 is mounted on the lower surface of the second semiconductor element 13. 14 may be mounted so as to be accommodated in the opening A. In the case of this example, an electrode is formed on the lower surface of the third semiconductor element 14, and this electrode is connected to the electrode of the first semiconductor element 12 via the bonding wire 18. A resin sealing material 17 is filled and fixed between the semiconductor element mounting substrate 1 and the first semiconductor element 12 and in the opening A. In this example, the second semiconductor element 13 and the third semiconductor element 14
Are accommodated in the opening A, so that further high-density mounting is possible.
【００２０】また、図３に断面図で示すように、上述の
実施形態例で用いたのと同様の半導体素子搭載用基板１
の上面に、第一半導体素子22を開口Ａを覆うようにして
フリップチップ接続により搭載するとともに、この第一
半導体素子22の下面に第二半導体素子23をその電極形成
面を下にして開口Ａ内に収容されるようにして搭載し、
第一半導体素子22の電極と第二半導体素子23の電極とを
ボンディングワイヤ28を介して接続するとともに、半導
体素子搭載用基板１と第一半導体素子22との間および開
口Ａ内に樹脂製封止材27を充填固着させてもよい。As shown in the sectional view of FIG. 3, the same semiconductor element mounting substrate 1 as used in the above-described embodiment is used.
A first semiconductor element 22 is mounted on the upper surface of the first semiconductor element 22 by flip-chip connection so as to cover the opening A, and a second semiconductor element 23 is mounted on the lower surface of the first semiconductor element 22 with its electrode forming surface facing down. It is mounted so that it is housed inside,
The electrodes of the first semiconductor element 22 and the electrodes of the second semiconductor element 23 are connected via bonding wires 28, and a resin seal is provided between the semiconductor element mounting substrate 1 and the first semiconductor element 22 and in the opening A. The stopper 27 may be filled and fixed.
【００２１】さらに、図４に断面図で示すように、上述
の実施形態例で用いたのと同様の半導体素子搭載用基板
１の上面に、第一半導体素子32を開口Ａを覆うようにし
てフリップチップ接続により搭載するとともに、この第
一半導体素子32の下面に第二半導体素子33をその電極形
成面を下にして開口Ａ内に収容されるようにして搭載
し、この第二半導体素子33の電極と第一半導体素子32の
電極とをボンディングワイヤ38を介して接続し、さらに
この第二半導体素子33の下面に第三半導体素子３４を開
口Ａ内に収容されるようにしてフリップチップ接続によ
り搭載するとともに、半導体素子搭載用基板１と第一半
導体素子３２との間および開口Ａ内に樹脂製封止材37を
充填固着させてもよい。Further, as shown in the sectional view of FIG. 4, the first semiconductor element 32 is formed on the upper surface of the semiconductor element mounting substrate 1 similar to that used in the above-described embodiment so as to cover the opening A. A second semiconductor element 33 is mounted on the lower surface of the first semiconductor element 32 so as to be housed in the opening A with its electrode forming surface facing down, and the second semiconductor element 33 And the electrode of the first semiconductor element 32 are connected via a bonding wire 38, and a third semiconductor element 34 is accommodated in the opening A on the lower surface of the second semiconductor element 33 so as to be flip-chip connected. In addition, the resin sealing material 37 may be filled and fixed between the semiconductor element mounting substrate 1 and the first semiconductor element 32 and in the opening A.
【００２２】またさらに、図５に断面図で示すように、
上述の実施形態例で用いたのと同様の半導体素子搭載用
基板１の上面に、第一半導体素子42を開口Ａを覆うよう
にしてフリップチップ接続により搭載するとともに、こ
の第一半導体素子42の下面に第二半導体素子43をその電
極形成面を下にして開口Ａ内に収容されるようにして搭
載し、この第二半導体素子43の電極と第一半導体素子42
の電極とをボンディングワイヤ48ａを介して接続し、さ
らにこの第二半導体素子43の下面に第三半導体素子44を
その電極形成面を下にして開口Ａ内に収容されるように
して搭載し、この第三半導体素子44の電極と第二半導体
素子43の電極とをボンディングワイヤ48ｂを介して接続
するとともに、半導体素子搭載用基板１と第一半導体素
子42との間および開口Ａ内に樹脂製封止材47を充填固着
させてもよい。Further, as shown in a sectional view in FIG.
The first semiconductor element 42 is mounted on the upper surface of the semiconductor element mounting substrate 1 similar to that used in the above-described embodiment by flip-chip connection so as to cover the opening A. On the lower surface, the second semiconductor element 43 is mounted so that the electrode forming surface thereof faces down in the opening A, and the electrode of the second semiconductor element 43 and the first semiconductor element 42 are mounted.
Are connected via bonding wires 48a, and a third semiconductor element 44 is mounted on the lower surface of the second semiconductor element 43 such that the third semiconductor element 44 is housed in the opening A with its electrode forming surface facing down, The electrodes of the third semiconductor element 44 and the electrodes of the second semiconductor element 43 are connected via bonding wires 48b, and a resin material is provided between the semiconductor element mounting substrate 1 and the first semiconductor element 42 and in the opening A. The sealing material 47 may be filled and fixed.
【００２３】さらにまた、図６に断面図で示すように、
上述の実施形態例で用いたのと同様の半導体素子搭載用
基板１の上面に、第一半導体素子52を開口Ａを覆うよう
にしてフリップチップ接続により搭載するとともに、こ
の第一半導体素子52の下面に第二半導体素子53をその電
極形成面を下にして開口Ａ内に収容されるようにして搭
載し、この第二半導体素子53の電極と第一半導体素子52
の電極とをボンディングワイヤ58ａを介して接続し、さ
らにこの第二半導体素子53の下面に第三半導体素子54を
その電極形成面を下にして開口Ａ内に収容されるように
して搭載し、この第三半導体素子54の電極と第一半導体
素子52の電極とをボンディングワイヤ58ｂを介して接続
するとともに、半導体素子搭載用基板１と第一半導体素
子52との間および開口Ａ内に樹脂製封止材57を充填固着
させてもよい。Further, as shown in a sectional view in FIG.
The first semiconductor element 52 is mounted on the upper surface of the semiconductor element mounting substrate 1 similar to that used in the above-described embodiment by flip-chip connection so as to cover the opening A. A second semiconductor element 53 is mounted on the lower surface so that the electrode forming surface thereof is received in the opening A, and the electrode of the second semiconductor element 53 and the first semiconductor element 52 are mounted.
And the third semiconductor element 54 is mounted on the lower surface of the second semiconductor element 53 such that the third semiconductor element 54 is housed in the opening A with its electrode forming surface down, The electrodes of the third semiconductor element 54 and the electrodes of the first semiconductor element 52 are connected via bonding wires 58b, and a resin material is provided between the semiconductor element mounting substrate 1 and the first semiconductor element 52 and in the opening A. The sealing material 57 may be filled and fixed.
【００２４】[0024]
【発明の効果】本発明の半導体装置によれば、半導体素
子搭載用基板の上面に開口を覆うようにして搭載された
第一半導体素子の下面に、第二半導体素子が開口内に収
容されるようにして搭載されていることから、その高さ
が半導体素子搭載用基板とこれに搭載された第一半導体
素子とを合わせた高さとなり、従って薄型の半導体装置
を提供することが可能である。According to the semiconductor device of the present invention, the second semiconductor element is housed in the opening on the lower surface of the first semiconductor element mounted on the upper surface of the semiconductor element mounting substrate so as to cover the opening. Since the semiconductor device is mounted as described above, the height thereof is equal to the height of the semiconductor element mounting substrate and the first semiconductor element mounted thereon, and thus a thin semiconductor device can be provided. .
【図１】本発明の半導体装置の実施形態の一例を示す断
面図である。FIG. 1 is a cross-sectional view illustrating an example of an embodiment of a semiconductor device of the present invention.
【図２】本発明の半導体装置の実施形態の他の例を示す
断面図である。FIG. 2 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention.
【図３】本発明の半導体装置の実施形態の他の例を示す
断面図である。FIG. 3 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention.
【図４】本発明の半導体装置の実施形態の他の例を示す
断面図である。FIG. 4 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention.
【図５】本発明の半導体装置の実施形態の他の例を示す
断面図である。FIG. 5 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention.
【図６】本発明の半導体装置の実施形態の他の例を示す
断面図である。FIG. 6 is a sectional view showing another example of the embodiment of the semiconductor device of the present invention.
【図７】従来の半導体装置の断面図である。FIG. 7 is a sectional view of a conventional semiconductor device.
１：半導体素子搭載用基板 ２，12，22，32，42，52：第一半導体素子 ３，13，23，33，43，53：第二半導体素子 ４：絶縁基板 ５ａ：半導体素子接続用パッド ５ｂ：外部接続用パッド Ａ：開口 1: Substrate for mounting semiconductor element 2, 12, 22, 32, 42, 52: First semiconductor element 3, 13, 23, 33, 43, 53: Second semiconductor element 4: Insulating substrate 5a: Pad for connecting semiconductor element 5b: External connection pad A: Opening
Claims (1)
複数の半導体素子接続用パッドが形成され、下面に該半
導体素子接続用パッドに電気的に接続された複数の外部
接続用パッドが形成されて成る半導体素子搭載用基板
と、該半導体素子搭載用基板の上面に前記開口を覆うよ
うにして前記半導体素子接続用パッドにフリップチップ
接続されて搭載された第一半導体素子と、該第一半導体
素子の下面に電気的に接続されて搭載され、前記開口内
に収容された第二半導体素子とを具備することを特徴と
する半導体装置。A plurality of semiconductor element connection pads are formed on an upper surface of an insulating substrate having an opening in a central portion, and a plurality of external connection pads electrically connected to the semiconductor element connection pads are formed on a lower surface. A first semiconductor element mounted on the upper surface of the semiconductor element mounting board by flip-chip connection to the semiconductor element connection pad so as to cover the opening; A semiconductor device comprising: a second semiconductor element which is electrically connected to and mounted on a lower surface of the semiconductor element and is accommodated in the opening.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36510799A JP2001185675A (en) | 1999-12-22 | 1999-12-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36510799A JP2001185675A (en) | 1999-12-22 | 1999-12-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2001185675A true JP2001185675A (en) | 2001-07-06 |
Family
ID=18483450
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36510799A Pending JP2001185675A (en) | 1999-12-22 | 1999-12-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2001185675A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308258A (en) * | 2000-04-26 | 2001-11-02 | Sony Corp | Semiconductor package and method of manufacturing it |
| JP2004342738A (en) * | 2003-05-14 | 2004-12-02 | Fujitsu Ltd | Semiconductor device and its manufacturing method, and semiconductor device precursor and its manufacturing method |
| JP2006080350A (en) * | 2004-09-10 | 2006-03-23 | Denso Corp | Semiconductor device, and mounting structure thereof |
-
1999
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001308258A (en) * | 2000-04-26 | 2001-11-02 | Sony Corp | Semiconductor package and method of manufacturing it |
| JP2004342738A (en) * | 2003-05-14 | 2004-12-02 | Fujitsu Ltd | Semiconductor device and its manufacturing method, and semiconductor device precursor and its manufacturing method |
| JP2006080350A (en) * | 2004-09-10 | 2006-03-23 | Denso Corp | Semiconductor device, and mounting structure thereof |
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