JPS633441A - Package for integrated circuit - Google Patents

Abstract

PURPOSE:To prevent erroneous operations due to external noises and unnecessary electromagnetic waves, by packaging a chip by a package base part, on which a metallized layer for a shield pattern is laminated, and a package cover part, on the inner surface of which a metallized layer for a shield pattern is provided. CONSTITUTION:Both a package base part 1 and a package cover part 2 are coupled with a packaging material 4. A polyimide quartz plate 9 is laminated on a ceramic bottom plate. A metallized layer 8 for a shield pattern is formed on the surface of the quartz plate 9. An island layer is laminated on the metallized layer 8. A metallized layer 5 for an island pattern is formed on the island layer. A polyimide quartz plate 9' is laminated on a ceramic top plate. A metallized layer 8' for a shield is formed on the quartz plate 9'. An integrated circuit chip 10 is mounted on the metallized layer 5. Thus erroneous operations due to external noises and unnecessary electromagnetic waves can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit package, and particularly to a multilayer laminated ceramic package that takes measures against external noise.

[Prior Art] Conventionally, this type of integrated circuit package has a single-layer or two-layer electrode layer for connection wiring, and each electrode for signal, power supply, or ground is mixed individually.

Moreover, the package cover was simply a metal cap or a ceramic lid placed over the package and sealed with a sealing material.

[Problem that the invention attempts to solve] The conventional integrated circuit packages mentioned above are for signals.

Since electrode patterns for individual connection wiring for power or ground are mixed, if the number of bonding pads on the chip increases, the number of connection wiring electrodes and external terminals on the package will correspondingly increase. However, the package mounting area increases significantly, and in order to increase the packaging density, the spacing between electrodes becomes smaller, which may make wire bonding difficult or cause leakage or short circuits between wiring lines. High-density mounting was difficult.

Furthermore, conventional packages do not take measures to protect the internal integrated circuits from malfunctions and characteristic deterioration caused by external noise and unnecessary electromagnetic waves.

[Means for Solving the Problems] The present invention provides a package for mounting an integrated circuit chip, which has electrodes formed of a metal vapor deposited film on a ceramic substrate and a pattern for connecting to external terminals. It has a package base in which a polyimide/quartz plate and a metallized layer for a shield pattern are laminated on the surface facing an individual layer for grounding and an integrated circuit chip, and a package cover part in which a metallized layer for a shield pattern is provided on the inner surface, This is a multilayer laminated ceramic package for an integrated circuit, characterized in that an integrated circuit chip is sealed in the package base portion and the cover portion.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

As shown in FIGS. 1A and 1B, the integrated circuit package according to the present invention consists of a package base 1 and a package cover 2, both of which are bonded together with a sealant 4. As shown in FIGS.

The package base 1 has the following structure. In other words,
As shown in FIGS. 1(A), (B), 2, and 4, a polyimide/quartz plate 9 is laminated on the ceramic bottom plate 1a, and a shield pattern metallization 8 is placed on the surface of the polyimide/quartz plate 9. and metallize 8 for shield pattern.
An island layer 1b is laminated thereon, and an island pattern metallization 5 is formed on the island layer 1b. As roughly shown in FIGS. 3(A), 3(B), and 4, a power supply wiring layer 1C is laminated on the island layer 1b, and an opening for housing the integrated circuit chip 10 is formed in the center of the power supply wiring layer 1C. A power supply pattern metallization 6 is formed around the opening 01 so as to surround the chip 10, and a power supply wiring layer 1C is formed.
A signal wiring layer 1d is laminated thereon, and an opening 02 for housing the integrated circuit chip 10 is provided in the center of the signal wiring layer 1d.
A signal pattern metallization 7 is formed around the periphery of the chip 2 so as to surround the chip. Further, around the package base 1, metallized external terminals for power supply 3a, external terminal metallized ground 3b, and external terminal metalized signals 3C are formed.

On the other hand, the package cover section 2 has the following structure. That is, Fig. 1 (A), (13), Fig. 2,
As shown in FIG. 5, a polyimide/quartz plate 9' is laminated on the ceramic top plate 2a, a shield pattern metallization 8' is formed on the polyimide/quartz plate 9', and an integrated circuit chip 10 is housed in the center. A cover frame 2b having an opening 03 is laminated on the shield pattern metallization 8'.

The integrated circuit chip 10 has an island pattern metallization 5
The power supply pads on the chip 10 are connected to the power supply pattern metallization 6, and the signal pads of the chip 10 are connected to the signal pattern metallization 7 by wire bonding.

From the metallization of each layer of the package, external terminal metallization 3a, 3b, 3c for power supply, ground, and signal are formed on the side of the package according to patterns for each lead-out.
connected to. In addition, metallization 8 for shield pattern, which is a metal conductor film laminated on the bottom layer of the package base.
is connected to ground by external terminal metallization 3b,
It serves to shield incident noise from the bottom direction.

On the other hand, the top plate 2 of the ceramic substrate of the package cover part 2
Metallization 8 for shield pattern between a and frame 2b
' is metallization 8 for the shield pattern at the base of the package.
Similarly, it is connected to the ground by the external terminal metallization 3b, and serves to shield incident noise from above.

Then, as shown in FIGS. 1A, 1B, and 1C, the chip 10 is sealed with the package base 1 and the package cover 2, and a semiconductor device is completed.

FIGS. 6(A) and 6(B) show another embodiment of the present invention. In this embodiment, through holes 11 are provided in the island layer 1b and the island pattern metallization 5, and the other configurations are the same as in the previous embodiment.

[Effects of the Invention] As explained above, the present invention separates the signal and power (or ground) electrodes into different individual layers, and furthermore, the power line is formed as a common electrode pattern so as to surround the integrated circuit chip. Since the number of external terminals does not increase even if the number of pads on the integrated circuit chip increases, it is advantageous as a high-density mounting method, and the signal lines and Leakage and induced noise between power lines can be prevented.

In addition, by forming a metal conductor film on the inner surface of the package base and cover so as to sandwich the integrated circuit chip, it has a shielding effect against external noise and electromagnetic waves, and has the effect of reducing or preventing malfunctions and deterioration. It is something.

[Brief explanation of the drawing]

FIG. 1(A) is a sectional view illustrating the entire package structure of an integrated circuit according to an embodiment of the present invention, FIG. 1(8) is a side view, and FIG.
) is a perspective view, Figure 2 is an exploded perspective view of the package, Figure 3 (A) is a plan view of the base of the package, (8) is a bottom view of the same,
Fig. 4 is an exploded perspective view of the package base, Fig. 5 is an exploded perspective view of the package cover, Fig. 6 (A) is a sectional view showing another embodiment of the present invention, and (B) is a side view. It is. 1... Package base 1a... Ceramic bottom plate 1b... Island layer 1C... Power wiring layer 1d... Signal wiring layer 2... Package cover part 2a... Ceramic top plate 2b. ... Cover frame 3 ... External terminal metallization 3a ... External terminal metallization for power supply 3b ... External terminal metallization for ground 3C ... External terminal metallization for signal 4 ... Sealing material 5 ... Island Metallization for pattern 6...Metallization for power supply pattern 7...Metallization for signal pattern 8.8'...Metallization for shield pattern 9.9'
...Polyimide/quartz 10...Integrated circuit chip 11...Through hole

Claims (1)

[Claims] (1) In a package that mounts an integrated circuit chip,
Electrodes made of metal vapor deposited film on a ceramic substrate, separate layers for signals, power and ground with patterns for extraction to external terminals, and a polyimide/quartz plate and shield pattern on the surface facing the integrated circuit chip. A multilayer laminate characterized in that it has a package base on which a metallized layer for forming a shield pattern is laminated, and a package cover portion on an inner surface of which a metallized layer for a shield pattern is provided, and an integrated circuit chip is sealed in the package base and the cover portion. Ceramic integrated circuit package.