JPS60160146A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60160146A
JPS60160146A JP59014871A JP1487184A JPS60160146A JP S60160146 A JPS60160146 A JP S60160146A JP 59014871 A JP59014871 A JP 59014871A JP 1487184 A JP1487184 A JP 1487184A JP S60160146 A JPS60160146 A JP S60160146A
Authority
JP
Japan
Prior art keywords
conductor layer
wall member
metallized layer
semiconductor device
recession
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59014871A
Other languages
Japanese (ja)
Inventor
Takao Mikawa
三川　卓男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP59014871A priority Critical patent/JPS60160146A/en
Publication of JPS60160146A publication Critical patent/JPS60160146A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/647—Resistive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To improve the integration density of a semiconductor device while standardizing a circuit block by a method wherein a conductor layer is formed on a wall member of a vessel containing IC element while a resistance circuit net is provided on the surface of insulating cover member over the vessel through the intermediary of the conductor layer to connect IC element with the circuit net through the intermediary of the conductor layer. CONSTITUTION:A recession is provided on the central part of surface of a vessel containing an IC element 5 while the bottom of recession and projections encircling the bottom are respectively coated with a conductor layer 4. Besides a wall member 3 is fixed on the projections through the intermediary of the conductor layer 4 while overall side surfaces of the wall member 3 is coated with the conductor layer 4. Next the IC element 5 is contained in the recession to be connected to the conductor layer 4 of the wall member 3 using a metal wire 7 while the upper opening of the vessel is covered with a ceramic member 9 with metallized layer 10 extending from the overall surface to the end of backside. Later a resistance circuit net comprising a resistor 11 and a conductor 12 is provided on the surface of the cover member 9 then they are connected to the conductor layer 4 of the wall member 3 and the connections are bonded by solder 8.

Description

【発明の詳細な説明】 本発明は半導体装置の容器の構造に関するものである。[Detailed description of the invention] The present invention relates to the structure of a container for a semiconductor device.

プリント配線板に直接取り付ける半導体装置として、容
器側面のメタライズ層を外部導出用電極とする、いわゆ
るチップキャリアと呼ばれる半導体装置がある。かかる
半導体装置の従来の構造は容器の内底面に半導体チップ
を取り付け、容器側面の電極用メタライズ層と接続して
いる容器内のメタライズ層によるランドと半導体チップ
の電極とを金ワイヤー等でワイヤーボンディング接続し
たのち、その上面に金ｌＩ４またはセラミックの蓋をシ
ール材にて封止したものであった。すなわち半導体チッ
プの各電極がチップキャリアの各端面に形成された電極
用メタライズ層に接続されていただけであった。このた
め、チップキャリアを載置する配線板の面積利用効率が
悪かった。As a semiconductor device that is directly attached to a printed wiring board, there is a semiconductor device called a so-called chip carrier that uses a metallized layer on the side surface of a container as an electrode for leading to the outside. The conventional structure of such a semiconductor device is to attach a semiconductor chip to the inner bottom surface of a container, and wire bond the electrode of the semiconductor chip with a land made of a metallized layer inside the container that is connected to a metallized layer for electrodes on the side surface of the container using a gold wire or the like. After the connections were made, a lid made of gold lI4 or ceramic was sealed on the top surface with a sealing material. That is, each electrode of the semiconductor chip was simply connected to an electrode metallized layer formed on each end face of the chip carrier. For this reason, the area utilization efficiency of the wiring board on which the chip carrier is mounted was poor.

そこで、本発明はより集積度が高く、配線板の面積利用
効率の良い半導体装置を得た本ので、容器の蓋に厚膜ま
た薄膜で形成された抵抗回路網を有し、容器端面の電極
用メタライズ層と抵抗回路網を接続した半導体装置を得
る。すなわち、本発明によれば、収容される半導体集積
回路チップだけでなく、周辺回路をも同一容器に形成さ
れておル、実装基板をより小さくできる。Therefore, the present invention provides a semiconductor device that has a higher degree of integration and is more efficient in utilizing the area of the wiring board.The present invention has a resistor network formed of a thick or thin film on the lid of the container, and electrodes on the end surface of the container. A semiconductor device is obtained in which the metallized layer and the resistor network are connected. That is, according to the present invention, not only the semiconductor integrated circuit chip to be accommodated but also the peripheral circuits are formed in the same container, so that the mounting board can be made smaller.

次に図面を用いて本発明をよシ詳細に説明する。Next, the present invention will be explained in detail using the drawings.

ｓｇ１図、！２図は従来のチップキャリアである。sg1 figure! Figure 2 shows a conventional chip carrier.

これは容器の底板６上に半導体集積回路素子５を載置し
、底板６上のステッチランド４と素子５の電極とを金ワ
イヤ７でワイヤーボンディングによ多接続することによ
り、底板６と壁部材３との外周に形成された電極用メタ
ライズ層１と電気的に接続している。それを金員板また
セラミック板の蓋２をシール材で封止してできている。This is achieved by placing the semiconductor integrated circuit device 5 on the bottom plate 6 of the container, and connecting the stitch lands 4 on the bottom plate 6 and the electrodes of the device 5 with gold wires 7 by wire bonding. It is electrically connected to the electrode metallized layer 1 formed on the outer periphery of the member 3. It is made by sealing a lid 2 made of a metal plate or a ceramic plate with a sealing material.

第３図、第４図は本発明の一実施例である。半導体集積
回路素子５を容器の底板上に載置し、金ワイヤ７でワイ
ヤボンディングして素子５上の電極と電極用メタライズ
層１とを接続するまでは従来と変らない。本実施例では
蓋部材９として、その上表面に厚膜または薄膜で形成さ
れた抵抗体１１と導体１２からなる抵抗回路網を形成し
たセラミック基板を用いる。蓋部材９の抵抗回路網はメ
タライズ層１０を介して電極用メタライズ層１とが半田
８で接続されるように壁部材３にシール材で封止されて
いる。FIGS. 3 and 4 show an embodiment of the present invention. There is no difference from the conventional method until the semiconductor integrated circuit element 5 is placed on the bottom plate of the container and the electrodes on the element 5 are connected to the electrode metallized layer 1 by wire bonding with the gold wire 7. In this embodiment, as the lid member 9, a ceramic substrate is used, on the upper surface of which a resistance circuit network consisting of a resistor 11 and a conductor 12 formed of a thick or thin film is formed. The resistance circuit network of the lid member 9 is sealed to the wall member 3 with a sealant so that it is connected to the electrode metallized layer 1 via the metallized layer 10 with solder 8.

このように本発明では半導体集積回路と周辺回路とを一
体化した半導体装置を提供するものである。これにより
、半導体装置の高密度化ができ、回路ブロックの標準化
ができる効果がある。As described above, the present invention provides a semiconductor device in which a semiconductor integrated circuit and a peripheral circuit are integrated. This has the effect of increasing the density of semiconductor devices and standardizing circuit blocks.

【図面の簡単な説明】[Brief explanation of drawings]

ｗｔ１図は従来のチップキャリアの平面図、第２図は従
来のチップキャリアの断面図、第３図は本発明のチップ
キャリアの一実施例の平面図、第４図は本発明のチップ
キャリアの一実施例の断面図である。 １・・・・・・電極用メタライズ層、２・・・・・・蓋
ｍ材、３・・・・・・壁部材、４・・・・・・ステッチ
ランド導体部、５・・・・・・半導体集積回路素子、６
・・・・・・底部材、７・・・・・・金細線、８・・・
・・・半田、９・・・・・・蓋部材、１０・・・・・・
メタライズ層、１１・・・・・・導体部、１２・・・・
・・抵抗体。 代理人　弁理士　内　原　曽Fig. 1 is a plan view of a conventional chip carrier, Fig. 2 is a sectional view of a conventional chip carrier, Fig. 3 is a plan view of an embodiment of the chip carrier of the present invention, and Fig. 4 is a plan view of the chip carrier of the present invention. FIG. 2 is a cross-sectional view of one embodiment. DESCRIPTION OF SYMBOLS 1... Electrode metallized layer, 2... Lid m material, 3... Wall member, 4... Stitch land conductor part, 5... ...Semiconductor integrated circuit element, 6
...Bottom member, 7...Gold wire, 8...
...Solder, 9...Lid member, 10...
Metallized layer, 11... Conductor portion, 12...
...Resistor. Agent Patent Attorney So Uchihara

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を載置する容器基板と、前記容器基板上に前
記半導体素子を囲むように配置された壁部材と、壁部材
上に載置された蓋部材と、前記容器基板と壁部材と蓋部
材との側面に形成された外部接続用電極メタライズ層と
、前記容器基板と前記壁部材との間を貫通して前記電極
メタライズ層に達する配線メタライズ層と、前記蓋部材
上に形成され前記電極メタライズ層の所定のものと接続
された膜回路網とを有する仁とを特徴とする半導体装置
。a container substrate on which a semiconductor element is placed; a wall member disposed on the container substrate so as to surround the semiconductor element; a lid member placed on the wall member; the container substrate, the wall member, and the lid member. an electrode metallized layer for external connection formed on the side surface of the container substrate, a wiring metallized layer penetrating between the container substrate and the wall member and reaching the electrode metallized layer, and a wiring metallized layer formed on the lid member and the electrode metallized layer. What is claimed is: 1. A semiconductor device comprising a layer having a membrane network connected to a predetermined number of layers.
JP59014871A 1984-01-30 1984-01-30 Semiconductor device Pending JPS60160146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59014871A JPS60160146A (en) 1984-01-30 1984-01-30 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59014871A JPS60160146A (en) 1984-01-30 1984-01-30 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS60160146A true JPS60160146A (en) 1985-08-21

Family

ID=11873077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59014871A Pending JPS60160146A (en) 1984-01-30 1984-01-30 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60160146A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477081A (en) * 1991-03-29 1995-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package
US7429501B1 (en) * 2003-08-25 2008-09-30 Xilinx, Inc. Lid and method of employing a lid on an integrated circuit
US8362609B1 (en) 2009-10-27 2013-01-29 Xilinx, Inc. Integrated circuit package and method of forming an integrated circuit package

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477081A (en) * 1991-03-29 1995-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package
US7429501B1 (en) * 2003-08-25 2008-09-30 Xilinx, Inc. Lid and method of employing a lid on an integrated circuit
US8362609B1 (en) 2009-10-27 2013-01-29 Xilinx, Inc. Integrated circuit package and method of forming an integrated circuit package

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