JPS60241228A - Semiconductor chip - Google Patents
Semiconductor chipInfo
- Publication number
- JPS60241228A JPS60241228A JP59096552A JP9655284A JPS60241228A JP S60241228 A JPS60241228 A JP S60241228A JP 59096552 A JP59096552 A JP 59096552A JP 9655284 A JP9655284 A JP 9655284A JP S60241228 A JPS60241228 A JP S60241228A
- Authority
- JP
- Japan
- Prior art keywords
- solder bumps
- chip
- semiconductor chip
- solder
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体装置に関し、特に半導体チップさらＫ
は複数の半導体チップを立体的に接続可能とし、高密度
実装を実現できる技術に関する。[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, and particularly to a semiconductor chip.
relates to technology that enables multiple semiconductor chips to be connected three-dimensionally and achieves high-density packaging.
半導体チップの実装基板へのポンディング方式の一つに
７リツプチツプボンデイング法がある。One of the methods of bonding a semiconductor chip to a mounting board is the 7-lip chip bonding method.
この方法はワイヤを用いないで直接半導体チップ（ヘレ
ット）を基板にフェイスダウンでボンディングする方法
やあり、この方法における半導体チップには、一般に、
ガラス膜などの保護膜で、デバイス表面を保獲し、その
電極部処例えば５０〜１００μの高さのバンプ（突起電
極）が形成された素子が使用され、このバンプの形成に
は、例えば、ＣｕボールやＣｕメッキでもつ上げた上に
半田（Ｐｂ−８ｎ）コートしたり、直接半田でもつ上げ
るなどの方法がとられる。バンプ電極を有する半導抹チ
ップは、上記電極面を下鳴して、予備半凪付された基板
のタンケクステンＷなどから成る場体層に位置合せして
直接押しつけ熱を加えて溶着させる。この方式により基
板上に多数の半導体チップを搭載することができ、いわ
ゆるマルチチップ実装が可能となるが、従来のかかる方
式における半導体チップには半田バンプが一面（上面）
ＶＣシか形成されていないので、あくまでも平面実装に
限られることになる。（フリップチップ方式については
、たとえば工業調査会発行、「ＩＣ化実装技術」の８１
Ｐに示されている。）〔発明の目的〕
本発明は半導体チップの高密度実装を実現することを目
的としたものである。This method involves directly bonding a semiconductor chip (heret) to a substrate face-down without using wires, and the semiconductor chip in this method generally includes:
An element is used in which the device surface is protected with a protective film such as a glass film, and bumps (protruding electrodes) with a height of, for example, 50 to 100 μm are formed on the electrode portions. Methods such as applying a Cu ball or Cu plating and then coating it with solder (Pb-8n), or directly applying solder are used. The semiconductor chip having bump electrodes is aligned with the field layer made of tanxen W or the like of the pre-semi-tempered substrate by lowering the electrode surface, and is directly pressed and welded by applying heat. This method allows a large number of semiconductor chips to be mounted on the board, making so-called multi-chip mounting possible, but in the conventional method, the semiconductor chip has only one surface (top surface) of solder bumps.
Since no VC film is formed, it is limited to flat surface mounting. (For the flip-chip method, see 81 of ``IC Mounting Technology'' published by Kogyo Kenkyukai, for example.
It is shown in P. ) [Object of the Invention] The object of the present invention is to realize high-density packaging of semiconductor chips.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および雄図面からあきらかになるであろ
う、
〔発明の概要〕
本願において開示される発明のうち代表的なものの概要
を簡単忙説明すれば、下記のとおりである。The above and other objects and novel features of the present invention include:
[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows, which will become clear from the description of this specification and the drawings.
すなわち、本発明では、例えば半田バンプを半導体チッ
プの上面だけでなく、側面又は（及び）下面にも具備さ
せることにより、半導体チップ同志を自由につなぎ合わ
せることができ、又三次元的な構成も可能とし、前記目
的を達成したものである。That is, in the present invention, for example, by providing solder bumps not only on the top surface of the semiconductor chip but also on the side surfaces and/or the bottom surface, semiconductor chips can be freely connected to each other, and a three-dimensional configuration can also be realized. This has enabled the above objectives to be achieved.
〔実施例］ 次に、本発明の実施例を図面に基づいて説明する。〔Example] Next, embodiments of the present invention will be described based on the drawings.
第１図は、半田バンプをベレットの上面すなわち、半導
体素子が形成されている側の基板表面上だけでなく、下
面すなわち前記上面に平行な半導体基板の他の表面（裏
面）上にも備えて成る本発明半導体チップの断面を示し
、第１図にて、１は半導体チップで四角形状の上面、下
面及び四側面より成るベレット２の上面に６個の半田バ
ンプ３が形成されているだけでなく、下面にも同数の半
田バンプ４が形成されている。In FIG. 1, solder bumps are provided not only on the top surface of the pellet, that is, the surface of the substrate on which the semiconductor element is formed, but also on the bottom surface, that is, the other surface (back surface) of the semiconductor substrate parallel to the top surface. In FIG. 1, reference numeral 1 denotes a semiconductor chip, and only six solder bumps 3 are formed on the upper surface of a pellet 2 consisting of a rectangular upper surface, lower surface, and four side surfaces. The same number of solder bumps 4 are also formed on the bottom surface.
第２図は、第１図Ａ部の詳細断面図で、第２図にて、５
は半田（Ｐｂ−８ｕ）パッド、６は金（Ａｕ）メッキ層
、７は銅（Ｃｕ）メッキ層、８はクロム（Ｃｒ）層、９
はガラス膜で例示されるデバイス表面保護膜、１０はア
ルミニウム（Ａｌ）■極配線、１１はＳ ｉｏ２膜など
の熱酸化膜で例示される絶縁膜、１２は半導体基板であ
る。このバンプの形成は、例えば第２図に示すように、
Ａｌ電極配線１０上に、バリア金属（ＣｒＪｉ８−Ｃｕ
層７−Ａｕ層６）を介して半球状に半田をコートすれば
よい。又バンプの形成は、内部配線を形成したウェハに
ガラス膜あるいにＳｉｎ、膜を被覆し、ホトレジスト技
術で電極用窓をあけ、次いで、ＣｒあるいはＴｉを接着
用金属として薄く蒸着し。Figure 2 is a detailed sectional view of part A in Figure 1.
is a solder (Pb-8u) pad, 6 is a gold (Au) plating layer, 7 is a copper (Cu) plating layer, 8 is a chromium (Cr) layer, 9
1 is a device surface protection film exemplified by a glass film, 10 is an aluminum (Al) electrode wiring, 11 is an insulating film exemplified by a thermal oxide film such as an Sio2 film, and 12 is a semiconductor substrate. The formation of this bump is, for example, as shown in FIG.
A barrier metal (CrJi8-Cu
Solder may be coated in a hemispherical manner through layer 7--Au layer 6). To form bumps, a wafer on which internal wiring has been formed is coated with a glass film or a Sin film, windows for electrodes are opened using photoresist technology, and then Cr or Ti is thinly vapor-deposited as an adhesive metal.
た後、バンプ金属を付着し、バンプ部分を残してエツチ
ング除去して形成してもよく、その他各種方法が可能で
ある。After that, bump metal may be attached and removed by etching leaving the bump portion, or various other methods are possible.
第１図にて、半田バンプ３は図示していないが前述のご
とくＡｌ電極配線１０と電気的に接続され、さらに、上
面の半田バンプ３は図示していないがチップ内部で、下
面の半田バンプ４と電気的に接続することができる。本
発明では半田バンプなチップの上面及び下面のみならず
、側面にも有していてもよい。第３図はこの実施例を示
す平面図、第４図は半田バングを上面、下向及び仙１面
にイ６Ｎえて成る本発明半導体チップの一例を示す拡大
側面図である、これら図において、１３は側面に形成さ
れた半田バンプであり、金属膜１４により上面半田バン
プ３及び下面半田バンプ４と接続している。第５図は、
本発明半導体チップを複数その半田バンプな介して連結
して、三元的伯成と成したセ１１を示し、三元的に構成
された当該チップを実装基板に実装して成る例を示す。In FIG. 1, the solder bumps 3 (not shown) are electrically connected to the Al electrode wiring 10 as described above, and the solder bumps 3 on the top surface are connected inside the chip (not shown) to the solder bumps on the bottom surface. 4 can be electrically connected. In the present invention, solder bumps may be provided not only on the top and bottom surfaces of the chip but also on the side surfaces. FIG. 3 is a plan view showing this embodiment, and FIG. 4 is an enlarged side view showing an example of a semiconductor chip of the present invention having solder bangs on the top, bottom, and side surfaces. Reference numeral 13 denotes a solder bump formed on the side surface, and is connected to the upper solder bump 3 and the lower solder bump 4 through a metal film 14. Figure 5 shows
A cell 11 is shown in which a plurality of semiconductor chips of the present invention are connected via their solder bumps to form a ternary structure, and an example is shown in which the ternary-structured chips are mounted on a mounting board.
第５図にて、】５は実装基板で、例えばセラミック基板
やプリント基板により構成され、この実装基板１５上に
形成された金属導体部（図示せず）と半導体チップの半
田バンプとを位置合せして熱溶着させである。実装基板
１５にはその裏面に複数の外部ビン１６が突出形成され
ており、半導体チップの内部配線は前記導体部を介し５
て外部ビン１６に電気的に接続している。実装基板１５
上に搭載された半導体チップは、四個の当該チップによ
りサイコロ状に連結されたチップ部１７と、該チップ部
１７と連結したＬ字形状のチップｓ１８と前記チップ部
と連結したチップ部１９と該チップ部と連結したチップ
部２０とから成っている例を示す。In FIG. 5, reference numeral 5 denotes a mounting board, which is made of, for example, a ceramic board or a printed circuit board, and the metal conductor portion (not shown) formed on this mounting board 15 is aligned with the solder bumps of the semiconductor chip. It is then heat welded. A plurality of external bins 16 are formed protrudingly on the back surface of the mounting board 15, and the internal wiring of the semiconductor chip is connected to the 5 via the conductor part.
and is electrically connected to the external bin 16. Mounting board 15
The semiconductor chips mounted on the top include a chip part 17 connected in a dice shape by four chips, an L-shaped chip s18 connected to the chip part 17, and a chip part 19 connected to the chip part. An example is shown in which the chip part 20 is connected to the chip part.
本発明半導体チップを構成するデバイス１２は、例えば
シリコン単結晶基板より、周知の技術によって、このデ
バイス内には多数の回路素子が形成され、１つの回路機
能を与えている、回路素子は、例えばＣＭＯ８から成り
、これらの回路素子によって、例えば論理回路やメモリ
回路などの回路機能が形成される。The device 12 constituting the semiconductor chip of the present invention has a large number of circuit elements formed therein using well-known techniques using, for example, a silicon single crystal substrate, and provides one circuit function. It consists of CMO8, and circuit functions such as a logic circuit and a memory circuit are formed by these circuit elements.
半導体チップにその上面のみならず他の面にも半田バン
プが形成されているので、半田バンプを介して複数の半
導体チップ同志を自由に連結することが可能であり、又
、半導体チップの三次元的な実装、畠密度実装が可能で
ある。Since solder bumps are formed on the semiconductor chip not only on its top surface but also on other surfaces, it is possible to freely connect multiple semiconductor chips to each other via the solder bumps, and it is also possible to connect the semiconductor chips three-dimensionally. It is possible to perform high-density mounting and high-density mounting.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例圧限定される
ものではなく、その要旨を逸脱しない範囲で種々変史Ｌ
ＩＩＴ能であることはいう丈でもない。たとえば半田バ
ンプはチップ側面あるいは下面にのみ、設けてもよい。Although the invention made by the present inventor has been specifically explained based on examples, the present invention is not limited to the above examples, and can be modified in various ways without departing from the gist of the invention.
It is not enough to be an IIT Noh student. For example, solder bumps may be provided only on the side or bottom surface of the chip.
チップの側面九のみ奴け、これを周知のセラミックパッ
ケージのキャビティ内に固着し、側面のバンプとキャビ
ティ内側壁のインナーリードとを接続し、ワイヤボンデ
ィングを省略することもできる。また、前記実施例では
半田バンプを形成する例を示したが、チップ面から突出
した導電体であれば、他の金属ボールのごときものでも
よく、上面及び下面に半田バンプを形成し、側面にＡｇ
ペーストのごとき導電性接着剤により導電体を形成して
もよい。又、本発明においては半導体チップを半田バン
プを介して積層し、立体的に構成することができる。It is also possible to omit wire bonding by fixing only the side surfaces of the chip in the cavity of a well-known ceramic package and connecting the bumps on the side surfaces to the inner leads on the inner wall of the cavity. Further, in the above embodiment, an example was shown in which solder bumps were formed, but any other conductor such as a metal ball may be used as long as it is a conductor that protrudes from the chip surface.Solder bumps are formed on the top and bottom surfaces, and Ag
The conductor may be formed using a conductive adhesive such as a paste. Further, in the present invention, semiconductor chips can be stacked via solder bumps to form a three-dimensional structure.
本発明半導体チップは、広くマルチチップ実装分野に応
用することができる、The semiconductor chip of the present invention can be widely applied to the field of multi-chip packaging.
図面は本発明の実施例を示し、
第１図は本発明の実施例を示す断面図、第２図は第１図
Ａ部の詳細を示す拡大断面図、第３図は本発明の他の実
施例を示す平面図、第４図は本発明の他の実施例を示す
側面図、第５図は本発明半導体チップを実装して成る半
導体装置の斜視図である。
−１・・・半導体チップ、２・・・ペレット、３・・・
半田バンプ（上面）、４・・・半田パンダ（下面）、５
・・・半田パッド、６７Ａｕ 層、７−Ｃｕ１ｆｌｔ、
８−Ｃｒ１ｆ！、９・・・デバイス表面保眼膜、１０・
・・ｉ電極配線、Ｊｌ・・・絶縁ＩｉＱ、】２・・・半
導体デバイス、１３・・・半田バンプ（側面）、１４・
・・金属膜、１５・・・実装淋板、１６・・・外部ピン
、１７・・・チップ部、１８・・・チップ部、１９・・
・チップ部、２０・・・チップ部。
第 １ 図
ブ
第 ２ 図
？The drawings show an embodiment of the present invention, FIG. 1 is a sectional view showing an embodiment of the invention, FIG. 2 is an enlarged sectional view showing details of part A in FIG. FIG. 4 is a plan view showing an embodiment of the present invention, FIG. 4 is a side view showing another embodiment of the present invention, and FIG. 5 is a perspective view of a semiconductor device in which a semiconductor chip of the present invention is mounted. -1...Semiconductor chip, 2...Pellet, 3...
Solder bump (top), 4...Solder panda (bottom), 5
...Solder pad, 67Au layer, 7-Cu1flt,
8-Cr1f! , 9...Device surface eye protection film, 10.
... i-electrode wiring, Jl... insulation IiQ, ]2... semiconductor device, 13... solder bump (side), 14.
... Metal film, 15... Mounting board, 16... External pin, 17... Chip part, 18... Chip part, 19...
- Chip part, 20... Chip part. Figure 1, Figure 2?
Claims (1)
の面のうち少なくとも二面に、突出した導電体を形成し
て成る、二以上の半導体チップ同志を立体的に連結する
ことのできる半導体チップ。 ２゜突出した導体部がバンプである、特許請求の範囲第
１項記載の半導体チップ。[Claims] 1. Three-dimensionally connecting two or more semiconductor chips by forming protruding conductors on at least two of the surfaces of a semiconductor chip having an upper surface, a lower surface, and side surfaces. A semiconductor chip that can The semiconductor chip according to claim 1, wherein the conductor portion protruding by 2° is a bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59096552A JPS60241228A (en) | 1984-05-16 | 1984-05-16 | Semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59096552A JPS60241228A (en) | 1984-05-16 | 1984-05-16 | Semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60241228A true JPS60241228A (en) | 1985-11-30 |
Family
ID=14168235
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59096552A Pending JPS60241228A (en) | 1984-05-16 | 1984-05-16 | Semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60241228A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5533664A (en) * | 1993-09-07 | 1996-07-09 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
| US5606198A (en) * | 1993-10-13 | 1997-02-25 | Yamaha Corporation | Semiconductor chip with electrodes on side surface |
| US5636104A (en) * | 1995-05-31 | 1997-06-03 | Samsung Electronics Co., Ltd. | Printed circuit board having solder ball mounting groove pads and a ball grid array package using such a board |
| US5907786A (en) * | 1992-11-11 | 1999-05-25 | Mitsubishi Denki Kabushiki Kaisha | Process for manufacturing a flip-chip integrated circuit |
| JP2009200173A (en) * | 2008-02-20 | 2009-09-03 | Nec Access Technica Ltd | Semiconductor package |
| US8227700B2 (en) | 2008-06-13 | 2012-07-24 | Samsung Electronics Co., Ltd. | Chip having side protection terminal and package using the chip |
-
1984
- 1984-05-16 JP JP59096552A patent/JPS60241228A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5907786A (en) * | 1992-11-11 | 1999-05-25 | Mitsubishi Denki Kabushiki Kaisha | Process for manufacturing a flip-chip integrated circuit |
| US6204566B1 (en) | 1992-11-11 | 2001-03-20 | Mitsubishi Denki Kabushiki Kaisha | Resin encapsulated electrode structure of a semiconductor device, mounted semiconductor devices, and semiconductor wafer including multiple electrode structures |
| US6284554B1 (en) | 1992-11-11 | 2001-09-04 | Mitsubishi Denki Kabushiki Kaisha | Process for manufacturing a flip-chip integrated circuit |
| US6469397B2 (en) | 1992-11-11 | 2002-10-22 | Mitsubishi Denki Kabushiki Kaisha | Resin encapsulated electrode structure of a semiconductor device, mounted semiconductor devices, and semiconductor wafer including multiple electrode structures |
| US5533664A (en) * | 1993-09-07 | 1996-07-09 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device |
| US5606198A (en) * | 1993-10-13 | 1997-02-25 | Yamaha Corporation | Semiconductor chip with electrodes on side surface |
| US5636104A (en) * | 1995-05-31 | 1997-06-03 | Samsung Electronics Co., Ltd. | Printed circuit board having solder ball mounting groove pads and a ball grid array package using such a board |
| JP2009200173A (en) * | 2008-02-20 | 2009-09-03 | Nec Access Technica Ltd | Semiconductor package |
| JP4701445B2 (en) * | 2008-02-20 | 2011-06-15 | Ｎｅｃアクセステクニカ株式会社 | Semiconductor package |
| US8227700B2 (en) | 2008-06-13 | 2012-07-24 | Samsung Electronics Co., Ltd. | Chip having side protection terminal and package using the chip |
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