JPH05211257A - Mounting method of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To mount a high-speed semiconductor integrated circuit with high density and at a low cost by using a silicon substrate as a circuit substrate and by directly mounting a VLSI chip on its main surface and radiating fins on the rear. CONSTITUTION:A VLSI chip 3 is adhered to the main surface of a silicon substrate 1 directly via an alloy layer 4. Bumps 5 and bumps 6 are formed on the VLSI chip 3 and a microwiring layer 2, respectively; and both are connected with TAB leads 7. A cap 8 is adhered and fixed by an adhesion 9, and the VLSI chip 3 and others are hermetically sealed. The periphery of the silicon substrate 1 is provided with bumps 10, and TAB leads 11 are connected as lead drawn outside. A TAB tape base material is provided as a lead reinforcing layer 12. Radiating fins 3 are adhered on the rear of the silicon substrate 1 with a thermal grease 14 of high thermal conductivity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor integrated circuit, and more particularly to providing a method for mounting a high speed semiconductor integrated circuit at a high density and at a low price.

[0002]

2. Description of the Related Art Conventionally, as a mounting method to which the present invention is applied, a 39th ECC (Electronic Components Conference, Elec) held in May 1989 was used.
tronics Components Conference
ence), that is, the implementation shown in FIG. 7, and the IEE spectrum (I)
EEE Spectrum) March 1990 cover and paper "Multi-chip Modules: Next Generation Packages (next)
t-generation Packages. ) ”, That is, the implementation shown in FIG. 8 is known.

In the mounting shown in FIG. 7, a ceramic multilayer substrate 27 is used.
A fine wiring layer 2 made of polyimide / metal multi-layer wiring is formed on the main surface of, and a plurality of VLSI chips 3 are formed on the surface.
Are die-bonded with the alloy layer 4. The electrical connection between the VLSI chip 3 and the fine wiring layer 2 is made by the wire 15 by the wire bonding method. The cap 8 and the grid array lead pins 23 are attached to the main surface side of the ceramic multilayer substrate 27. A metal 28 for heat radiation is embedded in the fine wiring layer 2. A radiation fin 13 is attached to the opposite surface side with a thermal grease 14.

In the mounting shown in FIG. 8, a silicon substrate 1 is used, and a plurality of VLSI chips 3 are formed on the main surface of the silicon substrate 1 by means of an alloy layer 4.
It is die-bonding with. The fine wiring layer 2 is formed in a place other than the VLSI chip 3 mounting portion. VL
The wire 15 is provided between the SI chip 3 and the fine wiring layer 2 by a wire bonding method. As shown in FIG. 8, the silicon substrate 1 is fixed to a large package (made of, for example, Kovar) 29 with a mount material 30. The silicon substrate 1 and the extraction lead 31 are connected by a wire 32 by a wire bonding method. The surface of the large package 29 is covered with the cap 8 and sealed by the seam welder method or the like. The heat radiation fins 13 are attached to the back surface side of the large package 29 by thermal grease 14.

In addition to this, the related mounting method is as follows:
Implementation reported in the 37th ECC held in May 987 (CJ Bartlett et al., "Multi-Chi
pPackaging Design for VLS
I-Based Systems ") are known.
That is, a fine wiring layer made of a polyimide / metal multilayer is formed on the main surface of a silicon substrate, and a flip chip is chip-connected thereto. In terms of high density, high speed (low inductance, built-in decoupling capacitance, etc.) and other points, it has basically excellent contents and is a suggestive method for future type mounting. However, in the field targeted by the present invention, the technical barrier cannot be overcome in terms of heat dissipation.

[0006]

The conventional mounting method shown in FIGS. 7 and 8 is called multi-chip packaging (hereinafter referred to as MCP), and is mounted on a printed wiring board by single-chip packaging. It can be said that it is a next-generation type mounting method that has many advantages such as delay time between chips, size, weight, amount of materials used, etc., as compared with the usual method. However, they are still lacking in technical problems as described below.

First, in the mounting method of FIG. 7, a fine wiring layer 2 is formed by a polyimide / metal multilayer wiring technique, and VLS is applied.
The short connection between the I chips 3 and the local sealing of only the periphery of the VLSI chip 3 with the cap 8 are excellent, but the heat dissipation surface is a problem. In the MCP, since the mounting density is increased, the heat generation density is higher than that in single chip packaging using a printed wiring board (PWB) as shown in FIG. 9, for example, and the heat dissipation surface is important.

As can be seen from FIG. 9, the heat generation density is rapidly increasing year by year, and the technical breakthrough of the heat radiation surface has become a basic technical problem for the MCP.

The main heat dissipation path of the mounting method shown in FIG. 7 is VL.
SI chip 3 → alloy layer 4 → metal 28 → ceramic multilayer substrate 27 → thermal grease 14 → radiating fin 13. Here, the metal 28 for heat dissipation is formed on the polyimide layer having a poor thermal conductivity, but since it is embedded in the polyimide layer, the back surface area ratio of the chip does not greatly exceed 50%. Further, the ceramic that can be easily manufactured by the green sheet method here is so-called alumina, and its thermal conductivity is poor at about 20 W / m · k. From these points, the mounting method of FIG. 7 has low heat dissipation capability.

Next, in the mounting method of FIG. 8, the ceramic portion of FIG. 7 is made into a silicon substrate 1 having a high thermal conductivity of up to 150 w / m · k, and the back surface of the VLSI chip 3 is directly bonded to the silicon substrate by the alloy layer 4. The point of die-bonding to 1 improves the heat dissipation surface. However, since the mechanical strength of the silicon substrate 1 is insufficient, the mounting material 30 is bonded to the large package 29. Compared to the single packaging package, this large package 29 is extremely large, and the present package manufacturing technology can only manufacture a Kovar material with gold plating and hermetically extracting the lead or a ceramic package. Absent. Both of them are expensive, and are currently more expensive than the portion of the silicon substrate 1 on which the VLSI chip 3 is mounted.

The silicon substrate 1 has a plane size of 40 to 12
It is a problem to be solved that a large-sized package of high price is required to mechanically reinforce against the stress in the cross-sectional direction with a shape of 0 mm □ and a thickness of about 1 mm. In the mounting method of FIG. 8, what is required to seal only the VLSI chip 3 and its periphery is sealed as a whole. This makes sealing difficult and unnecessarily makes the package expensive. This point is also a problem to be solved.

[0012]

In the mounting method according to the present invention, a silicon substrate having excellent thermal conductivity, surface flatness, thermal expansion coefficient matching, and price is used as a circuit substrate.
The silicon substrate is directly attached to the cooling fins for mechanical reinforcement. The VLSI chip is directly die-bonded to the silicon substrate, and the heat dissipation path from the chip to the cooling fin has a low thermal resistance.

Only the VLSI chip and its peripheral portion are hermetically sealed. A TAB (tape automated bonding) method is used for pulling out the leads from the silicon substrate to the outside, which is suitable for surface mounting.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention. 2 and 3 are a top view and a bottom view of FIG. 1, respectively.

FIG. 1 shows the following configuration. That is, the fine wiring layer 2 is formed on the main surface of the silicon substrate 1 by the multilayer wiring technique of polyimide / metal or SiO ₂ / metal. It is not formed in a predetermined portion corresponding to the VLSI chip 3. Therefore, VLS
The I-chip 3 is directly bonded to the silicon substrate 1 via the alloy layer 4. The reason why the alloy layer 4 is selected here is to suppress the thermal resistance of the bonded portion to be low. V
Bumps 5 and bumps 6 are formed on the LSI chip 3 and the fine wiring layer 2, respectively, and both are formed on TAB (Tape Automated Bonding: Tape Au).
The lead 7 of the tomated bonding is connected. A cap 8 for covering the VLSI chip 3, the bumps 5, the leads 7, the bumps 6 and the fine wiring layer 2 is provided. It is glued and fixed by adhesive 9 and VLS
The I-chip 3 and others are sealed.

Bumps 1 are formed on the periphery of the silicon substrate 1.
0 is provided, and the TAB lead 11 is connected as an external lead. A tape base material of TAB is provided as the reinforcing layer 12 of the lead.

On the back side of the silicon substrate 1, the heat radiation fin 1 is provided.
3 is bonded by a thermal grease 14 having a high thermal conductivity.

The embodiments of the present invention shown in FIGS. 1, 2 and 3 are as specifically described below. The size of the silicon substrate 1 is 40 mm on a side.
It is a 100 mm square and has a thickness of 0.5 to 1.0 mm. The fine wiring layer is made of polyimide having a thickness of 2 to 15 μm as an interlayer insulating film, and the conductor layer is 1 to 3 μm in thickness and 5 in width.
2 to 5 Cu wiring with a pitch of 10 to 50 μm
It was used after forming a layer. As the VLSI chip 3, a microcomputer, a memory, and a gate array chip manufactured by our company were appropriately selected and used. That is, the size was a square having one side of 10 to 20 mm, the number of I / O (the number of input / output lead terminals) of 200 to 700, and the bonding pad pitch of 80 to 120 μm. VL
The number of SI chips 3 was 4 to 20.

As the alloy layer 4, an Au-Si alloy layer was used. An Au layer and an Au-Si layer were previously metallized on the back surfaces of the silicon substrate 1 and the VLSI chip 3 and alloyed. The alloying was carried out with special consideration to prevent the formation of voids.

Bump 5, bump 6, and bump 10
Are metal bumps formed to a height of 5 to 30 μm by a plating method, and Au, high melting point Pb / Sn, eutectic Pb / S, respectively.
n bumps. The leads 7 and 11 are made of Cu having a thickness of 15 to 35 μm and a width of 40 to 80 μm.
Alternatively, it is a metal lead plated with Sn.

As the cap 8, a cap made of plastic or metal such as Kovar is used. As the adhesive material 9, an epoxy adhesive material was used in the examples.

The radiating fin 13 is made of Al, and a special radiating fin is used which enables high-performance heat radiating by experiment and thermal design simulation of fin thickness and pitch. Although a straight fin type is shown in the drawing, a disc type, a pin array type, and a special type were also used in the embodiments. As the thermal grease 14, a commercially available product having adhesiveness,
Heat resistance, workability, stability, etc. were evaluated and selected before use.

Although the embodiments have been specifically described above, it is needless to say that the embodiments other than those described can be carried out as long as they are suitable for the gist of the present invention.

FIG. 2 is a top view of FIG. FIG. 2 shows one in which four VLSI chips 3 are mounted. The figure shows a state in which the left half portion of the cap 8 is opened. In the figure, four bumps 5, bumps 6 and leads 7 are shown for each chip.
0 is displayed. In addition, the bump 10 and the lead 11
Similarly, although only a part is described for convenience of description, a large number of leads 11 are drawn from four sides.

FIG. 3 is a bottom view of FIG. As in the case of FIG. 2, for convenience of description, only a part of the bump 10 and the lead 11 is shown, but the lead 11 is drawn from four sides. V at the position indicated by the four broken lines
The LSI chip 3 is mounted. Details are not shown in the figure.

FIG. 4 is a sectional view showing a second embodiment of the present invention.

The VLSI chip 3 and the alloy layer 4 are formed on the main surface of the silicon substrate 1 (the fine wiring layer 2 is not shown in the drawing).
It is attached by. The electrical connection between the VLSI chip 3 and the silicon substrate 1 is made by a wire bonding method using Au or Al wires 15. Figure 1
Similarly to the above, the cap 8 is placed so as to locally seal the VLSI chip 3 and its peripheral portion. In this embodiment, the cap 8 has a flat ceiling portion, and is finally fixed to the printed wiring board 17 or the ceramic substrate by the adhesive 16. The bumps 10 of the silicon substrate 1 and the bumps 18 of the printed wiring board 17 are leads 11
Connected by. A heat radiation fin 13 is attached to the back surface side of the silicon substrate 1 with a thermal grease. In this embodiment, an epoxy-based adhesive is used as the adhesive 16, but other materials can be used.

FIG. 5 is a sectional view showing a third embodiment of the present invention. Although it is based on the mounting method described in FIG. 1, it is different in the following points. That is, the base 19 of a pin grid array (PPGA) package made of glass epoxy is attached to the heat radiation fin 13 by the adhesive material 20.

As shown in FIG. 5, the base 19 is perforated so that the silicon substrate 1 can be embedded therein. The bump 10 on the silicon substrate 1 and the bump 21 on the base 19 side
And are electrically connected by a lead 11. Base 19
On the side opposite to the heat radiation fins 13, there are provided grid array pins 23 soldered to the pads 22.

FIG. 6 is a sectional view showing a fourth embodiment of the present invention. In FIG. 6, the portion of the silicon substrate 1 on which the VLSI chip 3 is mounted is extracted and described. After connecting the bumps 5 of the VLSI chip 3 and the bumps 6 of the fine wiring layer 2 by the leads 7, each VLSI chip 3 is coated with the resin 24 by the potting method. Here, the resin 24 is an epoxy resin and is selected from commercial products in consideration of chip protection effect, workability, stability, easiness of automation and the like. After the curing, the protective film 25 is covered on the resin 24, and the peripheral portion is adhered and fixed by the adhesive 9. Protective film 2
The inside of 5 is sealed. A small but partially hollow area 26
(It is exaggerated in FIG. 6 for convenience of explanation)
Exist, and the protective film 25 is flexible and expands or contracts repeatedly due to a temperature change, and can absorb it.

[0032]

As described above, in the present invention, the silicon substrate having the thermal conductivity which is 7 to 8 times larger than that of the conventionally used alumina is used. As a result, the coefficients of thermal expansion can be matched, so that a large VLSI chip can be die-bonded with the alloy layer. Furthermore, the heat dissipation fins are attached directly to the silicon substrate with high thermal conductivity thermal grease. 4.5 ° C /
The internal thermal resistance, which was about W, can be reduced to 1.2 ° C./W or less.

Further, in the present invention, since extremely expensive large ceramic packages and large metal packages are not used, the manufacturing cost is drastically reduced to 1/2 to 1/3.

Further, according to the present invention, it is possible to realize high-performance connection between VLSI chips, as described in the section "Invention" of Table 1 below.

[0035]

Further, according to the present invention, since the sealing area is local, sealing is easy.

[Brief description of drawings]

FIG. 1 is a sectional view showing a mounting method according to a first embodiment of the present invention.

FIG. 2 is a top view of FIG.

FIG. 3 is a bottom view of FIG.

FIG. 4 is a sectional view showing a mounting method according to the second embodiment of the present invention.

FIG. 5 is a sectional view showing a mounting method according to the third embodiment of the present invention.

FIG. 6 is a sectional view showing a mounting method according to a fourth embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a conventional technique.

FIG. 8 is a cross-sectional view showing a conventional technique.

FIG. 9 is a trend diagram of heat generation density showing the technical background of the present invention.

[Explanation of symbols]

 1 Silicon Substrate 2 Fine Wiring Layer 3 VLSI Chip 4 Alloy Layer 5 Bump 6 Bump 7 Lead 8 Cap 9 Adhesive 10 Bump 11 Lead 12 Reinforcing Layer 13 Radiating Fin 14 Thermal Grease 15 Wire 16 Adhesive 17 Printed Wiring Board 18 Bump 19 Base 20 Adhesive Material 21 Bump 22 Pad 23 Pin 24 Resin 25 Protective Film 26 Hollow Area 27 Ceramic Multilayer Substrate 28 Metal 29 Large Package 30 Mounting Material 31 Drawer Lead 32 Wire

Claims (4)

[Claims] 1. A method of mounting a semiconductor integrated circuit, comprising a plurality of VLSI (Very Large Scale Integrated Circuit) chips mounted on a circuit board, wherein a silicon substrate is used as a circuit board, and a VLSI chip is provided on the main surface side. It is attached by an alloy layer, and a fine wiring layer is formed in a portion other than the portion corresponding to the VLSI chip, and the VLSI chip and the fine wiring layer are electrically connected with low inductance, and further, V
A mounting method characterized in that the LSI chip and a peripheral portion thereof are locally sealed by a cap, while a heat radiating fin is attached to the back side of the silicon substrate with thermal grease having high thermal conductivity. 2. The mounting method according to claim 1, wherein V
The LSI chip and the cap that covers the peripheral area are adhesively fixed to the printed wiring board or ceramic substrate with an adhesive, and the silicon substrate side and the printed wiring board or ceramic substrate side are TAB (tape automated bonding). The mounting method characterized by connecting by the method. 3. The mounting method according to claim 1, wherein the multilayer printed wiring board is provided with through holes for embedding a silicon substrate, and pads and pins for electrically connecting to the silicon substrate side are provided on the main surface side. The mounting method is characterized in that the heat radiation fins are attached and the back surface side is adhesively fixed with an adhesive. 4. The mounting method according to claim 1, wherein V
When sealing the LSI chip and its peripheral parts, VL
A mounting method characterized in that an SI chip is coated with a resin in advance and then a flexible film is coated and sealed.