JPH04342162A - Semiconductor integrated circuit device and its package structure - Google Patents
Semiconductor integrated circuit device and its package structureInfo
- Publication number
- JPH04342162A JPH04342162A JP3114509A JP11450991A JPH04342162A JP H04342162 A JPH04342162 A JP H04342162A JP 3114509 A JP3114509 A JP 3114509A JP 11450991 A JP11450991 A JP 11450991A JP H04342162 A JPH04342162 A JP H04342162A
- Authority
- JP
- Japan
- Prior art keywords
- tape carrier
- semiconductor chip
- carrier package
- heat sink
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004382 potting Methods 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 10
- 229920005989 resin Polymers 0.000 claims description 10
- 230000005855 radiation Effects 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 description 12
- 238000000034 method Methods 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229920000647 polyepoxide Polymers 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 229920001225 polyester resin Polymers 0.000 description 1
- 239000004645 polyester resin Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 229920003002 synthetic resin Polymers 0.000 description 1
- 239000000057 synthetic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体集積回路装置に
関し、特に、テープキャリヤパッケージ（Ｔａｐｅ Ｃ
ａｒｒｉｅｒ Ｐａｃｋａｇｅ；ＴＣＰ）の熱抵抗の低
減に適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuit devices, and particularly to tape carrier packages (Tape C
The present invention relates to a technique that is effective when applied to reduce the thermal resistance of carrier packages (TCP).
【０００２】0002
【従来の技術】近年、ポータブル形パソコンやラップト
ップ形パソコンなど、軽量、薄形パーソナルコンピュー
タの普及に伴い、半導体チップを基板に薄く実装するこ
とのできるテープキャリヤパッケージ（ＴＡＢともいう
）が注目されている。[Prior Art] In recent years, with the spread of lightweight and thin personal computers such as portable personal computers and laptop personal computers, tape carrier packages (also referred to as TAB), which allow semiconductor chips to be thinly mounted on substrates, have attracted attention. ing.
【０００３】テープキャリヤパッケージは、半導体チッ
プのボンディングパッド上に形成したＡｕのバンプとポ
リイミド樹脂のフィルムに形成したＣｕリードの一端と
を電気的に接続し、このＣｕリードの他端を実装基板と
電気的に接続する実装方式である。なお、テープキャリ
ヤパッケージについては、例えば特開平１−２１７９３
３号公報などに記載がある。[0003] The tape carrier package electrically connects an Au bump formed on a bonding pad of a semiconductor chip to one end of a Cu lead formed on a polyimide resin film, and connects the other end of this Cu lead to a mounting board. This is a mounting method that connects electrically. Regarding the tape carrier package, for example, Japanese Patent Application Laid-Open No. 1-21793
There is a description in Publication No. 3, etc.
【０００４】0004
【発明が解決しようとする課題】従来、テープキャリヤ
パッケージには、消費電力の少ないＣＭＯＳ ＬＳＩ
などを形成した半導体チップが搭載されていたが、ＬＳ
Ｉの大容量化、高速化に伴ってチップ一個あたりの消費
電力が増大しつつあることから、テープキャリヤパッケ
ージを基板に高密度実装したときの熱抵抗を如何に低減
するかが重要な課題となっている。[Problems to be Solved by the Invention] Conventionally, tape carrier packages have been manufactured using CMOS LSI chips with low power consumption.
It was equipped with a semiconductor chip that formed the LS
As the power consumption per chip is increasing with the increase in capacity and speed of I, an important issue is how to reduce the thermal resistance when tape carrier packages are mounted on a board at high density. It has become.
【０００５】そこで、本発明の目的は、テープキャリヤ
パッケージの熱抵抗を低減することのできる技術を提供
することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a technique that can reduce the thermal resistance of a tape carrier package.
【０００６】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述および添付図面から明らかに
なるであろう。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【０００７】[0007]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下の通りである。[Means for Solving the Problems] Among the inventions disclosed in this application, a brief overview of typical inventions will be as follows.
It is as follows.
【０００８】本発明の半導体集積回路装置は、テープキ
ャリヤパッケージに搭載された半導体チップの素子形成
面上にポッティング樹脂を介して放熱板を接合し、この
テープキャリヤパッケージの所定数を、一のテープキャ
リヤパッケージに搭載された半導体チップの放熱板と他
のテープキャリヤパッケージに搭載された半導体チップ
の背面とが接触するように積層した実装構造を有する。In the semiconductor integrated circuit device of the present invention, a heat sink is bonded to the element forming surface of a semiconductor chip mounted on a tape carrier package via a potting resin, and a predetermined number of tape carrier packages are connected to one tape. It has a mounting structure in which the heat dissipation plate of a semiconductor chip mounted on a carrier package and the back surface of a semiconductor chip mounted on another tape carrier package are stacked so as to be in contact with each other.
【０００９】[0009]
【作用】上記した手段によれば、テープキャリヤパッケ
ージの所定数を、一の半導体チップの放熱板と他の半導
体チップの背面とが接触するように積層することにより
、半導体チップから発生した熱を、半導体チップ−放熱
板−半導体チップ−放熱板・・・からなる熱伝達経路を
通じて外部に逃がすことができるので、テープキャリヤ
パッケージの熱抵抗を低減することができる。[Operation] According to the above-described means, a predetermined number of tape carrier packages are stacked so that the heat sink of one semiconductor chip is in contact with the back surface of another semiconductor chip, thereby dissipating the heat generated from the semiconductor chips. Since the heat can be released to the outside through the heat transfer path consisting of the semiconductor chip, the heat sink, the semiconductor chip, the heat sink, etc., the thermal resistance of the tape carrier package can be reduced.
【００１０】0010
【実施例】図４は、本発明の一実施例であるテープキャ
リヤパッケージ１の全体構成を示す平面図、図５は、こ
のテープキャリヤパッケージ１の要部断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 is a plan view showing the overall structure of a tape carrier package 1 according to an embodiment of the present invention, and FIG. 5 is a sectional view of a main part of this tape carrier package 1.
【００１１】ポリイミド樹脂、ポリエステル樹脂などの
耐熱性合成樹脂からなる絶縁フィルム２の一面には、こ
の絶縁フィルム２に接着されたＣｕ箔をエッチングする
ことによって形成した多数のリード３が設けられている
。このリード３の表面には、Ｓｎメッキまたは半田メッ
キが被着されている。A large number of leads 3 are provided on one surface of the insulating film 2 made of a heat-resistant synthetic resin such as polyimide resin or polyester resin, which are formed by etching Cu foil adhered to the insulating film 2. . The surface of this lead 3 is coated with Sn plating or solder plating.
【００１２】上記リード３の先端（インナーリード部）
は、絶縁フィルム２の中央部に開孔したデバイスホール
４内の半導体チップ５を囲むように配置されており、リ
ード３とチップ５とは、チップ５の素子形成面の周辺部
に設けられたＡｕのバンプ６を介して電気的に接続され
ている。上記チップ５の少なくとも素子形成面は、例え
ばエポキシ系樹脂からなるポッティング樹脂７によって
封止されている。[0012] Tip of the lead 3 (inner lead part)
are arranged to surround the semiconductor chip 5 in the device hole 4 formed in the center of the insulating film 2, and the leads 3 and the chip 5 are arranged around the device forming surface of the chip 5. They are electrically connected via Au bumps 6. At least the element forming surface of the chip 5 is sealed with a potting resin 7 made of, for example, epoxy resin.
【００１３】本実施例のテープキャリヤ１は、上記チッ
プ５の素子形成面上にチップ５よりも一回りサイズの小
さい放熱板８が接合されている。上記放熱板８は、Ｃｕ
やＡｌのような熱伝導率の高い金属板からなり、上記ポ
ッティング樹脂７を介してチップ５に接合されている。In the tape carrier 1 of this embodiment, a heat sink 8, which is one size smaller than the chip 5, is bonded to the element forming surface of the chip 5. The heat sink 8 is made of Cu.
It is made of a metal plate with high thermal conductivity, such as aluminum or aluminum, and is bonded to the chip 5 via the potting resin 7.
【００１４】チップ５に放熱板８を接合するには、イン
ナーリードボンディング工程が完了したチップ５の素子
形成面上にディスペンサなどを用いて液状のポッティン
グ樹脂７を供給した後、その上に放熱板８を載せ、この
状態でポッティング樹脂７を硬化させればよい。放熱板
８は、その上面がチップ５の素子形成面上に被着された
ポッティング樹脂７の上面よりも高くなるように接合す
る。In order to bond the heat sink 8 to the chip 5, liquid potting resin 7 is supplied using a dispenser or the like onto the element formation surface of the chip 5 on which the inner lead bonding process has been completed, and then the heat sink is placed on top of the liquid potting resin 7. 8 and then harden the potting resin 7 in this state. The heat sink 8 is bonded so that its upper surface is higher than the upper surface of the potting resin 7 deposited on the element forming surface of the chip 5.
【００１５】次に、図１〜図３を用いて上記テープキャ
リヤパッケージ１の実装構造を説明する。Next, the mounting structure of the tape carrier package 1 will be explained using FIGS. 1 to 3.
【００１６】テープキャリヤパッケージ１は、従来と同
様、基板９上に一個ずつ実装することも可能であるが、
本実施例では、図１に示すように、その所定数（図では
五個）を積層して実装する。その際、一個のテープキャ
リヤパッケージ１に搭載されたチップ５の背面（または
放熱板８）と、他のテープキャリヤパッケージ１のチッ
プ５に接合された放熱板８（またはチップ５の背面）と
が接触するように積層する。Although the tape carrier packages 1 can be mounted one by one on the substrate 9 as in the conventional case,
In this embodiment, as shown in FIG. 1, a predetermined number (five in the figure) are stacked and mounted. At that time, the back surface of the chip 5 (or the heat sink 8) mounted on one tape carrier package 1 and the heat sink 8 (or the back surface of the chip 5) bonded to the chip 5 of the other tape carrier package 1 are connected. Stack them so that they are in contact.
【００１７】これにより、チップ５−放熱板８−チップ
５−放熱板８・・・からなる熱の伝達経路が形成される
ので、それぞれのテープキャリヤパッケージ１のチップ
５から発生した熱を効率良く外部に逃がすことができる
。このとき、図１に示すように、最上層のテープキャリ
ヤパッケージ１に搭載されたチップ５の背面に放熱フィ
ン１０を接合することにより、それぞれのテープキャリ
ヤパッケージ１のチップ５から発生した熱をこの放熱フ
ィン１０を通じて効率良く外部に逃がすことができる。As a result, a heat transfer path consisting of the chip 5 - heat sink 8 - chip 5 - heat sink 8 . . . is formed, so that the heat generated from the chips 5 of each tape carrier package 1 is efficiently transferred. Can be released to the outside. At this time, as shown in FIG. 1, heat generated from the chips 5 of each tape carrier package 1 is transferred by bonding a heat radiation fin 10 to the back surface of the chip 5 mounted on the uppermost tape carrier package 1. The heat can be efficiently radiated to the outside through the heat dissipation fins 10.
【００１８】また、図１に示すように、基板９上に放熱
板１１を設け、この放熱板１１と最下層のテープキャリ
ヤパッケージ１のチップ５に接合された放熱板８とを接
触させることにより、それぞれのテープキャリヤパッケ
ージ１のチップ５から発生した熱をこの放熱板１１を通
じて効率良く基板９に逃がすこともできる。Furthermore, as shown in FIG. 1, by providing a heat sink 11 on the substrate 9 and bringing this heat sink 11 into contact with the heat sink 8 bonded to the chip 5 of the tape carrier package 1 at the bottom layer, It is also possible to efficiently release heat generated from the chips 5 of each tape carrier package 1 to the substrate 9 through the heat sink 11.
【００１９】図２および図３は、基板９上に実装された
上記テープキャリヤパッケージ１同士の接続方法の一例
である。FIGS. 2 and 3 show an example of a method for connecting the tape carrier packages 1 mounted on the substrate 9 to each other.
【００２０】すなわち、それぞれのテープキャリヤパッ
ケージ１は、四角枠状のキャリヤ基板１２に搭載された
状態で積層される。上記キャリヤ基板１２は、例えばガ
ラス布含浸エポキシ樹脂（ガラエポ）からなり、それら
の周縁部には、例えばＣｕメッキからなる電極１３が所
定の間隔で設けられている。That is, each tape carrier package 1 is stacked while being mounted on a rectangular frame-shaped carrier substrate 12. The carrier substrate 12 is made of, for example, a glass cloth-impregnated epoxy resin (glass-epoxy resin), and electrodes 13 made of, for example, Cu plating are provided at predetermined intervals on the periphery thereof.
【００２１】上記キャリヤ基板１２には、一端が上記電
極１３に接続された図示しない配線が形成されており、
テープキャリヤパッケージ１のリード３のアウターリー
ド部は、この配線の他端側にボンディングされる。テー
プキャリヤパッケージ１同士の電気的接続を行うには、
所定数のキャリヤ基板１２を積層し、上下のキャリヤ基
板１２の電極同士を半田などによって接続すればよい。[0021] On the carrier substrate 12, a wiring (not shown) is formed, one end of which is connected to the electrode 13.
The outer lead portion of the lead 3 of the tape carrier package 1 is bonded to the other end of this wiring. To make electrical connections between tape carrier packages 1,
A predetermined number of carrier substrates 12 may be stacked, and the electrodes of the upper and lower carrier substrates 12 may be connected to each other by soldering or the like.
【００２２】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。[0022] Above, the invention made by the present inventor has been specifically explained based on examples, but the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Needless to say.
【００２３】前記実施例では、チップ５の素子形成面を
下に向けた状態でテープキャリヤパッケージ１を積層し
たが、例えば図６に示すように、チップ５の素子形成面
を上に向けた状態でテープキャリヤパッケージ１を積層
してもよい。In the above embodiment, the tape carrier packages 1 were stacked with the element forming surface of the chip 5 facing downward, but as shown in FIG. 6, for example, the tape carrier package 1 was stacked with the element forming surface of the chip 5 facing upward. The tape carrier packages 1 may be stacked.
【００２４】その際、図に示すように、最上層のテープ
キャリヤパッケージ１に搭載されたチップ５の素子形成
面に放熱板８を接合する手段に代えて放熱フィン１０を
接合してもよい。At this time, as shown in the figure, a heat sink fin 10 may be bonded to the element forming surface of the chip 5 mounted on the uppermost tape carrier package 1 instead of the means for bonding the heat sink 8.
【００２５】前記実施例では、キャリヤ基板の周縁部に
形成した電極を通じてテープキャリヤパッケージ同士を
接続したが、例えばキャリヤ基板にスルーホールを形成
し、このスルーホールを通じてテープキャリヤパッケー
ジ同士を接続するようにしてもよい。In the above embodiment, the tape carrier packages were connected to each other through the electrodes formed on the periphery of the carrier substrate. However, for example, a through hole may be formed in the carrier substrate, and the tape carrier packages may be connected to each other through the through hole. You can.
【００２６】[0026]
【発明の効果】本願によって開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
以下の通りである。[Effects of the Invention] Among the inventions disclosed in this application, the effects obtained by the typical inventions will be briefly explained as follows.
It is as follows.
【００２７】半導体チップの素子形成面上に放熱板を接
合したテープキャリヤパッケージの所定数を、一のテー
プキャリヤパッケージに搭載された半導体チップの放熱
板と他のテープキャリヤパッケージに搭載された半導体
チップの背面とが接触するように積層することにより、
テープキャリヤパッケージの熱抵抗を低減することがで
きるので、その実装密度を向上させることができる。A predetermined number of tape carrier packages each having a heat sink bonded to the element forming surface of the semiconductor chip are arranged between the heat sink of the semiconductor chip mounted on one tape carrier package and the semiconductor chip mounted on the other tape carrier package. By laminating them so that they are in contact with the back side of the
Since the thermal resistance of the tape carrier package can be reduced, its packaging density can be improved.
【図１】本発明の一実施例であるテープキャリヤパッケ
ージの実装構造を示す要部断面図である。FIG. 1 is a sectional view of a main part showing a mounting structure of a tape carrier package according to an embodiment of the present invention.
【図２】このテープキャリヤパッケージを搭載したキャ
リヤ基板の斜視図である。FIG. 2 is a perspective view of a carrier board on which this tape carrier package is mounted.
【図３】このテープキャリヤパッケージの実装構造を示
す斜視図である。FIG. 3 is a perspective view showing the mounting structure of this tape carrier package.
【図４】このテープキャリヤパッケージの全体構成を示
す平面図である。FIG. 4 is a plan view showing the overall configuration of this tape carrier package.
【図５】このテープキャリヤパッケージの要部を示す断
面図である。FIG. 5 is a sectional view showing the main parts of this tape carrier package.
【図６】本発明の他の実施例であるテープキャリヤパッ
ケージの実装構造を示す要部断面図である。FIG. 6 is a sectional view of a main part showing a mounting structure of a tape carrier package according to another embodiment of the present invention.
１ テープキャリヤパッケージ ２ 絶縁フィルム ３ リード ４ デバイスホール ５ 半導体チップ ６ バンプ ７ ポッティング樹脂 ８ 放熱板 ９ 基板 １０ 放熱フィン １１ 放熱板 １２ キャリヤ基板 １３ 電極 1 Tape carrier package 2 Insulating film 3 Lead 4 Device hole 5 Semiconductor chip 6 Bump 7 Potting resin 8 Heat sink 9 Board 10 Heat radiation fin 11 Heat sink 12 Carrier board 13 Electrode
Claims (5)
端と、半導体チップのボンディングパッド上に形成した
バンプとを電気的に接続すると共に、前記半導体チップ
の少なくとも素子形成面をポッティング樹脂により封止
したテープキャリヤパッケージを有する半導体集積回路
装置であって、前記半導体チップの素子形成面上に放熱
板を接合したことを特徴とする半導体集積回路装置。1. One end of a lead formed on an insulating film is electrically connected to a bump formed on a bonding pad of a semiconductor chip, and at least an element forming surface of the semiconductor chip is sealed with a potting resin. 1. A semiconductor integrated circuit device having a tape carrier package, characterized in that a heat sink is bonded to an element forming surface of the semiconductor chip.
プの素子形成面上に放熱板を接合したことを特徴とする
請求項１記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein a heat sink is bonded to the element forming surface of the semiconductor chip using potting resin.
ヤパッケージの所定数を、一のテープキャリヤパッケー
ジに搭載された半導体チップの放熱板と他のテープキャ
リヤパッケージに搭載された半導体チップの背面とが接
触するように積層したことを特徴とする半導体集積回路
装置の実装構造。3. A predetermined number of the tape carrier packages according to claim 1 or 2 are arranged such that the heat sink of the semiconductor chip mounted on one tape carrier package and the back surface of the semiconductor chip mounted on the other tape carrier package are connected to each other. A mounting structure for a semiconductor integrated circuit device, characterized in that the layers are stacked so as to be in contact with each other.
搭載された半導体チップの素子形成面または背面に放熱
フィンを接合したことを特徴とする請求項３記載の半導
体集積回路装置の実装構造。4. The mounting structure for a semiconductor integrated circuit device according to claim 3, wherein a radiation fin is bonded to an element forming surface or a back surface of the semiconductor chip mounted on the uppermost tape carrier package.
ウターリード部を前記絶縁フィルムを囲む枠状のキャリ
ヤ基板の配線と電気的に接続すると共に、前記キャリヤ
基板の一部に前記配線と電気的に接続された電極または
スルーホールを設け、前記電極またはスルーホールを通
じてテープキャリヤパッケージ同士を電気的に接続した
ことを特徴とする請求項３または４記載の半導体集積回
路装置の実装構造。5. The outer lead portion of the lead formed on the insulating film is electrically connected to the wiring of a frame-shaped carrier board surrounding the insulating film, and a part of the carrier board is electrically connected to the wiring. 5. The mounting structure for a semiconductor integrated circuit device according to claim 3, wherein connected electrodes or through holes are provided, and the tape carrier packages are electrically connected to each other through the electrodes or through holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3114509A JPH04342162A (en) | 1991-05-20 | 1991-05-20 | Semiconductor integrated circuit device and its package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3114509A JPH04342162A (en) | 1991-05-20 | 1991-05-20 | Semiconductor integrated circuit device and its package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04342162A true JPH04342162A (en) | 1992-11-27 |
Family
ID=14639542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3114509A Withdrawn JPH04342162A (en) | 1991-05-20 | 1991-05-20 | Semiconductor integrated circuit device and its package structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04342162A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998025304A1 (en) * | 1996-12-04 | 1998-06-11 | Hitachi, Ltd. | Semiconductor device |
| US6492719B2 (en) | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
| JP2014075537A (en) * | 2012-10-05 | 2014-04-24 | Toyota Motor Corp | Semiconductor device |
-
1991
- 1991-05-20 JP JP3114509A patent/JPH04342162A/en not_active Withdrawn
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998025304A1 (en) * | 1996-12-04 | 1998-06-11 | Hitachi, Ltd. | Semiconductor device |
| US6335565B1 (en) | 1996-12-04 | 2002-01-01 | Hitachi, Ltd. | Semiconductor device |
| US6611012B2 (en) | 1996-12-04 | 2003-08-26 | Hitachi, Ltd. | Semiconductor device |
| US7138722B2 (en) | 1996-12-04 | 2006-11-21 | Renesas Technology Corp. | Semiconductor device |
| US6492719B2 (en) | 1999-07-30 | 2002-12-10 | Hitachi, Ltd. | Semiconductor device |
| US6630731B2 (en) | 1999-07-30 | 2003-10-07 | Hitachi, Ltd. | Semiconductor device |
| US6900074B2 (en) | 1999-07-30 | 2005-05-31 | Renesas Technology Corp. | Method of manufacturing a semiconductor device having plural semiconductor chips, wherein electrodes of the semiconductor chips are electrically connected together via wiring substrates of the semiconductor chips |
| JP2014075537A (en) * | 2012-10-05 | 2014-04-24 | Toyota Motor Corp | Semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980806 |