JPH11121641A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH11121641A
JPH11121641A JP27593397A JP27593397A JPH11121641A JP H11121641 A JPH11121641 A JP H11121641A JP 27593397 A JP27593397 A JP 27593397A JP 27593397 A JP27593397 A JP 27593397A JP H11121641 A JPH11121641 A JP H11121641A
Authority
JP
Japan
Prior art keywords
substrate
wiring
semiconductor chip
semiconductor device
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27593397A
Other languages
Japanese (ja)
Other versions
JP3061014B2 (en
Inventor
Futoshi Hosoya
太 細谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27593397A priority Critical patent/JP3061014B2/en
Publication of JPH11121641A publication Critical patent/JPH11121641A/en
Application granted granted Critical
Publication of JP3061014B2 publication Critical patent/JP3061014B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3442Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To make a semiconductor device very thin and to provide a satisfactory connection to a mounting board or the like, by providing a semiconductor device with a substantially flat back surface including a semiconductor chip, a sealed resin and externally connecting electrodes. SOLUTION: A semiconductor device has a substrate 1 having on its back a recessed cavity 1a, interconnections 2 provided on the surface of the substrate 1 and on the bottom of the cavity 1a, a semiconductor chip 3 electrically connected to the electrodes of the interconnections 2 by facedown bonding, add a sealed resin 4 for sealing the periphery of the chip 3 inserted into the cavity 1a of the substrate 1. The device also has externally connecting electrodes 5 and electronic parts 6. The electrodes 5 provided on side surfaces of the substrate 1 are electrically connected to the interconnection 2. The parts 6 are electrically connected to the interconnection 2 provided on the surface of the substrate 1. The back surface of the semiconductor device is formed into a substantially flat surface formed of the substrate l, the semiconductor chip 3, the sealed resin 4, and the externally connecting electrodes 5. As a result of this construction, an extremely thin semiconductor device can be achieved, and hence electronic equipment and the like can be downsized and reduced in weight.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法に関し、特に、リードレスチップキャリア
(LCC)型の半導体装置及びその製造方法に関する。
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a leadless chip carrier (LCC) type semiconductor device and a method of manufacturing the same.

【0002】[0002]

【従来の技術】従来のLCC型の半導体装置は、例え
ば、特開平9ー8167号公報に開示されている。図6
は、従来の半導体装置を示す縦断面図である。
2. Description of the Related Art A conventional LCC type semiconductor device is disclosed in, for example, JP-A-9-8167. FIG.
1 is a longitudinal sectional view showing a conventional semiconductor device.

【0003】図6に示すように、従来の半導体装置は、
ガラス−エポキシ材等の基体からなり裏面側にキャビテ
ィ21aが形成された基板21と、その基板21の表面
及び基板21のキャビティ21aの底部にそれぞれ設け
られた導体回路パターンからなる配線22と、基板21
の裏面に設けられた裏面電極23と、基板21の側面に
形成され、裏面電極23と配線22とを電気的に接続す
る端面スルーホール電極24と、基板21のキャビティ
21aの底部に固着された半導体チップ25と、その半
導体チップ25のパッドと基板21のキャビティ21a
の底部に形成された配線22の電極とを電気的に接続す
るボンディングワイヤ26と、キャビティ21a内に挿
入され、半導体チップ25を封止する封止樹脂27と、
基板21の表面に設けられた配線22と電気的に接続さ
れた半導体素子、抵抗素子、容量素子等の電子部品28
と、を有する。
As shown in FIG. 6, a conventional semiconductor device is
A substrate 21 made of a base material such as a glass-epoxy material and having a cavity 21a formed on the back surface; a wiring 22 made of a conductive circuit pattern provided on the surface of the substrate 21 and the bottom of the cavity 21a of the substrate 21; 21
Back electrode 23 provided on the back surface of the substrate 21, an end face through-hole electrode 24 formed on the side surface of the substrate 21 and electrically connecting the back electrode 23 and the wiring 22, and fixed to the bottom of the cavity 21a of the substrate 21. Semiconductor chip 25, pads of semiconductor chip 25 and cavity 21a of substrate 21
A bonding wire 26 for electrically connecting the electrodes of the wiring 22 formed at the bottom of the semiconductor chip 25 to a bonding wire 26 for sealing the semiconductor chip 25;
Electronic components 28 such as semiconductor elements, resistance elements, and capacitance elements electrically connected to the wiring 22 provided on the surface of the substrate 21
And

【0004】また、本願発明に関連する従来の技術は、
例えば、特開昭63ー147352号公報、特開平4ー
346250号公報及び実開昭60ー141129号公
報に開示されている。
[0004] Further, the prior art related to the present invention is as follows.
For example, it is disclosed in JP-A-63-147352, JP-A-4-346250 and JP-A-60-141129.

【0005】特開昭63ー147352号公報には、上
面及び底面に配線層及び外部導出用端子を備えスルーホ
ールを介し配線層と外部導出用端子を内部接続するモジ
ュール基板と、そのモジュール基板の端部上に積層さ
れ、モジュール基板と半導体収納容器のキャビティ部を
形成する樹脂ダムと、電極端子と接続するフィルムキャ
リアテープのリードを備えキャビティ部内においてモジ
ュール基板の配線層上にフェイスボンディングされる半
導体チップと、その半導体チップを樹脂ダム内に埋める
封止用樹脂とを含み、フェイスボンディングされる半導
体チップの裏面が樹脂ダム面及び封止樹脂面と共に素子
機能部近くまで研削又は研磨される薄型モジュールが開
示されている。
Japanese Patent Application Laid-Open No. 63-147352 discloses a module substrate having a wiring layer and external lead-out terminals on the top and bottom surfaces and internally connecting the wiring layer and the external lead-out terminals through through holes. A semiconductor laminated on an end and forming a cavity of a module substrate and a semiconductor storage container, and a lead of a film carrier tape connected to an electrode terminal. A semiconductor face-bonded to a wiring layer of the module substrate in the cavity. A thin module including a chip and a sealing resin for filling the semiconductor chip in a resin dam, wherein the back surface of the semiconductor chip to be face-bonded is ground or polished to near the element functional portion together with the resin dam surface and the sealing resin surface. Is disclosed.

【0006】特開平4ー346250号公報には、基板
に形成されたキャビティ内にICチップをフェイスダウ
ンして、ICチップの電極と基板の配線の電極とをバン
プを介して接合し、ICチップの裏面及びキャビティの
側壁とを樹脂で封止した半導体装置が開示されている。
[0006] Japanese Patent Application Laid-Open No. 4-346250 discloses that an IC chip is face-down in a cavity formed in a substrate, and an electrode of the IC chip and an electrode of a wiring of the substrate are joined via bumps. A semiconductor device in which the back surface and the side wall of the cavity are sealed with a resin is disclosed.

【0007】実開昭60ー141129号公報には、チ
ップの外周側面に多数の端子部を有し、その端子部がチ
ップの上面から下面に向かって内側に傾斜しているリー
ドレスチップキャリアの端子構造が開示されている。
Japanese Utility Model Application Laid-Open No. 60-141129 discloses a leadless chip carrier having a large number of terminals on the outer peripheral side surface of the chip, and the terminal portions are inclined inward from the upper surface to the lower surface of the chip. A terminal structure is disclosed.

【0008】[0008]

【発明が解決しようとする課題】図6に示す従来の半導
体装置では、基板21の配線22と半導体チップ25と
がボンディングワイヤ26によって接続されているの
で、ループ状のワイヤ26を封止するための封止樹脂2
7が厚くなり、それに伴って、半導体装置全体が厚くな
る。その結果、電子機器等の小型化・軽量化を図ること
ができないという問題がある。
In the conventional semiconductor device shown in FIG. 6, since the wiring 22 of the substrate 21 and the semiconductor chip 25 are connected by the bonding wires 26, it is necessary to seal the loop-shaped wires 26. Sealing resin 2
7 becomes thicker, and accordingly, the whole semiconductor device becomes thicker. As a result, there is a problem that it is not possible to reduce the size and weight of electronic devices and the like.

【0009】一方、特開昭63ー147352号公報に
は、半導体チップの裏面及び封止樹脂面を削り、略平坦
状に形成する点が開示されているが、外部接続電極を含
む裏面を削り、略平坦状に形成する点は開示されておら
ず、それを示唆する記載もない。
On the other hand, Japanese Patent Application Laid-Open No. 63-147352 discloses that the back surface of a semiconductor chip and a sealing resin surface are shaved to form a substantially flat shape. However, the back surface including external connection electrodes is shaved. However, there is no disclosure of the point of forming a substantially flat shape, and there is no description suggesting this.

【0010】また、特開平4ー346250号公報に
は、半導体チップをフェイスダウンして半導体チップの
電極と配線の電極とを接続する点が開示されているが、
半導体チップ、封止樹脂及び外部接続電極を含む裏面を
略平坦状に形成する点については開示されていない。
Japanese Patent Application Laid-Open No. 4-346250 discloses that a semiconductor chip is face-down and an electrode of the semiconductor chip is connected to an electrode of a wiring.
It does not disclose that the back surface including the semiconductor chip, the sealing resin, and the external connection electrodes is formed in a substantially flat shape.

【0011】さらに、実開昭60ー141129号公報
には、端子部が上面から下面に向かって内側に傾斜して
いる点が開示されているが、端子部の下部は、チップの
下面まで達しておらず、半導体チップ、封止樹脂及び外
部接続電極を含む裏面を略平坦状に形成する点について
は開示されていない。
Further, Japanese Utility Model Laid-Open No. 60-141129 discloses that the terminal portion is inclined inward from the upper surface to the lower surface, but the lower portion of the terminal portion reaches the lower surface of the chip. There is no disclosure of forming a substantially flat back surface including a semiconductor chip, a sealing resin, and external connection electrodes.

【0012】本発明は、上記課題を解決するためになさ
れたものであり、非常に薄く、かつ、実装用のボード等
との接続が良好な半導体装置及びその製造方法を提供す
ることを目的とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device which is very thin and has good connection with a mounting board or the like, and a method of manufacturing the same. I do.

【0013】[0013]

【課題を解決するための手段】本発明の半導体装置は、
裏面側に凹状のキャビティが形成された基板と、その基
板のキャビティの底部に設けられた配線と、その配線の
電極とフェイスダウンして電気的に接続された半導体チ
ップと、基板のキャビティ内に挿入され半導体チップの
周囲を封止する封止樹脂と、配線と電気的に接続された
外部接続電極と、を有し、半導体チップ、封止樹脂及び
外部接続電極を含む略平坦状の裏面を備えていることを
特徴とするものである。
According to the present invention, there is provided a semiconductor device comprising:
A substrate having a concave cavity on the back side, a wiring provided at the bottom of the cavity of the substrate, a semiconductor chip which is electrically connected face down to an electrode of the wiring, and a A sealing resin that is inserted and seals the periphery of the semiconductor chip, and an external connection electrode electrically connected to the wiring, and has a substantially flat back surface including the semiconductor chip, the sealing resin, and the external connection electrode. It is characterized by having.

【0014】本発明の半導体装置は又、裏面側に凹状の
キャビティが形成された基板と、その基板のキャビティ
の底部に設けられた配線と、その配線の電極とフェイス
ダウンして電気的に接続された半導体チップと、基板の
キャビティ内に挿入され半導体チップの周囲を封止する
封止樹脂と、基板の側面に設けられ、配線と電気的に接
続された外部接続電極と、を有し、基板、半導体チッ
プ、封止樹脂及び外部接続電極からなる略平坦状の裏面
を備えていることを特徴とするものである。
The semiconductor device of the present invention also includes a substrate having a concave cavity formed on the back surface, a wiring provided at the bottom of the cavity of the substrate, and a face-down and electrically connected to an electrode of the wiring. Having a semiconductor chip, a sealing resin inserted into a cavity of the substrate and sealing the periphery of the semiconductor chip, and an external connection electrode provided on a side surface of the substrate and electrically connected to wiring, It has a substantially flat back surface comprising a substrate, a semiconductor chip, a sealing resin, and an external connection electrode.

【0015】上記外部接続電極は、基板の表面側から裏
面側に向かって内側に傾斜して設けられるのが好まし
い。
It is preferable that the external connection electrode is provided so as to be inclined inward from the front side to the rear side of the substrate.

【0016】本発明の他の形態の半導体装置は、裏面側
に凹状のキャビティが形成された基板と、その基板のキ
ャビティの底部に設けられた配線と、その配線の電極と
フェイスダウンして電気的に接続された半導体チップ
と、基板のキャビティ内に挿入され半導体チップの周囲
を封止する封止樹脂と、配線と電気的に接続され、基板
の裏面側の周辺部の位置に設けられた略平坦状の外部接
続電極とを有し、半導体チップ、封止樹脂及び外部接続
電極からなる略平坦状の裏面を備えていることを特徴と
するものである。
According to another aspect of the present invention, there is provided a semiconductor device including a substrate having a concave cavity formed on the back surface thereof, a wiring provided at the bottom of the cavity of the substrate, and an electrode which is face-down with the electrode of the wiring. Semiconductor chip, a sealing resin inserted into the cavity of the substrate and sealing the periphery of the semiconductor chip, and electrically connected to the wiring, and provided at a peripheral portion on the back surface side of the substrate. And a substantially flat back surface comprising a semiconductor chip, a sealing resin and an external connection electrode.

【0017】上記半導体チップの電極と基板の配線の電
極とはバンプを介して電気的に接続されることを特徴と
するものである。
The electrodes of the semiconductor chip and the electrodes of the wiring of the substrate are electrically connected via bumps.

【0018】上記基板の表面に設けられた配線と、その
配線と電気的に接続された電子部品とを、さらに有して
もよい。
The semiconductor device may further include a wiring provided on the surface of the substrate, and an electronic component electrically connected to the wiring.

【0019】本発明の半導体装置の製造方法は、(1)
裏面側に凹状のキャビティが形成され、そのキャビティ
の底部に設けられた配線と、その配線と電気的に接続さ
れた外部接続電極とを備えた基板を作る工程と、(2)
前記半導体チップを、前記基板のキャビティの底部に設
けられた配線の電極にフェイスダウンして電気的に接続
する工程と、(3)前記基板のキャビティ内に樹脂を挿
入し、前記半導体チップの周囲を封止する工程と、
(4)前記半導体チップ、封止樹脂及び外部接続電極を
含む裏面を略平坦状に所定の厚さになるまで削る工程
と、を有し、(1)から(4)の順序で行うことを特徴
とするものである。
The method of manufacturing a semiconductor device according to the present invention comprises the steps of (1)
(2) a step of forming a substrate having a concave cavity formed on the back surface side and having a wiring provided at the bottom of the cavity and an external connection electrode electrically connected to the wiring;
A step of electrically connecting the semiconductor chip to a wiring electrode provided at the bottom of the cavity of the substrate by face-down, and (3) inserting a resin into the cavity of the substrate and surrounding the semiconductor chip. Sealing the
(4) a step of shaving the back surface including the semiconductor chip, the sealing resin and the external connection electrodes to a substantially flat shape to a predetermined thickness, and performing the steps in the order of (1) to (4). It is a feature.

【0020】本発明によれば、半導体チップが、基板の
キャビティの底部に設けられた配線の電極とフェイスダ
ウンして電気的に接続されるので、ボンディングワイヤ
を用いた場合に比べ、封止樹脂の高さを非常に低くでき
る。また、半導体装置の裏面は、半導体チップ、封止樹
脂及び外部接続電極を含む略平坦状の面で形成されるの
で、半導体チップの裏面等を回路に影響なく研削するこ
とができるとともに、外部接続電極と実装用のボード等
との接続が良好になる。
According to the present invention, the semiconductor chip is face-down and electrically connected to the electrodes of the wiring provided at the bottom of the cavity of the substrate. Can be very low. Further, since the back surface of the semiconductor device is formed of a substantially flat surface including the semiconductor chip, the sealing resin, and the external connection electrodes, the back surface of the semiconductor chip can be ground without affecting the circuit, and the external connection can be performed. The connection between the electrodes and the mounting board is improved.

【0021】特に、外部接続電極が、基板の表面側から
裏面側に向かって内側に傾斜して設けられる場合、その
端部が半導体装置の裏面に傾斜状に接することになるの
で、実装ボード上に盛られたはんだぺーストと接しやす
くなり、リフローの際に、はんだペーストが外部接続電
極に沿って這い上がるため、良好なはんだ付けが可能と
なる。
In particular, when the external connection electrode is provided to be inclined inward from the front surface side to the rear surface side of the substrate, the end thereof comes into contact with the rear surface of the semiconductor device in an inclined manner, so that the external connection electrode is mounted on the mounting board. The solder paste is easily brought into contact with the solder paste and the solder paste crawls along the external connection electrodes during reflow, so that good soldering is possible.

【0022】[0022]

【発明の実施の形態】以下、本発明の実施の形態につい
て図面を参照して説明する。図1は、本発明の第1の実
施の形態に係る半導体装置を示し、(A)はその縦断面
図、(B)はその側面図である。
Embodiments of the present invention will be described below with reference to the drawings. 1A and 1B show a semiconductor device according to a first embodiment of the present invention, wherein FIG. 1A is a longitudinal sectional view and FIG. 1B is a side view.

【0023】図1に示すように、本発明の第1の実施の
形態に係る半導体装置は、裏面側に凹状のキャビティ1
aが形成された基板1と、その基板1の表面及びキャビ
ティ1aの底部に設けられた配線2と、その配線2の電
極とフェイスダウンして電気的に接続された半導体チッ
プ3と、基板1のキャビティ1a内に挿入され半導体チ
ップ3の周囲を封止する封止樹脂4と、基板1の側面に
設けられ、配線2と電気的に接続された外部接続電極5
と、基板1の表面に設けられた配線2と電気的に接続さ
れた電子部品6と、を有する。
As shown in FIG. 1, the semiconductor device according to the first embodiment of the present invention has a concave cavity 1 on the back side.
a, a wiring 2 provided on the surface of the substrate 1 and at the bottom of the cavity 1a, a semiconductor chip 3 electrically connected face down to electrodes of the wiring 2; A sealing resin 4 inserted into the cavity 1a to seal the periphery of the semiconductor chip 3, and an external connection electrode 5 provided on the side surface of the substrate 1 and electrically connected to the wiring 2.
And an electronic component 6 electrically connected to the wiring 2 provided on the surface of the substrate 1.

【0024】基板1は、例えば、ガラスーエポキシ、ポ
リイミド等の有機系の基材やアルミナ等のセラミックス
の基材で作られる。基板1の厚さは、例えば約600μ
m程度であり、キャビティ1aの深さは、例えば約40
0μm程度である。
The substrate 1 is made of, for example, an organic base material such as glass-epoxy or polyimide or a ceramic base material such as alumina. The thickness of the substrate 1 is, for example, about 600 μm.
m, and the depth of the cavity 1a is, for example, about 40
It is about 0 μm.

【0025】半導体チップ3の厚さは、例えば約100
μm程度であり、半導体チップ3の裏面は半導体装置の
裏面に露出してそのー部となる。
The thickness of the semiconductor chip 3 is, for example, about 100
μm, and the back surface of the semiconductor chip 3 is exposed to the back surface of the semiconductor device and becomes a part thereof.

【0026】外部接続電極5は、図1(B)に示すよう
に、半導体装置の裏面の周辺部から側面にかけてスリッ
ト状に複数並べられて設けられる。
As shown in FIG. 1B, a plurality of external connection electrodes 5 are provided in a slit shape from the peripheral portion to the side surface of the back surface of the semiconductor device.

【0027】外部接続電極5は、充分な接続性が確保で
きる形であれはどのような形状でもよいが、半導体の裏
面に露出する端面は導体の厚さ程度で微小なため、半導
体装置が実装ボード上に表面実装される際に、はんだぺ
ーストとの接触を多くし、良好なはんだ付け実装が行わ
れるように、外部接続電極5は、基板1の表面側から裏
面側に向かって内側に傾斜して設けられるのが好まし
い。この場合、外部接続電極5の端部は、半導体装置の
裏面と傾斜状に接することになる。なお、外部接続電極
5の下部にあらかじめはんだ等を被覆しておいてもよ
い。
The external connection electrode 5 may have any shape as long as it has a sufficient connection property. However, since the end face exposed on the back surface of the semiconductor is as small as the thickness of the conductor, the semiconductor device can be mounted. When mounted on the surface of the board, the external connection electrodes 5 extend inward from the front side of the substrate 1 toward the back side so that the contact with the solder paste is increased and good solder mounting is performed. Preferably, it is provided at an inclination. In this case, the end of the external connection electrode 5 is in contact with the back surface of the semiconductor device in an inclined manner. The lower part of the external connection electrode 5 may be coated with solder or the like in advance.

【0028】外部接続電極5となる導体は、基板1の半
導体装置の裏面となる側の基材を溝或いは穴加工し、そ
の内面にめっき等により導体を付着させて形成したり、
配線2上に導体をめっきやはんだ付けにより盛って形成
する。
The conductor serving as the external connection electrode 5 is formed by forming a groove or a hole in the base material of the substrate 1 on the side to be the back surface of the semiconductor device and attaching the conductor to the inner surface by plating or the like.
Conductors are formed on the wiring 2 by plating or soldering.

【0029】フェイスダウン接続としては、半導体チッ
プ3又は基板1側に金等のバンプ7を形成し、基板1の
配線2の電極に対し熱圧着やはんだ、導体ペースト、異
方性導電樹脂等によって接続する方法がとられる。
For the face-down connection, a bump 7 made of gold or the like is formed on the semiconductor chip 3 or the substrate 1 side, and thermocompression bonding, solder, conductive paste, anisotropic conductive resin or the like is applied to the electrodes of the wiring 2 of the substrate 1. The method of connection is taken.

【0030】封止樹脂4は、エポキシ、フェノール、ア
クリル系等の樹脂が用いられ、半導体チップ3と基板1
との接続部等を保護する。
As the sealing resin 4, a resin such as epoxy, phenol or acrylic resin is used.
Protect the connection with

【0031】半導体チップ3の裏面は、基板1のー部と
共に、シリコンウェハの研削を行う研磨装置等で研削さ
れ、半導体装置を薄く仕上げる。このときに外部接続電
極5となる導体も研削される。そして、半導体装置の裏
面は、基板1、半導体チップ3、封止樹脂4及び外部接
続電極5からなる略平坦状の面に形成される。
The back surface of the semiconductor chip 3 is ground together with the part of the substrate 1 by a polishing device or the like for grinding a silicon wafer to finish the semiconductor device thinly. At this time, the conductor serving as the external connection electrode 5 is also ground. The back surface of the semiconductor device is formed on a substantially flat surface including the substrate 1, the semiconductor chip 3, the sealing resin 4, and the external connection electrodes 5.

【0032】半導体装置の裏面の一部である外部接続電
極5は、実装用のボード等に電気的に接続される。
The external connection electrode 5, which is a part of the back surface of the semiconductor device, is electrically connected to a mounting board or the like.

【0033】図2及び図3は、本発明の半導体装置の製
造方法を示す工程図である。
FIGS. 2 and 3 are process diagrams showing a method for manufacturing a semiconductor device according to the present invention.

【0034】まず、基板1は、通常のプリント配線板の
製造工程と同様に製造される。基板1の裏面側には、底
部に半導体チップ3をフェイスダウン接続するための電
極が設けられたキャビティ1aをルータ等の切削機で切
削加工して形成する。また、円盤状の切削歯によってス
リット状に周囲部を切削加工した後、その内面にめっき
導体を形成することによって外部接続電極5となる導体
を設ける(図2(A)参照)。基板1の厚さは約600
μm程度、キャビティ1aの深さは約400μm程度で
ある。
First, the substrate 1 is manufactured in the same manner as in a normal printed wiring board manufacturing process. On the back side of the substrate 1, a cavity 1a provided with an electrode for connecting the semiconductor chip 3 face-down to the bottom is formed by cutting with a cutting machine such as a router. Further, after the peripheral portion is cut in a slit shape with a disk-shaped cutting tooth, a conductor serving as the external connection electrode 5 is provided by forming a plated conductor on the inner surface (see FIG. 2A). The thickness of the substrate 1 is about 600
μm, and the depth of the cavity 1a is about 400 μm.

【0035】次いで、キャビティ1aの底部に設けられ
た配線2の電極に、金のバンプ7を電極として形成した
約400μmの厚さの半導体チップ3を、はんだでフェ
イスダウン接続する。
Next, a semiconductor chip 3 having a thickness of about 400 μm and having a gold bump 7 as an electrode is face-down connected to the electrode of the wiring 2 provided at the bottom of the cavity 1a by soldering.

【0036】次いで、キャビティ1a内の隙間を封止樹
脂4で埋め、硬化して封止する(図2(B)参照)。
Next, the gap in the cavity 1a is filled with the sealing resin 4, cured, and sealed (see FIG. 2B).

【0037】次いで、半導体チップ3を裏面から研削加
工し、約100μmにまで薄くすると同時に、半導体装
置全体を約300μmにまで薄くし、かつ、裏面を平坦
状にする。このとき、外部接続電極5の端部は、半導体
装置の裏面に傾斜状に接するように形成される(図3
(A)参照)。
Next, the semiconductor chip 3 is ground from the back surface and thinned to about 100 μm, and at the same time, the whole semiconductor device is thinned to about 300 μm and the back surface is flat. At this time, the end of the external connection electrode 5 is formed so as to contact the back surface of the semiconductor device in an inclined manner (FIG. 3).
(A)).

【0038】以上の工程により、非常に薄い約300μ
m程度の半導体装置が完成する。なお、半導体装置の裏
面の外部接続電極5には実装ボード(図示せず)が電気
的に接続され、半導体装置の表面には、電子部品6が基
板1の表面に設けられた配線2と電気的に接続される
(図3(B)参照)。これによって、薄型化された高密
度の半導体装置が実現できる。
By the above steps, a very thin layer of about 300 μm
A semiconductor device of about m is completed. A mounting board (not shown) is electrically connected to the external connection electrode 5 on the back surface of the semiconductor device, and an electronic component 6 is electrically connected to the wiring 2 provided on the surface of the substrate 1 on the front surface of the semiconductor device. (See FIG. 3B). Thus, a thin, high-density semiconductor device can be realized.

【0039】図4(A)は、外部接続電極5が内側に傾
斜状に形成された場合における実装状態を示す説明図、
(B)は、外部接続電極5が垂直状に形成された場合に
おける実装状態を示す説明図である。
FIG. 4A is an explanatory view showing a mounting state when the external connection electrode 5 is formed to be inclined inward.
(B) is an explanatory view showing a mounting state when the external connection electrodes 5 are formed vertically.

【0040】外部接続電極5は、基板1の表面側から裏
面側に向かって内側に傾斜して設けられるので、裏面側
の端部は、半導体装置の裏面と傾斜状に接することにな
る。従って、はんだぺースト11が印刷された実装ボー
ド9のランド10上に、本発明の半導体装置の裏面を位
置合わせして載せたとき、内側に傾斜状に形成された外
部接続電極5(図4(A)参照)の方が、垂直状に形成
された外部接続電極5(図4(B)参照)に比べ、はん
だぺースト11と接しやすくなり、リフローの際に、は
んだペースト11が外部接続電極5に沿って這い上がる
ため、良好なはんだ付けが可能となる。
The external connection electrode 5 is provided to be inclined inward from the front surface side of the substrate 1 to the rear surface side, so that the end on the rear surface side is in contact with the rear surface of the semiconductor device in an inclined manner. Therefore, when the back surface of the semiconductor device of the present invention is placed on the land 10 of the mounting board 9 on which the solder paste 11 is printed and aligned, the external connection electrode 5 (FIG. (A) is easier to contact the solder paste 11 than the external connection electrode 5 formed vertically (see FIG. 4B), and the solder paste 11 is connected to the external paste during reflow. Since it crawls along the electrode 5, good soldering becomes possible.

【0041】図5は、本発明の第2の実施の形態に係る
半導体装置を示す縦断面図である。図5(A)に示すよ
うに、本発明の第2の実施の形態に係る半導体装置は、
裏面側に凹状のキャビティ1aが形成された基板1と、
その基板1のキャビティ1aの底部に設けられた配線2
と、その配線2の電極とフェイスダウンして電気的に接
続された半導体チップ3と、基板1のキャビティ1a内
に挿入され半導体チップ3の周囲を封止する封止樹脂4
と、配線2と電気的に接続され、基板1の裏面側の周辺
部の位置に設けられた略平坦状の外部接続電極5とを有
する。
FIG. 5 is a longitudinal sectional view showing a semiconductor device according to the second embodiment of the present invention. As shown in FIG. 5A, the semiconductor device according to the second embodiment of the present invention
A substrate 1 having a concave cavity 1a formed on the back side;
Wiring 2 provided at the bottom of cavity 1a of substrate 1
And a semiconductor chip 3 electrically connected face down to the electrodes of the wiring 2 and a sealing resin 4 inserted into the cavity 1 a of the substrate 1 and sealing the periphery of the semiconductor chip 3.
And a substantially flat external connection electrode 5 which is electrically connected to the wiring 2 and is provided at a peripheral position on the back surface side of the substrate 1.

【0042】半導体装置の裏面は、半導体チップ3、封
止樹脂4及び外部接続電極5からなる略平坦状の面で形
成される。
The back surface of the semiconductor device is formed as a substantially flat surface including the semiconductor chip 3, the sealing resin 4 and the external connection electrodes 5.

【0043】基板1はポリイミドフィルムを基材とした
約50μmの厚さのフレキシブル配線板である。半導体
チップ3の厚さは、例えば約100μmである。
The substrate 1 is a flexible wiring board having a thickness of about 50 μm using a polyimide film as a base material. The thickness of the semiconductor chip 3 is, for example, about 100 μm.

【0044】基板1は、その表面の周辺に150μmの
厚さの補強板12が貼り付けられ、中央部の裏面側に凹
状のキャビティ1aが形成される。キャビティ1aの底
部に設けられた配線2の電極に半導体チップ3がバンプ
7を介してフェイスダウン接続される。
The substrate 1 has a reinforcing plate 12 having a thickness of 150 μm adhered to the periphery of the surface thereof, and a concave cavity 1 a is formed on the back surface side at the center. The semiconductor chip 3 is face-down connected to the electrode of the wiring 2 provided at the bottom of the cavity 1 a via the bump 7.

【0045】基板1の裏面の周辺部には、外部接続電極
5を形成する導体がはんだ等の金属を凸形状に形成する
ことにより設けられる。
A conductor forming the external connection electrode 5 is provided in the peripheral portion on the back surface of the substrate 1 by forming a metal such as solder into a convex shape.

【0046】製造においては、封止樹脂4で半導体チッ
プ3を封止した後、半導体装置の裏面側を研削し、半導
体装置を300μm程度に薄く形成する。研削されて平
坦になった半導体装置の裏面にはランドグリッドアレイ
状に外部接続電極5が水平に接する形で露出される。
In manufacturing, after the semiconductor chip 3 is sealed with the sealing resin 4, the back surface side of the semiconductor device is ground to form the semiconductor device as thin as about 300 μm. External connection electrodes 5 are exposed in a land-grid array form such that they are in horizontal contact with each other on the back surface of the ground semiconductor device.

【0047】なお、図5(B)に示すように、半導体装
置の表面に配線2を設け、その配線2に電気的に接続さ
れる電子部品6を実装してもよい。
As shown in FIG. 5B, a wiring 2 may be provided on the surface of the semiconductor device, and an electronic component 6 electrically connected to the wiring 2 may be mounted.

【0048】本発明は、上記実施の形態に限定されるこ
とはなく、特許請求の範囲に記載された技術的事項の範
囲内において、種々の変更が可能である。
The present invention is not limited to the above embodiment, and various changes can be made within the scope of the technical matters described in the claims.

【0049】[0049]

【発明の効果】本発明によれば、次のような優れた効果
を奏する。 (1)半導体チップが、基板のキャビティの底部に設け
られた配線の電極とフェイスダウンして電気的に接続さ
れるので、ボンディングワイヤを用いた場合に比べ、封
止樹脂の高さを非常に低くできる。また、半導体装置の
裏面は、半導体チップ、封止樹脂及び外部接続電極を含
む略平坦状の面で形成されるので、半導体チップの裏面
等を回路に影響なく研削することができる。従って、非
常に薄い半導体装置を実現することができ、電子機器等
の小型化・軽量化を図ることができる。 (2)半導体装置の裏面は、半導体チップ、封止樹脂及
び外部接続電極を含む略平坦状の面で形成されることに
より、外部接続電極と実装用のボード等とを良好に接続
することができる。従って、信頼性の高い半導体装置を
実現することができる。
According to the present invention, the following excellent effects can be obtained. (1) Since the semiconductor chip is face-down and electrically connected to the wiring electrodes provided at the bottom of the cavity of the substrate, the height of the sealing resin is extremely reduced as compared with the case where bonding wires are used. Can be lowered. In addition, since the back surface of the semiconductor device is formed as a substantially flat surface including the semiconductor chip, the sealing resin, and the external connection electrodes, the back surface of the semiconductor chip can be ground without affecting the circuit. Therefore, a very thin semiconductor device can be realized, and the size and weight of electronic devices and the like can be reduced. (2) Since the back surface of the semiconductor device is formed as a substantially flat surface including the semiconductor chip, the sealing resin, and the external connection electrodes, the external connection electrodes can be connected well to the mounting board and the like. it can. Therefore, a highly reliable semiconductor device can be realized.

【0050】特に、外部接続電極が、基板の表面側から
裏面側に向かって内側に傾斜して設けられる場合、その
端部が半導体装置の裏面に傾斜状に接することになるの
で、実装ボード上に盛られたはんだぺーストと接しやす
くなり、リフローの際に、はんだペーストが外部接続電
極に沿って這い上がるため、良好なはんだ付けが可能と
なる (3)半導体装置の表面に電子部品等を実装できるの
で、高密度な半導体装置を実現することができる。
In particular, when the external connection electrode is provided to be inclined inward from the front surface side to the rear surface side of the substrate, the end thereof comes into contact with the rear surface of the semiconductor device in an inclined manner, so that (3) Good soldering is possible because the solder paste creeps along the external connection electrodes during reflow. (3) Electronic components and the like are mounted on the surface of the semiconductor device. Since the semiconductor device can be mounted, a high-density semiconductor device can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】(A)は本発明の第1の実施の形態に係る半導
体装置を示す縦断面図、(B)はその側面図である。
FIG. 1A is a longitudinal sectional view showing a semiconductor device according to a first embodiment of the present invention, and FIG. 1B is a side view thereof.

【図2】(A)及び(B)は本発明の半導体装置の製造
方法を示す工程図である。
FIGS. 2A and 2B are process diagrams showing a method for manufacturing a semiconductor device according to the present invention.

【図3】(A)及び(B)は本発明の半導体装置の製造
方法を示す工程図である。
FIGS. 3A and 3B are process diagrams showing a method for manufacturing a semiconductor device according to the present invention.

【図4】(A)は、外部接続電極が内側に傾斜状に形成
された場合における実装状態を示す説明図、(B)は、
外部接続電極が垂直状に形成された場合における実装状
態を示す説明図である。
FIG. 4A is an explanatory view showing a mounting state when an external connection electrode is formed to be inclined inward, and FIG.
FIG. 9 is an explanatory diagram showing a mounting state when the external connection electrodes are formed vertically.

【図5】本発明の第2の実施の形態に係る半導体装置を
示す縦断面図である。
FIG. 5 is a longitudinal sectional view showing a semiconductor device according to a second embodiment of the present invention.

【図6】従来の半導体装置を示す縦断面図である。FIG. 6 is a longitudinal sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1:基板 1a:キャビティ 2:配線 3:半導体チップ 4:封止樹脂 5:外部接続電極 6:電子部品 7:バンプ 9 実装ボード 10 ランド 11 はんだぺースト 12 補強板 1: substrate 1a: cavity 2: wiring 3: semiconductor chip 4: sealing resin 5: external connection electrode 6: electronic component 7: bump 9 mounting board 10 land 11 solder paste 12 reinforcing plate

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】裏面側に凹状のキャビティが形成された基
板と、その基板のキャビティの底部に設けられた配線
と、その配線の電極とフェイスダウンして電気的に接続
された半導体チップと、前記基板のキャビティ内に挿入
され前記半導体チップの周囲を封止する封止樹脂と、前
記配線と電気的に接続された外部接続電極と、を有し、 前記半導体チップ、封止樹脂及び外部接続電極を含む略
平坦状の裏面を備えていることを特徴とする半導体装
置。
A substrate provided with a concave cavity on the back surface side, a wiring provided at a bottom of the cavity of the substrate, a semiconductor chip electrically connected face down to an electrode of the wiring; A sealing resin inserted into a cavity of the substrate to seal around the semiconductor chip; and an external connection electrode electrically connected to the wiring, wherein the semiconductor chip, the sealing resin, and the external connection A semiconductor device having a substantially flat back surface including electrodes.
【請求項2】裏面側に凹状のキャビティが形成された基
板と、その基板のキャビティの底部に設けられた配線
と、その配線の電極とフェイスダウンして電気的に接続
された半導体チップと、前記基板のキャビティ内に挿入
され前記半導体チップの周囲を封止する封止樹脂と、前
記基板の側面に設けられ、前記配線と電気的に接続され
た外部接続電極と、を有し、 前記基板、半導体チップ、封止樹脂及び外部接続電極か
らなる略平坦状の裏面を備えていることを特徴とする半
導体装置。
2. A substrate having a concave cavity formed on the back side, a wiring provided at the bottom of the cavity of the substrate, and a semiconductor chip which is electrically connected face down to an electrode of the wiring. A sealing resin inserted into a cavity of the substrate to seal around the semiconductor chip, and an external connection electrode provided on a side surface of the substrate and electrically connected to the wiring, A semiconductor device having a substantially flat back surface comprising a semiconductor chip, a sealing resin, and an external connection electrode.
【請求項3】前記外部接続電極は、基板の表面側から裏
面側に向かって内側に傾斜して設けられることを特徴と
する請求項2に記載の半導体装置。
3. The semiconductor device according to claim 2, wherein the external connection electrode is provided to be inclined inward from the front side to the back side of the substrate.
【請求項4】裏面側に凹状のキャビティが形成された基
板と、その基板のキャビティの底部に設けられた配線
と、その配線の電極とフェイスダウンして電気的に接続
された半導体チップと、前記基板のキャビティ内に挿入
され前記半導体チップの周囲を封止する封止樹脂と、前
記配線と電気的に接続され、前記基板の裏面側の周辺部
の位置に設けられた略平坦状の外部接続電極とを有し、 前記半導体チップ、封止樹脂及び外部接続電極からなる
略平坦状の裏面を備えていることを特徴とする半導体装
置。
4. A substrate having a concave cavity formed on the back side, a wiring provided at the bottom of the cavity of the substrate, and a semiconductor chip which is electrically connected face down to an electrode of the wiring. A sealing resin inserted into the cavity of the substrate and sealing the periphery of the semiconductor chip; and a substantially flat external part electrically connected to the wiring and provided at a peripheral portion on the back side of the substrate. A semiconductor device comprising: a connection electrode; and a substantially flat back surface including the semiconductor chip, a sealing resin, and an external connection electrode.
【請求項5】前記半導体チップの電極と前記基板の配線
の電極とはバンプを介して電気的に接続されることを特
徴とする請求項1乃至4のいずれか1つの項に記載の半
導体装置。
5. The semiconductor device according to claim 1, wherein the electrodes of the semiconductor chip and the electrodes of the wiring of the substrate are electrically connected via bumps. .
【請求項6】前記基板の表面に設けられた配線と、その
配線と電気的に接続された電子部品とを、さらに有する
ことを特徴とする請求項1乃至5のいずれか1つの項に
記載の半導体装置。
6. The semiconductor device according to claim 1, further comprising a wiring provided on a surface of the substrate, and an electronic component electrically connected to the wiring. Semiconductor device.
【請求項7】(1)裏面側に凹状のキャビティが形成さ
れ、そのキャビティの底部に設けられた配線と、その配
線と電気的に接続された外部接続電極とを備えた基板を
作る工程と、(2)前記半導体チップを、前記基板のキ
ャビティの底部に設けられた配線の電極にフェイスダウ
ンして電気的に接続する工程と、(3)前記基板のキャ
ビティ内に樹脂を挿入し、前記半導体チップの周囲を封
止する工程と、(4)前記半導体チップ、封止樹脂及び
外部接続電極を含む裏面を略平坦状に所定の厚さになる
まで削る工程と、 を有し、(1)から(4)の順序で行うことを特徴とす
る半導体装置の製造方法。
7. A step of forming a substrate in which a concave cavity is formed on the back surface side, the substrate provided with a wiring provided at the bottom of the cavity, and an external connection electrode electrically connected to the wiring. (2) a step of face-down electrically connecting the semiconductor chip to an electrode of a wiring provided on a bottom of the cavity of the substrate; and (3) inserting a resin into the cavity of the substrate, (1) a step of sealing the periphery of the semiconductor chip, and (4) a step of shaving the back surface including the semiconductor chip, the sealing resin, and the external connection electrode to a substantially flat shape to a predetermined thickness. ) To (4), in which order.
JP27593397A 1997-10-08 1997-10-08 Semiconductor device and manufacturing method thereof Expired - Lifetime JP3061014B2 (en)

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Publication number Priority date Publication date Assignee Title
GB2396963A (en) * 2002-11-14 2004-07-07 Agilent Technologies Inc Semiconductor packaging structure
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