JPH05275608A - Semiconductor element housing package - Google Patents
Semiconductor element housing packageInfo
- Publication number
- JPH05275608A JPH05275608A JP7109592A JP7109592A JPH05275608A JP H05275608 A JPH05275608 A JP H05275608A JP 7109592 A JP7109592 A JP 7109592A JP 7109592 A JP7109592 A JP 7109592A JP H05275608 A JPH05275608 A JP H05275608A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- thick film
- film resistor
- metal frame
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体素子を収容するた
めの半導体素子収納用パッケージに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element.
【０００２】[0002]
【従来の技術】従来、半導体素子を収納するための半導
体素子収納用パッケージは、図２に示すように、上面中
央部に半導体素子を搭載するための半導体素子搭載部Ｂ
及び該半導体素子搭載部Ｂ周辺より底面にかけて導出す
るメタライズ配線層１２を有し、且つ上面外周部に金属
枠体１３がろう付けされた絶縁基体１１と蓋体１４とか
ら構成され、前記絶縁基体１１の半導体素子搭載部Ｂに
半導体素子１５を樹脂、ガラス、半田等の接着剤を介し
て取着固定した後、半導体素子１５の各電極をボンディ
ングワイヤー１６を介してメタライズ配線層１２に電気
的に接続し、しかる後、前記絶縁基体１１にろう付けさ
れた金属枠体１３に蓋体１４を溶接により接合させ、絶
縁基体１１と蓋体１４とから成る容器の内部に半導体素
子１５を気密に封止することによって最終製品としての
半導体装置となる。2. Description of the Related Art Conventionally, as shown in FIG. 2, a semiconductor element housing package for housing a semiconductor element has a semiconductor element mounting portion B for mounting a semiconductor element in a central portion of an upper surface thereof.
And an insulating base 11 having a metallized wiring layer 12 extending from the periphery of the semiconductor element mounting portion B to the bottom and having a metal frame 13 brazed to the outer periphery of the upper surface, and a lid 14, After the semiconductor element 15 is attached and fixed to the semiconductor element mounting portion B of 11 with an adhesive such as resin, glass or solder, each electrode of the semiconductor element 15 is electrically connected to the metallized wiring layer 12 via the bonding wire 16. Then, the lid 14 is joined to the metal frame 13 brazed to the insulating base 11 by welding, and the semiconductor element 15 is hermetically sealed inside the container including the insulating base 11 and the lid 14. By encapsulating, a semiconductor device as a final product is obtained.
【０００３】また、この従来の半導体素子収納用パッケ
ージでは、絶縁基体１１の底面で、半導体素子１５の入
出力電極が接続されるメタライズ配線層１２と接地電極
が接続されるメタライズ配線層１２との間に終端抵抗と
しての厚膜抵抗体１７が被着形成されており、該厚膜抵
抗体１７は半導体素子１５に出し入れされる電気信号に
発生するノイズを有効に除去し、半導体素子１５を正常
に作動させるようになっている。Further, in this conventional semiconductor element housing package, the metallized wiring layer 12 to which the input / output electrodes of the semiconductor element 15 are connected and the metallized wiring layer 12 to which the ground electrode is connected are formed on the bottom surface of the insulating substrate 11. A thick film resistor 17 as a terminating resistor is formed between the thick film resistor 17 and the thick film resistor 17 effectively removes noise generated in an electric signal which is taken in and out of the semiconductor element 15 to keep the semiconductor element 15 normal. It is designed to operate.
【０００４】尚、前記絶縁基体１１はメタライズ配線層
１２となる金属ペーストが印刷塗布されたセラミックグ
リーンシートを複数枚積層するとともに約１６００℃の
温度で焼成してメタライズ配線層１２を有するセラミッ
ク焼結体となし、次に前記セラミック焼結体の上面に金
属枠体１３を約１０００℃の温度で銀ろう付けした後、
前記セラミック焼結体の下面に厚膜抵抗体１７となる抵
抗体ペーストをスクリーン印刷法を用いて印刷塗布し、
最後にこれを約９００℃の温度で焼き付けることによっ
て製作される。The insulating substrate 11 is formed by laminating a plurality of ceramic green sheets on which a metal paste to be the metallized wiring layer 12 is printed and applied, and firing the ceramic green sheets at a temperature of about 1600 ° C. to sinter the ceramic substrate having the metallized wiring layer 12. And then brazing the metal frame 13 on the upper surface of the ceramic sintered body at a temperature of about 1000 ° C.
A resistor paste to be the thick film resistor 17 is printed and applied on the lower surface of the ceramic sintered body by a screen printing method,
Finally, it is manufactured by baking it at a temperature of about 900 ° C.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージでは、厚膜抵抗体１７
が絶縁基体１１の底面に形成されており、厚膜抵抗体１
７と半導体素子１５との配線距離が長いものであること
から厚膜抵抗体１７が半導体素子に出し入れされる電気
信号に発生したノイズを効果的に除去することができ
ず、半導体素子１５を常に、正常に作動させることがで
きないという欠点を有していた。However, in the conventional package for accommodating semiconductor elements, the thick film resistor 17 is used.
Is formed on the bottom surface of the insulating substrate 11, and the thick film resistor 1
Since the wiring distance between the semiconductor element 15 and the semiconductor element 15 is long, the thick film resistor 17 cannot effectively remove the noise generated in the electric signal input to and output from the semiconductor element, and the semiconductor element 15 is always It had a drawback that it could not be operated normally.
【０００６】そこで、上記欠点を解消するために厚膜抵
抗体１７を絶縁基体１１上面の半導体素子１５近傍に形
成し、厚膜抵抗体１７と半導体素子１５との配線距離を
短くすることが考えられる。Therefore, in order to solve the above drawbacks, it is considered to form the thick film resistor 17 on the upper surface of the insulating substrate 11 in the vicinity of the semiconductor element 15 to shorten the wiring distance between the thick film resistor 17 and the semiconductor element 15. Be done.
【０００７】しかしながら、絶縁基体１１の上面に厚膜
抵抗体１７を形成する場合、絶縁基体１１の上面には蓋
体１４が溶接される金属枠体１３が取着されており、該
金属枠体１３はその高さが高いことから絶縁基体１１の
上面に厚膜抵抗体１７となる抵抗体ペーストをスクリー
ン印刷法により印刷塗布しようとしても前記金属枠体１
３がスクリーン印刷機の絶縁基体１１上面への当接を阻
害し、その結果、絶縁基体１１上面に所定パターン、所
定抵抗値の厚膜抵抗体１７を被着形成することができな
いという欠点を誘発した。However, when the thick film resistor 17 is formed on the upper surface of the insulating base body 11, the metal frame body 13 to which the lid body 14 is welded is attached to the upper surface of the insulating base body 11. Since 13 is high in height, even if an attempt is made to print-apply a resistor paste that will become the thick film resistor 17 on the upper surface of the insulating substrate 11 by screen printing,
3 impedes contact with the upper surface of the insulating substrate 11 of the screen printing machine, and as a result, induces a defect that the thick film resistor 17 having a predetermined pattern and a predetermined resistance value cannot be adhered and formed on the upper surface of the insulating substrate 11. did.
【０００８】また、絶縁基体１１に金属枠体１３を取着
する前に、絶縁基体１１の上面に厚膜抵抗体１７を形成
しておくことも考えられるが、この場合、絶縁基体１１
に金属枠体１３をろう付けにより取着する際に先に絶縁
基体１１の上面に形成した厚膜抵抗体１７に約１０００
℃のろう付け温度が印加されることとなり、その結果、
前記厚膜導体１７は印加されるろう付け温度によって組
織変化を起し、厚膜抵抗体１７の抵抗値が大きく変化し
て半導体素子１５に出し入れされる電気信号に発生する
ノイズを有効に除去することができなくなるという欠点
が誘発される。It is also possible to form a thick film resistor 17 on the upper surface of the insulating base 11 before attaching the metal frame 13 to the insulating base 11. In this case, the insulating base 11 is formed.
When the metal frame body 13 is attached by brazing to the thick film resistor 17 previously formed on the upper surface of the insulating substrate 11, approximately 1000
A brazing temperature of ° C will be applied, resulting in
The thick film conductor 17 undergoes a tissue change depending on the brazing temperature applied thereto, and the resistance value of the thick film resistor 17 largely changes to effectively remove noise generated in an electric signal which is taken in and out of the semiconductor element 15. The drawback of being unable to do so is triggered.
【０００９】[0009]
【発明の目的】本発明は、上記欠点に鑑み案出されたも
のであり、その目的は、半導体素子に出し入れされる電
気信号に発生するノイズを有効に除去し、半導体素子を
安定に、且つ確実に作動させることが可能な半導体素子
収納用パッケージを提供することにある。SUMMARY OF THE INVENTION The present invention has been devised in view of the above-mentioned drawbacks, and an object of the present invention is to effectively remove noise generated in an electric signal which is put into and taken out of a semiconductor element, to stabilize the semiconductor element, and It is an object to provide a package for accommodating a semiconductor element that can be reliably operated.
【００１０】[0010]
【課題を解決するための手段】本発明は、上面外周部に
金属枠体が取着された絶縁基体と蓋体とから成り、内部
に半導体素子を収容するための空所を有する半導体素子
収納用パッケージであって、前記絶縁基体はその上面中
央部に金属枠体の高さより高い突出部を有し、且つ該突
出部上面に半導体素子が載置固定される載置部と、前記
半導体素子の各電極を外部電気回路に接続する複数個の
メタライズ配線層の一端と、前記半導体素子の接地電極
及び入出力電極との間に接続される厚膜抵抗体とを被着
形成したことを特徴とするものである。According to the present invention, there is provided a semiconductor element housing comprising an insulating base body having a metal frame body attached to an outer peripheral portion of an upper surface thereof and a lid body, and having a space for housing a semiconductor element therein. A package for a semiconductor device, wherein the insulating base has a protrusion at a central portion of an upper surface thereof that is higher than a height of a metal frame, and a semiconductor element is mounted and fixed on the upper surface of the protrusion. And a thick film resistor connected between one end of a plurality of metallized wiring layers connecting the respective electrodes to an external electric circuit and the ground electrode and the input / output electrode of the semiconductor element are adhered and formed. It is what
【００１１】[0011]
【作用】本発明の半導体素子収納用パッケージによれば
上面外周部に金属枠体が取着された絶縁基体の上面中央
部に金属枠体の高さより高い突出部を設け、該突出部上
面に半導体素子が載置固定される載置部と、前記半導体
素子の各電極を外部電気回路に接続する複数個のメタラ
イズ配線層の一端と、前記半導体素子の接地電極及び入
出力電極との間に接続される厚膜抵抗体とを被着形成す
るようになしたことから絶縁基体の上面中央部に厚膜抵
抗体となる抵抗体ペーストをスクリーン印刷によって印
刷塗布する際、金属枠体がスクリーン印刷機の絶縁基体
上面への当接を阻害することはなく、その結果、絶縁基
体上面に所定パターン、所定抵抗値の厚膜抵抗体を被着
形成することができる。According to the package for housing a semiconductor element of the present invention, a projecting portion higher than the height of the metal frame body is provided in the central portion of the upper surface of the insulating substrate having the metal frame body attached to the outer peripheral surface of the upper surface, and the projecting portion has an upper surface. Between a mounting portion on which the semiconductor element is mounted and fixed, one ends of a plurality of metallized wiring layers connecting each electrode of the semiconductor element to an external electric circuit, and a ground electrode and an input / output electrode of the semiconductor element. Since the thick film resistor to be connected is adhered and formed, when the resistor paste to be the thick film resistor is applied by screen printing to the central portion of the upper surface of the insulating substrate, the metal frame is screen printed. It does not hinder the contact of the machine with the upper surface of the insulating substrate, and as a result, a thick film resistor having a predetermined pattern and a predetermined resistance value can be deposited on the upper surface of the insulating substrate.
【００１２】[0012]
【実施例】次に本発明の半導体素子収納用パッケージを
添付図面に基づき詳細に説明する。図１は本発明の半導
体素子収納用パッケージの一実施例を示す断面図であ
り、１は絶縁基体、２は蓋体である。前記絶縁基体１と
蓋体２とで半導体素子４を収容する容器３が構成され
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor element housing package of the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention, in which 1 is an insulating base and 2 is a lid. The insulating base 1 and the lid 2 constitute a container 3 for housing the semiconductor element 4.
【００１３】前記絶縁基体１は酸化アルミニウム質焼結
体、ムライト質焼結体、炭化珪素質焼結体、窒化アルミ
ニウム質焼結体等の電気絶縁材料から成る板状体であ
り、その上面外周部にはコバール（Ｆｅ−Ｃｏ−Ｎｉ合
金）等の金属から成る金属枠体５が銀ろう等のろう材を
介して接合されている。The insulating substrate 1 is a plate-like body made of an electrically insulating material such as an aluminum oxide sintered body, a mullite sintered body, a silicon carbide sintered body, and an aluminum nitride sintered body. A metal frame body 5 made of a metal such as Kovar (Fe—Co—Ni alloy) is joined to the portion via a brazing material such as silver brazing.
【００１４】前記絶縁基体１はその上面中央部に金属枠
体５の高さよりも高い突出部６を有し、該突出部６の上
面は半導体素子４を搭載するための半導体素子搭載部Ａ
となっており、該半導体素子搭載部Ａには半導体素子４
が樹脂、ガラス、ろう材等の接着材を介して取着固定さ
れる。The insulating substrate 1 has a protrusion 6 higher than the height of the metal frame 5 at the center of the upper surface thereof, and the upper surface of the protrusion 6 has a semiconductor element mounting portion A for mounting the semiconductor element 4.
The semiconductor element mounting portion A has a semiconductor element 4
Are attached and fixed via an adhesive material such as resin, glass, or brazing material.
【００１５】尚、前記突出部６を有する絶縁基体１は、
例えば酸化アルミニウム質焼結体から成る場合、アルミ
ナ、シリカ、カルシア、マグネシア等の原料粉末に適当
なバインダー、有機溶剤を添加混合して泥漿状となすと
ともに、これを従来周知のドクターブレード法やカレン
ダーロール法によりシート状となすことによってセラミ
ックグリーンシートを得、次に前記セラミックグリーン
シートに適当な打ち抜き加工を施すとともに、これを複
数枚積層し、高温（約１６００℃）で焼成することによ
って製作される。The insulating base 1 having the protrusion 6 is
For example, in the case of an aluminum oxide sintered body, alumina, silica, calcia, magnesia, and other raw material powders are mixed with an appropriate binder and an organic solvent to form a slurry, which is conventionally known as a doctor blade method or calender. A ceramic green sheet is obtained by forming it into a sheet by a roll method, and then the ceramic green sheet is subjected to appropriate punching processing, and a plurality of these are laminated and fired at a high temperature (about 1600 ° C.). It
【００１６】また、前記絶縁基体１はその突出部６の上
面で、半導体素子搭載部Ａ周辺から底面にかけて複数の
メタライズ配線層７が形成されており、該メタライズ配
線層７の突出部６上面部位には半導体素子４の各電極が
ボンディングワイヤー８を介して電気的に接続され、ま
たメタライズ配線層７の絶縁基体１下面部位は外部電気
回路の配線導体が半田等の導電性接着剤を介して接続さ
れ、これによって半導体素子４がボンディングワイヤ８
及びメタライズ配線層７を介して外部電気回路と電気的
に接続されることとなる。A plurality of metallized wiring layers 7 are formed on the upper surface of the protruding portion 6 of the insulating base 1 from the periphery of the semiconductor element mounting portion A to the bottom surface thereof. The electrodes of the semiconductor element 4 are electrically connected to each other via the bonding wires 8, and the wiring conductor of the external electric circuit is connected to the lower surface of the insulating substrate 1 of the metallized wiring layer 7 via a conductive adhesive such as solder. The semiconductor element 4 is connected to the bonding wire 8
And, it is electrically connected to an external electric circuit through the metallized wiring layer 7.
【００１７】前記メタライズ配線層７はタングステン、
モリブデン、マンガン等の高融点金属粉末から成り、該
タングステン等の高融点金属粉末に適当なバインダー、
有機溶剤を添加混合して得た金属ペーストを絶縁基体１
となるセラミックグリーンシートに予め従来周知のスク
リーン印刷法により印刷塗布しておくことによって形成
される。The metallized wiring layer 7 is made of tungsten,
It is composed of a high melting point metal powder such as molybdenum and manganese, and is a binder suitable for the high melting point metal powder such as tungsten,
Insulating substrate 1 is a metal paste obtained by adding and mixing an organic solvent.
It is formed by printing and applying in advance to a ceramic green sheet to be formed by a conventionally known screen printing method.
【００１８】尚、前記メタライズ配線層７はその露出す
る外表面にニッケル、金等の耐食性に優れ、且つ半田等
の導電性接着剤と濡れ性の良い金属をメッキにより０．
１乃至２０μｍの厚みに層着させておくと、メタライズ
配線層７が酸化腐食されるのを有効に防止できるととも
にメタライズ配線層７とボンディングワイヤー８及びメ
タライズ配線層７と外部電気回路の配線導体との接続が
容易、且つ強固なものとなる。従って、メタライズ配線
層７が酸化腐食されるのを有効に防止するとともにメタ
ライズ配線層７とボンディングワイヤー８及びメタライ
ズ配線層７と外部電気回路の配線導体との接続を容易、
且つ強固なものとなすためにはメタライズ配線層７の露
出する外表面にニッケル、金等の耐食性に優れ、且つ半
田等の導電性接着剤と濡れ性の良い金属をメッキにより
０．１乃至２０μｍの厚みに層着させておくことが好ま
しい。The metallized wiring layer 7 has an exposed outer surface which is plated with a metal such as nickel and gold having excellent corrosion resistance and a conductive adhesive such as solder and having good wettability.
When the metallized wiring layer 7 is layered to a thickness of 1 to 20 μm, the metallized wiring layer 7 can be effectively prevented from being oxidized and corroded, and the metallized wiring layer 7, the bonding wire 8, the metallized wiring layer 7, and the wiring conductor of the external electric circuit can be effectively prevented. Connection is easy and strong. Therefore, the metallized wiring layer 7 can be effectively prevented from being oxidized and corroded, and the metallized wiring layer 7 and the bonding wire 8 and the metallized wiring layer 7 and the wiring conductor of the external electric circuit can be easily connected.
In addition, in order to make it strong, the exposed outer surface of the metallized wiring layer 7 is plated with a metal having good corrosion resistance such as nickel and gold, and a conductive adhesive such as solder and good wettability by 0.1 to 20 μm. It is preferable that the layers are laminated to each other.
【００１９】また前記絶縁基体１はその突出部６上面で
半導体素子４の入出力電極が接続されるメタライズ配線
層と接地電極が接続されるメタライズ配線層との間に終
端抵抗としての厚膜抵抗体９が被着形成されている。On the upper surface of the protruding portion 6 of the insulating substrate 1, a thick film resistor as a terminating resistor is provided between the metallized wiring layer to which the input / output electrodes of the semiconductor element 4 are connected and the metallized wiring layer to which the ground electrode is connected. The body 9 is adhered and formed.
【００２０】前記厚膜抵抗体９はランタンボライド（Ｌ
ａＢ6 ）、酸化錫（ＳｎＯ2 ）等の抵抗体からなり、該
ランタンボライド等の抵抗体粉末に適当なガラスフリッ
ト、バインダー、有機溶剤を添加混合して得た抵抗体ペ
ーストを前記絶縁基体１の突出部６上面に従来周知のス
クリーン印刷法により印刷塗布した後、これを約９００
℃の温度で焼き付けることによって絶縁基体１の突出部
６にメタライズ配線層７と電気的に接続されるようにし
て被着形成される。The thick film resistor 9 is made of lanthanide (L
aB6), tin oxide (SnO2) or the like, and a resistor paste obtained by adding and mixing a suitable glass frit, a binder and an organic solvent to the resistor powder such as lanthanum boride. After printing and coating on the upper surface of the protrusion 6 by a conventionally known screen printing method, about 900
By baking at a temperature of ° C, the protrusion 6 of the insulating substrate 1 is deposited and formed so as to be electrically connected to the metallized wiring layer 7.
【００２１】前記厚膜抵抗９は絶縁基体１の突出部６上
面で半導体素子４の近傍に形成されていることから厚膜
抵抗体９と半導体素子４との間の配線距離は極めて短い
ものとなり、その結果、厚膜抵抗体９が半導体素子４に
出し入れされる電気信号に発生したノイズを極めて有効
に除去することが可能となる。Since the thick film resistor 9 is formed in the vicinity of the semiconductor element 4 on the upper surface of the protruding portion 6 of the insulating substrate 1, the wiring distance between the thick film resistor 9 and the semiconductor element 4 becomes extremely short. As a result, it becomes possible to very effectively remove the noise generated in the electric signal which the thick film resistor 9 takes in and out of the semiconductor element 4.
【００２２】また前記厚膜抵抗体９は突出部６上面が金
属枠体５の高さより高くなっていることから突出部６上
面にスクリーン印刷法を採用することによって形成する
際、金属枠体５がスクリーン印刷機の突出部６上面への
当接を阻害することはなく、その結果、絶縁基体１の突
出部６上面に所定パターン、所定抵抗値の厚膜抵抗体９
を被着形成することができる。Since the upper surface of the protruding portion 6 is higher than the height of the metal frame body 5 when the thick film resistor 9 is formed by using the screen printing method on the upper surface of the protruding portion 6, the metal frame body 5 is formed. Does not hinder the contact with the upper surface of the protrusion 6 of the screen printing machine, and as a result, the thick film resistor 9 having a predetermined pattern and a predetermined resistance value is formed on the upper surface of the protrusion 6 of the insulating substrate 1.
Can be adhered and formed.
【００２３】更に前記絶縁基体１はその外周部に金属枠
体５がろう付けされており、該金属枠体５は絶縁基体１
に蓋体２を接合する際の下地金属として作用し、前記金
属枠体５の上面には金属製の蓋体２がシームウエルド或
いはろう付けによって接合される。Further, a metal frame body 5 is brazed to the outer peripheral portion of the insulating base body 1, and the metal frame body 5 is the insulating base body 1.
It acts as a base metal when the lid 2 is joined to the metal lid 5, and the lid 2 made of metal is joined to the upper surface of the metal frame 5 by seam welding or brazing.
【００２４】前記金属枠体５は、例えばコバールから成
る場合は、コバールの板材を従来周知の打ち抜き加工法
によって枠状に成形することによって製作され、金属枠
体５の絶縁基体１への取着は、絶縁基体１の上面外周部
に例えば純銀から成るろう材と金属枠体５とを順次載置
するとともにこれを還元雰囲気中約１０００℃の温度に
加熱して純銀から成るろう材を溶融させることによって
接合される。When the metal frame body 5 is made of, for example, Kovar, it is manufactured by forming a Kovar plate material into a frame shape by a conventionally known punching method, and attaching the metal frame body 5 to the insulating substrate 1. For example, a brazing material made of pure silver and a metal frame 5 are sequentially placed on the outer peripheral portion of the upper surface of the insulating substrate 1, and the brazing material made of pure silver is melted by heating the brazing material made of pure silver in a reducing atmosphere. To be joined together.
【００２５】尚、前記金属枠体５はその露出する外表面
にニッケル、金等の耐食性に優れた金属を０．１乃至２
０μｍの厚みに層着させておけば、金属枠体５が酸化腐
食するのを有効に防止できる。従って、前記金属枠体５
の外表面にはニッケル、金等の耐食性に優れた金属を
０．１乃至２０μｍの厚みに層着させておくことが好ま
しい。It should be noted that the metal frame body 5 has a metal such as nickel or gold having excellent corrosion resistance on the exposed outer surface thereof in an amount of 0.1 to 2.
When the metal frame 5 is layered to a thickness of 0 μm, it is possible to effectively prevent the metal frame 5 from being oxidized and corroded. Therefore, the metal frame 5
It is preferable that a metal having excellent corrosion resistance such as nickel and gold is layered on the outer surface of 0.1 to a thickness of 0.1 to 20 μm.
【００２６】かくして、本発明の半導体素子収納用パッ
ケージによれば、絶縁基体１の半導体素子搭載部Ａに半
導体素子４を樹脂、ガラス、ろう材等の接着剤を介して
取着固定するとともに該半導体素子４の各電極をメタラ
イズ配線層７にボンディングワイヤー８を介して電気的
に接続し、しかる後、絶縁基体１にろう付けされた金属
枠体５の上面に蓋体２を接合させ内部に半導体素子４を
気密に封止することによって半導体装置となる。Thus, according to the semiconductor element housing package of the present invention, the semiconductor element 4 is attached and fixed to the semiconductor element mounting portion A of the insulating substrate 1 via an adhesive such as resin, glass or brazing material. Each electrode of the semiconductor element 4 is electrically connected to the metallized wiring layer 7 via a bonding wire 8. After that, the lid 2 is joined to the upper surface of the metal frame body 5 brazed to the insulating base body 1 inside. A semiconductor device is obtained by hermetically sealing the semiconductor element 4.
【００２７】尚、本発明は上述の実施例に限定されるも
のではなく、本発明の要旨を逸脱しない範囲であれば種
々の変更は可能であり、例えば上述の実施例では厚膜抵
抗体は終端抵抗であったが、ダンピング抵抗や他の抵抗
であっても良い。The present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the present invention. For example, in the above-mentioned embodiments, the thick film resistor is Although it is a terminating resistance, it may be a damping resistance or another resistance.
【００２８】また、絶縁基体１の上面には厚膜抵抗体の
他に銅や銀−パラジウム等の厚膜導体から成る厚膜導体
層を被着形成しても良い。In addition to the thick film resistor, a thick film conductor layer made of a thick film conductor such as copper or silver-palladium may be deposited on the upper surface of the insulating substrate 1.
【００２９】[0029]
【発明の効果】本発明の半導体素子収納用パッケージに
よれば、上面外周部に金属枠体が取着された絶縁基体の
上面中央部に金属枠体の高さより高い突出部を設け、該
突出部上面に半導体素子が載置固定される載置部と、前
記半導体素子の各電極を外部電気回路に接続する複数個
のメタライズ配線層の一端と、前記半導体素子の接地電
極及び入出力電極との間に接続される厚膜抵抗体とを被
着形成するようになしたことから絶縁基体の上面中央部
に厚膜抵抗体となる抵抗体ペーストをスクリーン印刷に
よって印刷塗布する際、金属枠体がスクリーン印刷機の
絶縁基体上面への当接を阻害することはなく、その結
果、絶縁基体上面に所定パターン、所定抵抗値の厚膜抵
抗体を被着形成することができる。According to the package for accommodating semiconductor elements of the present invention, a projecting portion higher than the height of the metal frame body is provided at the central portion of the upper surface of the insulating substrate having the metal frame body attached to the outer peripheral surface of the upper surface. A mounting portion on which a semiconductor element is mounted and fixed on the upper surface of the portion, one end of a plurality of metallized wiring layers connecting each electrode of the semiconductor element to an external electric circuit, and a ground electrode and an input / output electrode of the semiconductor element. Since a thick film resistor connected between the two is adhered and formed, a metal frame body is used when the resistor paste to be the thick film resistor is applied by screen printing to the central portion of the upper surface of the insulating substrate. Does not hinder the contact of the screen printing machine with the upper surface of the insulating substrate, and as a result, a thick film resistor having a predetermined pattern and a predetermined resistance value can be deposited on the upper surface of the insulating substrate.
【００３０】また厚膜抵抗を半導体素子の近傍に形成し
たことから厚膜抵抗体と半導体素子との間の配線距離は
極めて短いものとなり、その結果、厚膜抵抗体が半導体
素子に出し入れされる電気信号に発生したノイズを極め
て有効に除去することが可能となる。Further, since the thick film resistor is formed in the vicinity of the semiconductor element, the wiring distance between the thick film resistor and the semiconductor element becomes extremely short, and as a result, the thick film resistor is taken in and out of the semiconductor element. It is possible to very effectively remove the noise generated in the electric signal.
【図１】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of a semiconductor element housing package of the present invention.
【図２】従来の半導体素子収納用パッケージを示す断面
図である。FIG. 2 is a cross-sectional view showing a conventional semiconductor element housing package.
１・・・絶縁基体 ２・・・蓋体 ３・・・容器 ４・・・半導体素子 ５・・・金属枠体 ６・・・突出部 Ａ・・・半導体素子搭載部 ７・・・メタライズ配線層 ９・・・厚膜抵抗体 DESCRIPTION OF SYMBOLS 1 ... Insulating base body 2 ... Lid body 3 ... Container 4 ... Semiconductor element 5 ... Metal frame body 6 ... Projection part A ... Semiconductor element mounting part 7 ... Metallized wiring Layer 9: thick film resistor
Claims (1)
体と蓋体とから成り、内部に半導体素子を収容するため
の空所を有する半導体素子収納用パッケージであって、
前記絶縁基体はその上面中央部に金属枠体の高さより高
い突出部を有し、且つ該突出部上面に半導体素子が載置
固定される載置部と、前記半導体素子の各電極を外部電
気回路に接続する複数個のメタライズ配線層の一端と、
前記半導体素子の接地電極及び入出力電極との間に接続
される厚膜抵抗体とを被着形成したことを特徴とする半
導体素子収納用パッケージ。1. A package for accommodating a semiconductor element, comprising an insulating base body having a metal frame attached to an outer peripheral surface of an upper surface thereof and a lid body, and having a cavity for accommodating a semiconductor element therein.
The insulating substrate has a protrusion at the center of the upper surface thereof that is higher than the height of the metal frame, and a mounting portion on which the semiconductor element is mounted and fixed on the upper surface of the protrusion and each electrode of the semiconductor element are electrically connected to the outside. One end of a plurality of metallized wiring layers connected to the circuit,
A package for accommodating a semiconductor element, wherein a thick film resistor connected between a ground electrode and an input / output electrode of the semiconductor element is adhered and formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7109592A JPH05275608A (en) | 1992-03-27 | 1992-03-27 | Semiconductor element housing package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7109592A JPH05275608A (en) | 1992-03-27 | 1992-03-27 | Semiconductor element housing package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05275608A true JPH05275608A (en) | 1993-10-22 |
Family
ID=13450640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7109592A Pending JPH05275608A (en) | 1992-03-27 | 1992-03-27 | Semiconductor element housing package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05275608A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767579A (en) * | 1995-12-21 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an electrical connection between a control electrode and a resistive layer |
| JP2013026317A (en) * | 2011-07-19 | 2013-02-04 | Fujitsu Ltd | Heat dissipation module and electronic device |
| JP2019169675A (en) * | 2018-03-26 | 2019-10-03 | 京セラ株式会社 | Ceramic circuit board, package, and electronic apparatus |
-
1992
- 1992-03-27 JP JP7109592A patent/JPH05275608A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5767579A (en) * | 1995-12-21 | 1998-06-16 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having an electrical connection between a control electrode and a resistive layer |
| JP2013026317A (en) * | 2011-07-19 | 2013-02-04 | Fujitsu Ltd | Heat dissipation module and electronic device |
| JP2019169675A (en) * | 2018-03-26 | 2019-10-03 | 京セラ株式会社 | Ceramic circuit board, package, and electronic apparatus |
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