JP3287992B2 - Package for storing semiconductor elements - Google Patents

Package for storing semiconductor elements

Info

Publication number
JP3287992B2
JP3287992B2 JP22824396A JP22824396A JP3287992B2 JP 3287992 B2 JP3287992 B2 JP 3287992B2 JP 22824396 A JP22824396 A JP 22824396A JP 22824396 A JP22824396 A JP 22824396A JP 3287992 B2 JP3287992 B2 JP 3287992B2
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring layer
metallized wiring
molybdenum
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP22824396A
Other languages
Japanese (ja)
Other versions
JPH1074862A (en
Inventor
義博 細井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP22824396A priority Critical patent/JP3287992B2/en
Publication of JPH1074862A publication Critical patent/JPH1074862A/en
Application granted granted Critical
Publication of JP3287992B2 publication Critical patent/JP3287992B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Semiconductor Lasers (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子を収容
する半導体素子収納用パッケージに関し、より詳細には
高周波用半導体素子を収容する半導体素子収納用パッケ
ージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device housing package for housing a semiconductor device, and more particularly to a semiconductor device housing package for housing a high frequency semiconductor device.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは一般に酸化アルミニウム質焼
結体から成り、上面に半導体素子を収容すための凹部及
びその凹部周辺から下面に導出するモリブデンから成る
メタライズ配線層を有する絶縁基体と、蓋体とから構成
されており、絶縁基体の凹部底面に半導体素子をガラス
・樹脂・ロウ材等の接着剤を介して接着固定するととも
に半導体素子の各電極をメタライズ配線層にボンディン
グワイヤを介して電気的に接続し、しかる後、絶縁基体
と蓋体とから成る容器内部に半導体素子を気密に封止す
ることによって製品としての半導体装置となり、前記メ
タライズ配線層で絶縁基体下面に導出した部位を外部電
気回路基板の配線導体に半田等を介して接続することに
より内部に収容する半導体素子が外部電気回路に接続さ
れることとなる。
2. Description of the Related Art Conventionally, a package for accommodating a semiconductor element for accommodating a semiconductor element is generally made of a sintered body of aluminum oxide. And a lid. The semiconductor element is bonded and fixed to the bottom surface of the concave portion of the insulating base via an adhesive such as glass, resin, brazing material, and the like. The electrodes are electrically connected to the metallization wiring layer via bonding wires, and thereafter, the semiconductor element is hermetically sealed in a container formed of an insulating base and a lid, thereby forming a semiconductor device as a product. The part led out to the lower surface of the insulating base in the wiring layer is housed inside by connecting to the wiring conductor of the external electric circuit board via solder or the like. So that the semiconductor element is connected to an external electric circuit.

【0003】また、かかる従来の半導体素子収納用パッ
ケージは、モリブデンから成るメタライズ配線層が酸化
腐蝕することを防止するとともにメタライズ配線層とボ
ンディングワイヤとの接続及びメタライズ配線層と外部
電気回路基板の配線導体との接続を良好とするために、
メタライズ配線導体の露出表面にニッケルめっき層なら
びに必要に応じて更に金めっき層が鍍着されている。
Further, such a conventional package for accommodating a semiconductor element prevents the metallized wiring layer made of molybdenum from being oxidized and corroded, and also connects the metallized wiring layer to the bonding wire and connects the metallized wiring layer to the external electric circuit board. To improve the connection with the conductor,
A nickel plating layer and, if necessary, a gold plating layer are further plated on the exposed surface of the metallized wiring conductor.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、かかる
従来の半導体素子収納用パッケージによれば、メタライ
ズ配線層に鍍着されたニッケルめっき層が磁性を有して
おり、そのニッケルめっき層が有する磁性のためにメタ
ライズ配線層のインダクタンスが大きなものとなること
から、内部に高速作動する半導体素子を収容し、その半
導体素子にメタライズ配線層を介して高速の信号を入出
力すると、メタライズ配線層の大きなインダクタンスに
起因して信号の波形が乱れ、その結果、内部に収容する
半導体素子を正常に作動させることが不可となってしま
うという欠点を有していた。
However, according to such a conventional package for accommodating a semiconductor element, the nickel plating layer plated on the metallized wiring layer has a magnetic property, and the nickel plating layer has a magnetic property. Therefore, if a semiconductor element that operates at a high speed is accommodated inside and a high-speed signal is input and output to and from the semiconductor element through the metallization wiring layer, the inductance of the metallization wiring layer becomes large. As a result, the waveform of the signal is disturbed, and as a result, it becomes impossible to normally operate the semiconductor element housed therein.

【0005】本発明の目的は、上記の欠点を解消し、高
速の信号を正確に伝搬させることができる高周波用半導
体素子に好適な半導体素子収納用パッケージを提供する
ことにある。
An object of the present invention is to provide a semiconductor element housing package suitable for a high-frequency semiconductor element capable of solving the above-mentioned disadvantages and accurately transmitting a high-speed signal.

【0006】[0006]

【課題を解決するための手段】本発明の半導体素子収納
用パッケージは、半導体素子を収容する絶縁容器に半導
体素子を外部電気回路に接続するためのモリブデンメタ
ライズ配線層を被着形成するとともに該モリブデンメタ
ライズ配線層表面にニッケルめっき層を鍍着させて成る
半導体素子収納用パッケージであって、前記ニッケルめ
っき層は、その内部にモリブデンを単位体積当り10重量
%以上含有せしめてあることを特徴とするものである。
According to the present invention, there is provided a package for accommodating a semiconductor element, wherein a molybdenum metallized wiring layer for connecting the semiconductor element to an external electric circuit is formed on an insulating container for accommodating the semiconductor element. What is claimed is: 1. A package for accommodating a semiconductor element comprising a metallized wiring layer having a nickel plating layer plated on a surface thereof, wherein the nickel plating layer contains molybdenum in a content of 10% by weight or more per unit volume. Things.

【0007】本発明の半導体素子収納用パッケージによ
れば、モリブデンメタライズ配線層表面に鍍着させたニ
ッケルめっき層はモリブデンを10重量%以上含有せしめ
てあることから略非磁性となり、その結果、メタライズ
配線層のインダクタンスが大きなものとなることがな
く、内部に収容した半導体素子にメタライズ配線層によ
り高速の信号を正確に伝搬させることができる。
According to the semiconductor device housing package of the present invention, the nickel plating layer plated on the surface of the molybdenum metallized wiring layer contains molybdenum in an amount of 10% by weight or more, and thus becomes substantially non-magnetic. The inductance of the wiring layer does not become large, and a high-speed signal can be accurately transmitted to the semiconductor element housed therein by the metallized wiring layer.

【0008】[0008]

【発明の実施の形態】次に本発明を添付図面に基づき詳
細に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the accompanying drawings.

【0009】図1は本発明の半導体素子収納用パッケー
ジの実施の形態の一例を示す断面図であり、同図におい
て1は絶縁基体、2は蓋体である。この絶縁基体1と蓋
体2とで半導体素子3を収容する容器4が構成される。
FIG. 1 is a sectional view showing an example of an embodiment of a package for accommodating a semiconductor element according to the present invention. In FIG. 1, reference numeral 1 denotes an insulating base, and 2 denotes a lid. The insulating base 1 and the lid 2 constitute a container 4 for housing the semiconductor element 3.

【0010】絶縁基体1は、酸化アルミニウム質焼結体
・窒化アルミニウム質焼結体・ムライト質焼結体・炭化
珪素質焼結体・ガラスセラミック焼結体等の電気絶縁材
料から成り、その上面に凹部1aを有し、凹部1a底面
には半導体素子3がガラス・樹脂・ロウ材等の接着剤を
介して接着固定される。
The insulating substrate 1 is made of an electrically insulating material such as an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon carbide sintered body, a glass ceramic sintered body, and the like. The semiconductor element 3 is bonded and fixed to the bottom surface of the concave portion 1a via an adhesive such as glass, resin, or brazing material.

【0011】絶縁基体1は、例えば酸化アルミニウム質
焼結体から成る場合、酸化アルミニウム・酸化珪素・酸
化カルシウム・酸化マグネシウム等の原料粉末に適当な
有機バインダーや溶剤等を添加混合して泥漿状となすと
ともにこれを従来周知のドクターブレード法等を採用し
てシート状となすことによって複数枚のセラミックグリ
ーンシートを得、しかる後、複数枚のセラミックグリー
ンシートの各々に適当な打ち抜き加工を施すとともにこ
れらを上下に積層し、高温(約1600℃)で焼成すること
によって製作される。
When the insulating substrate 1 is made of, for example, an aluminum oxide sintered body, a suitable organic binder, a solvent, or the like is added to a raw material powder such as aluminum oxide, silicon oxide, calcium oxide, magnesium oxide, etc., and mixed to form a slurry. In addition, a plurality of ceramic green sheets are obtained by adopting a conventionally known doctor blade method or the like into a sheet shape, and thereafter, a plurality of ceramic green sheets are subjected to appropriate punching and Are stacked on top of each other and fired at a high temperature (about 1600 ° C.).

【0012】また絶縁基体1は、凹部1a周辺から下面
にかけて複数個のメタライズ配線層5が被着形成されて
おり、それらメタライズ配線層5の凹部1a周辺の部位
には半導体素子3の各電極がボンディングワイヤ6を介
して電気的に接続され、また絶縁基体1下面に導出され
た部位は外部電気回路基板の配線導体に半田等を介して
電気的に接続される。
A plurality of metallized wiring layers 5 are formed on the insulating substrate 1 from the periphery of the concave portion 1a to the lower surface, and each electrode of the semiconductor element 3 is formed at a portion of the metallized wiring layer 5 around the concave portion 1a. The portion that is electrically connected via the bonding wire 6 and that is led out to the lower surface of the insulating base 1 is electrically connected to the wiring conductor of the external electric circuit board via solder or the like.

【0013】メタライズ配線層5はモリブデンから成
り、モリブデン粉末に適当な有機バインダーや溶剤等を
添加混合して得た金属ペーストを、絶縁基体1となるセ
ラミックグリーンシートに予め従来周知のスクリーン印
刷法等により所定パターンに印刷塗布しておくことによ
って、絶縁基体1の凹部1a周辺から下面にかけて被着
形成される。
The metallized wiring layer 5 is made of molybdenum. A metal paste obtained by adding a suitable organic binder or solvent to molybdenum powder is mixed on a ceramic green sheet serving as the insulating substrate 1 in advance by a screen printing method known in the art. By printing and applying a predetermined pattern on the insulating substrate 1, the insulating substrate 1 is adhered and formed from the periphery to the lower surface of the concave portion 1a.

【0014】またメタライズ配線層5は、その露出する
表面にニッケルめっき層7が被着されており、このニッ
ケルめっき層7によりメタライズ配線層5が酸化腐食す
るのが防止されるとともにメタライズ配線層5とボンデ
ィングワイヤ6との接続及びメタライズ配線層5と外部
電気回路基板の配線導体との接続が良好なものとなって
いる。
The metallized wiring layer 5 is provided with a nickel plating layer 7 on the exposed surface. The nickel plating layer 7 prevents the metallized wiring layer 5 from being oxidized and corroded, and at the same time, prevents the metallized wiring layer 5 from being oxidized and corroded. And the bonding wires 6 and the metallized wiring layer 5 and the wiring conductors of the external electric circuit board are connected well.

【0015】なお、ニッケルめっき層7は、従来周知の
電解めっき法や無電解めっき法を採用して1〜10μm程
度の厚みに鍍着される。
The nickel plating layer 7 is plated to a thickness of about 1 to 10 μm by using a conventionally known electrolytic plating method or electroless plating method.

【0016】また、ニッケルめっき層7にはその内部に
モリブデンを単位体積当り10重量%以上含有せしめてあ
る。ここで単位体積当りとはニッケルメッキ層7の体積
1μm3 当りのことをいうが、モリブデン含有量は単位
体積当り10重量%以上であるので、ニッケルメッキ層7
の任意の体積当りあるいは全体積で見ても10重量%以上
となることは当然である。
The nickel plating layer 7 contains molybdenum in an amount of 10% by weight or more per unit volume. Here, “per unit volume” means per 1 μm 3 of the volume of the nickel plating layer 7. Since the molybdenum content is 10% by weight or more per unit volume,
Naturally, it is 10% by weight or more per arbitrary volume or in total volume.

【0017】ニッケルめっき層7は、モリブデンを10重
量%以上含有せしめてあることから、その磁性が極めて
弱く略非磁性となっており、その磁性によってメタライ
ズ配線層5のインダクタンスを大きなものとすることは
ない。従って、本発明の半導体素子収納用パッケージに
よれば、メタライズ配線層5により高速の信号を正確に
伝搬させることができ、内部に収容する半導体素子3を
正確に作動させることができる。
Since the nickel plating layer 7 contains 10% by weight or more of molybdenum, its magnetism is extremely weak and almost non-magnetic, and the magnetism increases the inductance of the metallized wiring layer 5. There is no. Therefore, according to the semiconductor element housing package of the present invention, a high-speed signal can be accurately propagated by the metallized wiring layer 5, and the semiconductor element 3 housed therein can be operated accurately.

【0018】なお、ニッケルめっき層7に含有せしめる
モリブデンの含有量が10重量%未満ではニッケルめっき
層7の磁性を極めて弱いものとして略非磁性となすこと
ができないことから、ニッケルめっき層7に含有せしめ
るモリブデンの含有量は10重量%以上とすることが好ま
しく、更にはモリブデンの含有量が12重量%以上である
と実質的に磁性を有しないことからモリブデンの含有量
が12重量%以上であることより好ましい。一方、モリブ
デンの含有量が30重量%を超えるとメタライズ配線層5
とボンディングワイヤ6との接続及びメタライズ配線層
5と外部電気回路基板との接続が困難となることからモ
リブデンの含有量は上記範囲内で更に30重量%以下であ
ることが好ましい。
If the content of molybdenum to be contained in the nickel plating layer 7 is less than 10% by weight, the magnetism of the nickel plating layer 7 is extremely weak and cannot be made substantially non-magnetic. The content of molybdenum is preferably at least 10% by weight. Further, when the content of molybdenum is at least 12% by weight, there is substantially no magnetism, so the content of molybdenum is at least 12% by weight. More preferred. On the other hand, if the molybdenum content exceeds 30% by weight, the metallized wiring layer 5
It is preferable that the content of molybdenum is further 30% by weight or less within the above range, since it becomes difficult to connect the metal wire and the bonding wire 6 and the metallized wiring layer 5 to the external electric circuit board.

【0019】ニッケルめっき層7にモリブデンを10重量
%以上含有せしめるには、メタライズ配線層5の表面に
ニッケルめっき層7を鍍着させた後、これを 900〜1100
℃の温度で30分〜1時間熱処理してメタライズ配線層5
中のモリブデンをニッケルめっき層7中に熱拡散させる
方法、あるいは例えば硫酸ニッケル50〜90g/l、モリ
ブデン酸ナトリウム40〜50g/l、クエン酸ナトリウム
5〜10g/l、クエン酸80〜100 g/lを含むめっき浴
中で電解めっきする方法や、更にこのめっき浴中に次亜
燐酸ナトリウムやジメチルアミンボラン等の還元剤を添
加しためっき浴中で無電解めっきする方法が採用され
る。
In order to make the nickel plating layer 7 contain 10% by weight or more of molybdenum, the nickel plating layer 7 is plated on the surface of the metallized wiring layer 5 and then 900-1100.
Heat treatment at a temperature of 30 ° C. for 30 minutes to 1 hour to form a metallized wiring layer 5
A method of thermally diffusing the molybdenum therein into the nickel plating layer 7, or for example, nickel sulfate 50 to 90 g / l, sodium molybdate 40 to 50 g / l, sodium citrate 5 to 10 g / l, citric acid 80 to 100 g / l and a method of electroless plating in a plating bath containing a reducing agent such as sodium hypophosphite or dimethylamine borane added to the plating bath.

【0020】かくして本発明の半導体素子収納用パッケ
ージによれば、絶縁基体1の凹部1a底面に半導体素子
3をガラス・樹脂・ロウ材等の接着剤を介して接着固定
するとともに半導体素子3の各電極をメタライズ配線層
5にボンディングワイヤ6を介して電気的に接続し、し
かる後、絶縁基体1の上面に蓋体2をガラス・樹脂・ロ
ウ材等の封止材を介して接合させて、絶縁基体1と蓋体
2とから成る容器4内部に半導体素子3を気密に収容す
ることによって製品としての半導体装置が完成する。
Thus, according to the semiconductor device housing package of the present invention, the semiconductor device 3 is bonded and fixed to the bottom surface of the concave portion 1a of the insulating base 1 with an adhesive such as glass, resin, brazing material, etc. The electrode is electrically connected to the metallized wiring layer 5 via the bonding wire 6, and then the lid 2 is joined to the upper surface of the insulating base 1 via a sealing material such as glass, resin, brazing material, etc. A semiconductor device as a product is completed by hermetically housing the semiconductor element 3 in a container 4 including the insulating base 1 and the lid 2.

【0021】なお、本発明は上述の実施の形態に限定さ
れるものではなく、本発明の要旨を逸脱しない範囲であ
れば種々の変更は可能である。例えば、ニッケルめっき
層の上に更に金めっき層を 0.1〜3μm程度の厚みに鍍
着させても良く、この場合、メタライズ配線層が酸化腐
食するのを更に有効に防止することができるとともにメ
タライズ配線層とボンディングワイヤとの接続及びメタ
ライズ配線層と外部電気回路基板の配線導体との接続を
更に良好なものとすることができる。
The present invention is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present invention. For example, a gold plating layer may be further plated on the nickel plating layer to a thickness of about 0.1 to 3 μm. In this case, the metallized wiring layer can be more effectively prevented from being oxidized and corroded, and the metallized wiring layer can be more effectively prevented. The connection between the layer and the bonding wire and the connection between the metallized wiring layer and the wiring conductor of the external electric circuit board can be further improved.

【0022】[0022]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、メタライズ配線層に鍍着させたニッケルめっき
層中にモリブデンを単位体積当り10重量%以上含有せし
めたことからニッケルめっき層が略非磁性となり、その
結果、メタライズ配線層のインダクタンスが大きなもの
となることがなく、メタライズ配線層により高速の信号
を正確に伝搬させることができ、内部に収容する半導体
素子を正確に作動させることができ、高周波用半導体素
子に好適な半導体素子収納用パッケージを提供すること
ができた。
According to the package for housing a semiconductor device of the present invention, the nickel plating layer plated on the metallized wiring layer contains molybdenum at 10% by weight or more per unit volume. As a result, the inductance of the metallized wiring layer does not become large, and high-speed signals can be accurately propagated by the metallized wiring layer, and the semiconductor element housed therein can be operated accurately. Thus, a semiconductor element storage package suitable for a high-frequency semiconductor element can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の半導体素子収納用パッケージの実施の
形態の一例を示す断面図である。
FIG. 1 is a cross-sectional view showing an example of an embodiment of a semiconductor element storage package according to the present invention.

【符号の説明】[Explanation of symbols]

1・・・絶縁基体 2・・・蓋体 3・・・半導体素子 4・・・容器 5・・・メタライズ配線層 7・・・ニッケルめっき層 DESCRIPTION OF SYMBOLS 1 ... Insulating base 2 ... Lid 3 ... Semiconductor element 4 ... Container 5 ... Metallized wiring layer 7 ... Nickel plating layer

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体素子を収容する絶縁容器に半導体
素子を外部電気回路に接続するためのモリブデンメタラ
イズ配線層を被着形成するとともに該モリブデンメタラ
イズ配線層表面にニッケルめっき層を鍍着させて成る半
導体素子収納用パッケージであって、前記ニッケルめっ
き層は、その内部にモリブデンを単位体積当り10重量
%以上含有せしめてあることを特徴とする半導体素子収
納用パッケージ。
A molybdenum metallized wiring layer for connecting a semiconductor element to an external electric circuit is formed on an insulating container containing the semiconductor element, and a nickel plating layer is plated on the surface of the molybdenum metallized wiring layer. A package for storing a semiconductor element, wherein the nickel plating layer contains molybdenum in a content of 10% by weight or more per unit volume.
JP22824396A 1996-08-29 1996-08-29 Package for storing semiconductor elements Expired - Fee Related JP3287992B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22824396A JP3287992B2 (en) 1996-08-29 1996-08-29 Package for storing semiconductor elements

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22824396A JP3287992B2 (en) 1996-08-29 1996-08-29 Package for storing semiconductor elements

Publications (2)

Publication Number Publication Date
JPH1074862A JPH1074862A (en) 1998-03-17
JP3287992B2 true JP3287992B2 (en) 2002-06-04

Family

ID=16873411

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22824396A Expired - Fee Related JP3287992B2 (en) 1996-08-29 1996-08-29 Package for storing semiconductor elements

Country Status (1)

Country Link
JP (1) JP3287992B2 (en)

Also Published As

Publication number Publication date
JPH1074862A (en) 1998-03-17

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